1631c5347SAlexander Shiyan /* 2631c5347SAlexander Shiyan * Cirrus Logic CLPS711X CLK driver 3631c5347SAlexander Shiyan * 4631c5347SAlexander Shiyan * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> 5631c5347SAlexander Shiyan * 6631c5347SAlexander Shiyan * This program is free software; you can redistribute it and/or modify 7631c5347SAlexander Shiyan * it under the terms of the GNU General Public License as published by 8631c5347SAlexander Shiyan * the Free Software Foundation; either version 2 of the License, or 9631c5347SAlexander Shiyan * (at your option) any later version. 10631c5347SAlexander Shiyan */ 11631c5347SAlexander Shiyan 12631c5347SAlexander Shiyan #include <linux/clk-provider.h> 13631c5347SAlexander Shiyan #include <linux/clkdev.h> 14631c5347SAlexander Shiyan #include <linux/io.h> 15631c5347SAlexander Shiyan #include <linux/ioport.h> 16631c5347SAlexander Shiyan #include <linux/of_address.h> 17631c5347SAlexander Shiyan #include <linux/slab.h> 18631c5347SAlexander Shiyan #include <linux/mfd/syscon/clps711x.h> 19631c5347SAlexander Shiyan 20631c5347SAlexander Shiyan #include <dt-bindings/clock/clps711x-clock.h> 21631c5347SAlexander Shiyan 22631c5347SAlexander Shiyan #define CLPS711X_SYSCON1 (0x0100) 23631c5347SAlexander Shiyan #define CLPS711X_SYSCON2 (0x1100) 24631c5347SAlexander Shiyan #define CLPS711X_SYSFLG2 (CLPS711X_SYSCON2 + SYSFLG_OFFSET) 25631c5347SAlexander Shiyan #define CLPS711X_PLLR (0xa5a8) 26631c5347SAlexander Shiyan 27631c5347SAlexander Shiyan #define CLPS711X_EXT_FREQ (13000000) 28631c5347SAlexander Shiyan #define CLPS711X_OSC_FREQ (3686400) 29631c5347SAlexander Shiyan 30631c5347SAlexander Shiyan static const struct clk_div_table spi_div_table[] = { 31631c5347SAlexander Shiyan { .val = 0, .div = 32, }, 32631c5347SAlexander Shiyan { .val = 1, .div = 8, }, 33631c5347SAlexander Shiyan { .val = 2, .div = 2, }, 34631c5347SAlexander Shiyan { .val = 3, .div = 1, }, 35631c5347SAlexander Shiyan }; 36631c5347SAlexander Shiyan 37631c5347SAlexander Shiyan static const struct clk_div_table timer_div_table[] = { 38631c5347SAlexander Shiyan { .val = 0, .div = 256, }, 39631c5347SAlexander Shiyan { .val = 1, .div = 1, }, 40631c5347SAlexander Shiyan }; 41631c5347SAlexander Shiyan 42631c5347SAlexander Shiyan struct clps711x_clk { 43631c5347SAlexander Shiyan struct clk_onecell_data clk_data; 44631c5347SAlexander Shiyan spinlock_t lock; 45631c5347SAlexander Shiyan struct clk *clks[CLPS711X_CLK_MAX]; 46631c5347SAlexander Shiyan }; 47631c5347SAlexander Shiyan 48631c5347SAlexander Shiyan static struct clps711x_clk * __init _clps711x_clk_init(void __iomem *base, 49631c5347SAlexander Shiyan u32 fref) 50631c5347SAlexander Shiyan { 51631c5347SAlexander Shiyan u32 tmp, f_cpu, f_pll, f_bus, f_tim, f_pwm, f_spi; 52631c5347SAlexander Shiyan struct clps711x_clk *clps711x_clk; 53631c5347SAlexander Shiyan unsigned i; 54631c5347SAlexander Shiyan 55631c5347SAlexander Shiyan if (!base) 56631c5347SAlexander Shiyan return ERR_PTR(-ENOMEM); 57631c5347SAlexander Shiyan 58631c5347SAlexander Shiyan clps711x_clk = kzalloc(sizeof(*clps711x_clk), GFP_KERNEL); 59631c5347SAlexander Shiyan if (!clps711x_clk) 60631c5347SAlexander Shiyan return ERR_PTR(-ENOMEM); 61631c5347SAlexander Shiyan 62631c5347SAlexander Shiyan spin_lock_init(&clps711x_clk->lock); 63631c5347SAlexander Shiyan 64631c5347SAlexander Shiyan /* Read PLL multiplier value and sanity check */ 65631c5347SAlexander Shiyan tmp = readl(base + CLPS711X_PLLR) >> 24; 66631c5347SAlexander Shiyan if (((tmp >= 10) && (tmp <= 50)) || !fref) 67631c5347SAlexander Shiyan f_pll = DIV_ROUND_UP(CLPS711X_OSC_FREQ * tmp, 2); 68631c5347SAlexander Shiyan else 69631c5347SAlexander Shiyan f_pll = fref; 70631c5347SAlexander Shiyan 71631c5347SAlexander Shiyan tmp = readl(base + CLPS711X_SYSFLG2); 72631c5347SAlexander Shiyan if (tmp & SYSFLG2_CKMODE) { 73631c5347SAlexander Shiyan f_cpu = CLPS711X_EXT_FREQ; 74631c5347SAlexander Shiyan f_bus = CLPS711X_EXT_FREQ; 75631c5347SAlexander Shiyan f_spi = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 96); 76631c5347SAlexander Shiyan f_pll = 0; 77631c5347SAlexander Shiyan f_pwm = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 128); 78631c5347SAlexander Shiyan } else { 79631c5347SAlexander Shiyan f_cpu = f_pll; 80631c5347SAlexander Shiyan if (f_cpu > 36864000) 81631c5347SAlexander Shiyan f_bus = DIV_ROUND_UP(f_cpu, 2); 82631c5347SAlexander Shiyan else 83631c5347SAlexander Shiyan f_bus = 36864000 / 2; 84631c5347SAlexander Shiyan f_spi = DIV_ROUND_CLOSEST(f_cpu, 576); 85631c5347SAlexander Shiyan f_pwm = DIV_ROUND_CLOSEST(f_cpu, 768); 86631c5347SAlexander Shiyan } 87631c5347SAlexander Shiyan 88631c5347SAlexander Shiyan if (tmp & SYSFLG2_CKMODE) { 89631c5347SAlexander Shiyan if (readl(base + CLPS711X_SYSCON2) & SYSCON2_OSTB) 90631c5347SAlexander Shiyan f_tim = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 26); 91631c5347SAlexander Shiyan else 92631c5347SAlexander Shiyan f_tim = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 24); 93631c5347SAlexander Shiyan } else 94631c5347SAlexander Shiyan f_tim = DIV_ROUND_CLOSEST(f_cpu, 144); 95631c5347SAlexander Shiyan 96631c5347SAlexander Shiyan tmp = readl(base + CLPS711X_SYSCON1); 97631c5347SAlexander Shiyan /* Timer1 in free running mode. 98631c5347SAlexander Shiyan * Counter will wrap around to 0xffff when it underflows 99631c5347SAlexander Shiyan * and will continue to count down. 100631c5347SAlexander Shiyan */ 101631c5347SAlexander Shiyan tmp &= ~(SYSCON1_TC1M | SYSCON1_TC1S); 102631c5347SAlexander Shiyan /* Timer2 in prescale mode. 103631c5347SAlexander Shiyan * Value writen is automatically re-loaded when 104631c5347SAlexander Shiyan * the counter underflows. 105631c5347SAlexander Shiyan */ 106631c5347SAlexander Shiyan tmp |= SYSCON1_TC2M | SYSCON1_TC2S; 107631c5347SAlexander Shiyan writel(tmp, base + CLPS711X_SYSCON1); 108631c5347SAlexander Shiyan 109631c5347SAlexander Shiyan clps711x_clk->clks[CLPS711X_CLK_DUMMY] = 11026659adaSStephen Boyd clk_register_fixed_rate(NULL, "dummy", NULL, 0, 0); 111631c5347SAlexander Shiyan clps711x_clk->clks[CLPS711X_CLK_CPU] = 11226659adaSStephen Boyd clk_register_fixed_rate(NULL, "cpu", NULL, 0, f_cpu); 113631c5347SAlexander Shiyan clps711x_clk->clks[CLPS711X_CLK_BUS] = 11426659adaSStephen Boyd clk_register_fixed_rate(NULL, "bus", NULL, 0, f_bus); 115631c5347SAlexander Shiyan clps711x_clk->clks[CLPS711X_CLK_PLL] = 11626659adaSStephen Boyd clk_register_fixed_rate(NULL, "pll", NULL, 0, f_pll); 117631c5347SAlexander Shiyan clps711x_clk->clks[CLPS711X_CLK_TIMERREF] = 11826659adaSStephen Boyd clk_register_fixed_rate(NULL, "timer_ref", NULL, 0, f_tim); 119631c5347SAlexander Shiyan clps711x_clk->clks[CLPS711X_CLK_TIMER1] = 120631c5347SAlexander Shiyan clk_register_divider_table(NULL, "timer1", "timer_ref", 0, 121631c5347SAlexander Shiyan base + CLPS711X_SYSCON1, 5, 1, 0, 122631c5347SAlexander Shiyan timer_div_table, &clps711x_clk->lock); 123631c5347SAlexander Shiyan clps711x_clk->clks[CLPS711X_CLK_TIMER2] = 124631c5347SAlexander Shiyan clk_register_divider_table(NULL, "timer2", "timer_ref", 0, 125631c5347SAlexander Shiyan base + CLPS711X_SYSCON1, 7, 1, 0, 126631c5347SAlexander Shiyan timer_div_table, &clps711x_clk->lock); 127631c5347SAlexander Shiyan clps711x_clk->clks[CLPS711X_CLK_PWM] = 12826659adaSStephen Boyd clk_register_fixed_rate(NULL, "pwm", NULL, 0, f_pwm); 129631c5347SAlexander Shiyan clps711x_clk->clks[CLPS711X_CLK_SPIREF] = 13026659adaSStephen Boyd clk_register_fixed_rate(NULL, "spi_ref", NULL, 0, f_spi); 131631c5347SAlexander Shiyan clps711x_clk->clks[CLPS711X_CLK_SPI] = 132631c5347SAlexander Shiyan clk_register_divider_table(NULL, "spi", "spi_ref", 0, 133631c5347SAlexander Shiyan base + CLPS711X_SYSCON1, 16, 2, 0, 134631c5347SAlexander Shiyan spi_div_table, &clps711x_clk->lock); 135631c5347SAlexander Shiyan clps711x_clk->clks[CLPS711X_CLK_UART] = 136631c5347SAlexander Shiyan clk_register_fixed_factor(NULL, "uart", "bus", 0, 1, 10); 137631c5347SAlexander Shiyan clps711x_clk->clks[CLPS711X_CLK_TICK] = 13826659adaSStephen Boyd clk_register_fixed_rate(NULL, "tick", NULL, 0, 64); 139631c5347SAlexander Shiyan for (i = 0; i < CLPS711X_CLK_MAX; i++) 140631c5347SAlexander Shiyan if (IS_ERR(clps711x_clk->clks[i])) 141631c5347SAlexander Shiyan pr_err("clk %i: register failed with %ld\n", 142631c5347SAlexander Shiyan i, PTR_ERR(clps711x_clk->clks[i])); 143631c5347SAlexander Shiyan 144631c5347SAlexander Shiyan return clps711x_clk; 145631c5347SAlexander Shiyan } 146631c5347SAlexander Shiyan 147631c5347SAlexander Shiyan void __init clps711x_clk_init(void __iomem *base) 148631c5347SAlexander Shiyan { 149631c5347SAlexander Shiyan struct clps711x_clk *clps711x_clk; 150631c5347SAlexander Shiyan 151631c5347SAlexander Shiyan clps711x_clk = _clps711x_clk_init(base, 73728000); 152631c5347SAlexander Shiyan 153631c5347SAlexander Shiyan BUG_ON(IS_ERR(clps711x_clk)); 154631c5347SAlexander Shiyan 155631c5347SAlexander Shiyan /* Clocksource */ 156631c5347SAlexander Shiyan clk_register_clkdev(clps711x_clk->clks[CLPS711X_CLK_TIMER1], 157631c5347SAlexander Shiyan NULL, "clps711x-timer.0"); 158631c5347SAlexander Shiyan clk_register_clkdev(clps711x_clk->clks[CLPS711X_CLK_TIMER2], 159631c5347SAlexander Shiyan NULL, "clps711x-timer.1"); 160631c5347SAlexander Shiyan 161631c5347SAlexander Shiyan /* Drivers */ 162631c5347SAlexander Shiyan clk_register_clkdev(clps711x_clk->clks[CLPS711X_CLK_PWM], 163631c5347SAlexander Shiyan NULL, "clps711x-pwm"); 164631c5347SAlexander Shiyan clk_register_clkdev(clps711x_clk->clks[CLPS711X_CLK_UART], 165631c5347SAlexander Shiyan NULL, "clps711x-uart.0"); 166631c5347SAlexander Shiyan clk_register_clkdev(clps711x_clk->clks[CLPS711X_CLK_UART], 167631c5347SAlexander Shiyan NULL, "clps711x-uart.1"); 168631c5347SAlexander Shiyan } 169631c5347SAlexander Shiyan 170631c5347SAlexander Shiyan #ifdef CONFIG_OF 171631c5347SAlexander Shiyan static void __init clps711x_clk_init_dt(struct device_node *np) 172631c5347SAlexander Shiyan { 173631c5347SAlexander Shiyan void __iomem *base = of_iomap(np, 0); 174631c5347SAlexander Shiyan struct clps711x_clk *clps711x_clk; 175631c5347SAlexander Shiyan u32 fref = 0; 176631c5347SAlexander Shiyan 177631c5347SAlexander Shiyan WARN_ON(of_property_read_u32(np, "startup-frequency", &fref)); 178631c5347SAlexander Shiyan 179631c5347SAlexander Shiyan clps711x_clk = _clps711x_clk_init(base, fref); 180631c5347SAlexander Shiyan BUG_ON(IS_ERR(clps711x_clk)); 181631c5347SAlexander Shiyan 182631c5347SAlexander Shiyan clps711x_clk->clk_data.clks = clps711x_clk->clks; 183631c5347SAlexander Shiyan clps711x_clk->clk_data.clk_num = CLPS711X_CLK_MAX; 184631c5347SAlexander Shiyan of_clk_add_provider(np, of_clk_src_onecell_get, 185631c5347SAlexander Shiyan &clps711x_clk->clk_data); 186631c5347SAlexander Shiyan } 187893b7798SAlexander Shiyan CLK_OF_DECLARE(clps711x, "cirrus,ep7209-clk", clps711x_clk_init_dt); 188631c5347SAlexander Shiyan #endif 189