12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2631c5347SAlexander Shiyan /* 3631c5347SAlexander Shiyan * Cirrus Logic CLPS711X CLK driver 4631c5347SAlexander Shiyan * 5631c5347SAlexander Shiyan * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> 6631c5347SAlexander Shiyan */ 7631c5347SAlexander Shiyan 8631c5347SAlexander Shiyan #include <linux/clk-provider.h> 9631c5347SAlexander Shiyan #include <linux/clkdev.h> 10631c5347SAlexander Shiyan #include <linux/io.h> 11631c5347SAlexander Shiyan #include <linux/ioport.h> 12631c5347SAlexander Shiyan #include <linux/of_address.h> 13631c5347SAlexander Shiyan #include <linux/slab.h> 14631c5347SAlexander Shiyan #include <linux/mfd/syscon/clps711x.h> 15631c5347SAlexander Shiyan 16631c5347SAlexander Shiyan #include <dt-bindings/clock/clps711x-clock.h> 17631c5347SAlexander Shiyan 18631c5347SAlexander Shiyan #define CLPS711X_SYSCON1 (0x0100) 19631c5347SAlexander Shiyan #define CLPS711X_SYSCON2 (0x1100) 20631c5347SAlexander Shiyan #define CLPS711X_SYSFLG2 (CLPS711X_SYSCON2 + SYSFLG_OFFSET) 21631c5347SAlexander Shiyan #define CLPS711X_PLLR (0xa5a8) 22631c5347SAlexander Shiyan 23631c5347SAlexander Shiyan #define CLPS711X_EXT_FREQ (13000000) 24631c5347SAlexander Shiyan #define CLPS711X_OSC_FREQ (3686400) 25631c5347SAlexander Shiyan 26631c5347SAlexander Shiyan static const struct clk_div_table spi_div_table[] = { 27631c5347SAlexander Shiyan { .val = 0, .div = 32, }, 28631c5347SAlexander Shiyan { .val = 1, .div = 8, }, 29631c5347SAlexander Shiyan { .val = 2, .div = 2, }, 30631c5347SAlexander Shiyan { .val = 3, .div = 1, }, 31631c5347SAlexander Shiyan }; 32631c5347SAlexander Shiyan 33631c5347SAlexander Shiyan static const struct clk_div_table timer_div_table[] = { 34631c5347SAlexander Shiyan { .val = 0, .div = 256, }, 35631c5347SAlexander Shiyan { .val = 1, .div = 1, }, 36631c5347SAlexander Shiyan }; 37631c5347SAlexander Shiyan 38631c5347SAlexander Shiyan struct clps711x_clk { 39631c5347SAlexander Shiyan spinlock_t lock; 40f48d947aSStephen Boyd struct clk_hw_onecell_data clk_data; 41631c5347SAlexander Shiyan }; 42631c5347SAlexander Shiyan 4331cc9e09SAlexander Shiyan static void __init clps711x_clk_init_dt(struct device_node *np) 44631c5347SAlexander Shiyan { 4531cc9e09SAlexander Shiyan u32 tmp, f_cpu, f_pll, f_bus, f_tim, f_pwm, f_spi, fref = 0; 46631c5347SAlexander Shiyan struct clps711x_clk *clps711x_clk; 4731cc9e09SAlexander Shiyan void __iomem *base; 48631c5347SAlexander Shiyan 4931cc9e09SAlexander Shiyan WARN_ON(of_property_read_u32(np, "startup-frequency", &fref)); 5031cc9e09SAlexander Shiyan 5131cc9e09SAlexander Shiyan base = of_iomap(np, 0); 5231cc9e09SAlexander Shiyan BUG_ON(!base); 53631c5347SAlexander Shiyan 54acafe7e3SKees Cook clps711x_clk = kzalloc(struct_size(clps711x_clk, clk_data.hws, 55acafe7e3SKees Cook CLPS711X_CLK_MAX), 56f48d947aSStephen Boyd GFP_KERNEL); 5731cc9e09SAlexander Shiyan BUG_ON(!clps711x_clk); 58631c5347SAlexander Shiyan 59631c5347SAlexander Shiyan spin_lock_init(&clps711x_clk->lock); 60631c5347SAlexander Shiyan 61631c5347SAlexander Shiyan /* Read PLL multiplier value and sanity check */ 62631c5347SAlexander Shiyan tmp = readl(base + CLPS711X_PLLR) >> 24; 63631c5347SAlexander Shiyan if (((tmp >= 10) && (tmp <= 50)) || !fref) 64631c5347SAlexander Shiyan f_pll = DIV_ROUND_UP(CLPS711X_OSC_FREQ * tmp, 2); 65631c5347SAlexander Shiyan else 66631c5347SAlexander Shiyan f_pll = fref; 67631c5347SAlexander Shiyan 68631c5347SAlexander Shiyan tmp = readl(base + CLPS711X_SYSFLG2); 69631c5347SAlexander Shiyan if (tmp & SYSFLG2_CKMODE) { 70631c5347SAlexander Shiyan f_cpu = CLPS711X_EXT_FREQ; 71631c5347SAlexander Shiyan f_bus = CLPS711X_EXT_FREQ; 72631c5347SAlexander Shiyan f_spi = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 96); 73631c5347SAlexander Shiyan f_pll = 0; 74631c5347SAlexander Shiyan f_pwm = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 128); 75631c5347SAlexander Shiyan } else { 76631c5347SAlexander Shiyan f_cpu = f_pll; 77631c5347SAlexander Shiyan if (f_cpu > 36864000) 78631c5347SAlexander Shiyan f_bus = DIV_ROUND_UP(f_cpu, 2); 79631c5347SAlexander Shiyan else 80631c5347SAlexander Shiyan f_bus = 36864000 / 2; 81631c5347SAlexander Shiyan f_spi = DIV_ROUND_CLOSEST(f_cpu, 576); 82631c5347SAlexander Shiyan f_pwm = DIV_ROUND_CLOSEST(f_cpu, 768); 83631c5347SAlexander Shiyan } 84631c5347SAlexander Shiyan 85631c5347SAlexander Shiyan if (tmp & SYSFLG2_CKMODE) { 86631c5347SAlexander Shiyan if (readl(base + CLPS711X_SYSCON2) & SYSCON2_OSTB) 87631c5347SAlexander Shiyan f_tim = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 26); 88631c5347SAlexander Shiyan else 89631c5347SAlexander Shiyan f_tim = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 24); 90631c5347SAlexander Shiyan } else 91631c5347SAlexander Shiyan f_tim = DIV_ROUND_CLOSEST(f_cpu, 144); 92631c5347SAlexander Shiyan 93631c5347SAlexander Shiyan tmp = readl(base + CLPS711X_SYSCON1); 94631c5347SAlexander Shiyan /* Timer1 in free running mode. 95631c5347SAlexander Shiyan * Counter will wrap around to 0xffff when it underflows 96631c5347SAlexander Shiyan * and will continue to count down. 97631c5347SAlexander Shiyan */ 98631c5347SAlexander Shiyan tmp &= ~(SYSCON1_TC1M | SYSCON1_TC1S); 99631c5347SAlexander Shiyan /* Timer2 in prescale mode. 100631c5347SAlexander Shiyan * Value writen is automatically re-loaded when 101631c5347SAlexander Shiyan * the counter underflows. 102631c5347SAlexander Shiyan */ 103631c5347SAlexander Shiyan tmp |= SYSCON1_TC2M | SYSCON1_TC2S; 104631c5347SAlexander Shiyan writel(tmp, base + CLPS711X_SYSCON1); 105631c5347SAlexander Shiyan 106f48d947aSStephen Boyd clps711x_clk->clk_data.hws[CLPS711X_CLK_DUMMY] = 107f48d947aSStephen Boyd clk_hw_register_fixed_rate(NULL, "dummy", NULL, 0, 0); 108f48d947aSStephen Boyd clps711x_clk->clk_data.hws[CLPS711X_CLK_CPU] = 109f48d947aSStephen Boyd clk_hw_register_fixed_rate(NULL, "cpu", NULL, 0, f_cpu); 110f48d947aSStephen Boyd clps711x_clk->clk_data.hws[CLPS711X_CLK_BUS] = 111f48d947aSStephen Boyd clk_hw_register_fixed_rate(NULL, "bus", NULL, 0, f_bus); 112f48d947aSStephen Boyd clps711x_clk->clk_data.hws[CLPS711X_CLK_PLL] = 113f48d947aSStephen Boyd clk_hw_register_fixed_rate(NULL, "pll", NULL, 0, f_pll); 114f48d947aSStephen Boyd clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMERREF] = 115f48d947aSStephen Boyd clk_hw_register_fixed_rate(NULL, "timer_ref", NULL, 0, f_tim); 116f48d947aSStephen Boyd clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER1] = 117f48d947aSStephen Boyd clk_hw_register_divider_table(NULL, "timer1", "timer_ref", 0, 118631c5347SAlexander Shiyan base + CLPS711X_SYSCON1, 5, 1, 0, 119631c5347SAlexander Shiyan timer_div_table, &clps711x_clk->lock); 120f48d947aSStephen Boyd clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER2] = 121f48d947aSStephen Boyd clk_hw_register_divider_table(NULL, "timer2", "timer_ref", 0, 122631c5347SAlexander Shiyan base + CLPS711X_SYSCON1, 7, 1, 0, 123631c5347SAlexander Shiyan timer_div_table, &clps711x_clk->lock); 124f48d947aSStephen Boyd clps711x_clk->clk_data.hws[CLPS711X_CLK_PWM] = 125f48d947aSStephen Boyd clk_hw_register_fixed_rate(NULL, "pwm", NULL, 0, f_pwm); 126f48d947aSStephen Boyd clps711x_clk->clk_data.hws[CLPS711X_CLK_SPIREF] = 127f48d947aSStephen Boyd clk_hw_register_fixed_rate(NULL, "spi_ref", NULL, 0, f_spi); 128f48d947aSStephen Boyd clps711x_clk->clk_data.hws[CLPS711X_CLK_SPI] = 129f48d947aSStephen Boyd clk_hw_register_divider_table(NULL, "spi", "spi_ref", 0, 130631c5347SAlexander Shiyan base + CLPS711X_SYSCON1, 16, 2, 0, 131631c5347SAlexander Shiyan spi_div_table, &clps711x_clk->lock); 132f48d947aSStephen Boyd clps711x_clk->clk_data.hws[CLPS711X_CLK_UART] = 133f48d947aSStephen Boyd clk_hw_register_fixed_factor(NULL, "uart", "bus", 0, 1, 10); 134f48d947aSStephen Boyd clps711x_clk->clk_data.hws[CLPS711X_CLK_TICK] = 135f48d947aSStephen Boyd clk_hw_register_fixed_rate(NULL, "tick", NULL, 0, 64); 13631cc9e09SAlexander Shiyan for (tmp = 0; tmp < CLPS711X_CLK_MAX; tmp++) 13731cc9e09SAlexander Shiyan if (IS_ERR(clps711x_clk->clk_data.hws[tmp])) 138631c5347SAlexander Shiyan pr_err("clk %i: register failed with %ld\n", 13931cc9e09SAlexander Shiyan tmp, PTR_ERR(clps711x_clk->clk_data.hws[tmp])); 140631c5347SAlexander Shiyan 141f48d947aSStephen Boyd clps711x_clk->clk_data.num = CLPS711X_CLK_MAX; 142f48d947aSStephen Boyd of_clk_add_hw_provider(np, of_clk_hw_onecell_get, 143631c5347SAlexander Shiyan &clps711x_clk->clk_data); 144631c5347SAlexander Shiyan } 145893b7798SAlexander Shiyan CLK_OF_DECLARE(clps711x, "cirrus,ep7209-clk", clps711x_clk_init_dt); 146