1 /* 2 * Driver for TI Multi PLL CDCE913/925/937/949 clock synthesizer 3 * 4 * This driver always connects the Y1 to the input clock, Y2/Y3 to PLL1, 5 * Y4/Y5 to PLL2, and so on. PLL frequency is set on a first-come-first-serve 6 * basis. Clients can directly request any frequency that the chip can 7 * deliver using the standard clk framework. In addition, the device can 8 * be configured and activated via the devicetree. 9 * 10 * Copyright (C) 2014, Topic Embedded Products 11 * Licenced under GPL 12 */ 13 #include <linux/clk.h> 14 #include <linux/clk-provider.h> 15 #include <linux/delay.h> 16 #include <linux/module.h> 17 #include <linux/i2c.h> 18 #include <linux/regmap.h> 19 #include <linux/slab.h> 20 #include <linux/gcd.h> 21 22 /* Each chip has different number of PLLs and outputs, for example: 23 * The CECE925 has 2 PLLs which can be routed through dividers to 5 outputs. 24 * Model this as 2 PLL clocks which are parents to the outputs. 25 */ 26 27 enum { 28 CDCE913, 29 CDCE925, 30 CDCE937, 31 CDCE949, 32 }; 33 34 struct clk_cdce925_chip_info { 35 int num_plls; 36 int num_outputs; 37 }; 38 39 static const struct clk_cdce925_chip_info clk_cdce925_chip_info_tbl[] = { 40 [CDCE913] = { .num_plls = 1, .num_outputs = 3 }, 41 [CDCE925] = { .num_plls = 2, .num_outputs = 5 }, 42 [CDCE937] = { .num_plls = 3, .num_outputs = 7 }, 43 [CDCE949] = { .num_plls = 4, .num_outputs = 9 }, 44 }; 45 46 #define MAX_NUMBER_OF_PLLS 4 47 #define MAX_NUMBER_OF_OUTPUTS 9 48 49 #define CDCE925_REG_GLOBAL1 0x01 50 #define CDCE925_REG_Y1SPIPDIVH 0x02 51 #define CDCE925_REG_PDIVL 0x03 52 #define CDCE925_REG_XCSEL 0x05 53 /* PLL parameters start at 0x10, steps of 0x10 */ 54 #define CDCE925_OFFSET_PLL 0x10 55 /* Add CDCE925_OFFSET_PLL * (pll) to these registers before sending */ 56 #define CDCE925_PLL_MUX_OUTPUTS 0x14 57 #define CDCE925_PLL_MULDIV 0x18 58 59 #define CDCE925_PLL_FREQUENCY_MIN 80000000ul 60 #define CDCE925_PLL_FREQUENCY_MAX 230000000ul 61 struct clk_cdce925_chip; 62 63 struct clk_cdce925_output { 64 struct clk_hw hw; 65 struct clk_cdce925_chip *chip; 66 u8 index; 67 u16 pdiv; /* 1..127 for Y2-Y9; 1..1023 for Y1 */ 68 }; 69 #define to_clk_cdce925_output(_hw) \ 70 container_of(_hw, struct clk_cdce925_output, hw) 71 72 struct clk_cdce925_pll { 73 struct clk_hw hw; 74 struct clk_cdce925_chip *chip; 75 u8 index; 76 u16 m; /* 1..511 */ 77 u16 n; /* 1..4095 */ 78 }; 79 #define to_clk_cdce925_pll(_hw) container_of(_hw, struct clk_cdce925_pll, hw) 80 81 struct clk_cdce925_chip { 82 struct regmap *regmap; 83 struct i2c_client *i2c_client; 84 const struct clk_cdce925_chip_info *chip_info; 85 struct clk_cdce925_pll pll[MAX_NUMBER_OF_PLLS]; 86 struct clk_cdce925_output clk[MAX_NUMBER_OF_OUTPUTS]; 87 }; 88 89 /* ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** */ 90 91 static unsigned long cdce925_pll_calculate_rate(unsigned long parent_rate, 92 u16 n, u16 m) 93 { 94 if ((!m || !n) || (m == n)) 95 return parent_rate; /* In bypass mode runs at same frequency */ 96 return mult_frac(parent_rate, (unsigned long)n, (unsigned long)m); 97 } 98 99 static unsigned long cdce925_pll_recalc_rate(struct clk_hw *hw, 100 unsigned long parent_rate) 101 { 102 /* Output frequency of PLL is Fout = (Fin/Pdiv)*(N/M) */ 103 struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw); 104 105 return cdce925_pll_calculate_rate(parent_rate, data->n, data->m); 106 } 107 108 static void cdce925_pll_find_rate(unsigned long rate, 109 unsigned long parent_rate, u16 *n, u16 *m) 110 { 111 unsigned long un; 112 unsigned long um; 113 unsigned long g; 114 115 if (rate <= parent_rate) { 116 /* Can always deliver parent_rate in bypass mode */ 117 rate = parent_rate; 118 *n = 0; 119 *m = 0; 120 } else { 121 /* In PLL mode, need to apply min/max range */ 122 if (rate < CDCE925_PLL_FREQUENCY_MIN) 123 rate = CDCE925_PLL_FREQUENCY_MIN; 124 else if (rate > CDCE925_PLL_FREQUENCY_MAX) 125 rate = CDCE925_PLL_FREQUENCY_MAX; 126 127 g = gcd(rate, parent_rate); 128 um = parent_rate / g; 129 un = rate / g; 130 /* When outside hw range, reduce to fit (rounding errors) */ 131 while ((un > 4095) || (um > 511)) { 132 un >>= 1; 133 um >>= 1; 134 } 135 if (un == 0) 136 un = 1; 137 if (um == 0) 138 um = 1; 139 140 *n = un; 141 *m = um; 142 } 143 } 144 145 static long cdce925_pll_round_rate(struct clk_hw *hw, unsigned long rate, 146 unsigned long *parent_rate) 147 { 148 u16 n, m; 149 150 cdce925_pll_find_rate(rate, *parent_rate, &n, &m); 151 return (long)cdce925_pll_calculate_rate(*parent_rate, n, m); 152 } 153 154 static int cdce925_pll_set_rate(struct clk_hw *hw, unsigned long rate, 155 unsigned long parent_rate) 156 { 157 struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw); 158 159 if (!rate || (rate == parent_rate)) { 160 data->m = 0; /* Bypass mode */ 161 data->n = 0; 162 return 0; 163 } 164 165 if ((rate < CDCE925_PLL_FREQUENCY_MIN) || 166 (rate > CDCE925_PLL_FREQUENCY_MAX)) { 167 pr_debug("%s: rate %lu outside PLL range.\n", __func__, rate); 168 return -EINVAL; 169 } 170 171 if (rate < parent_rate) { 172 pr_debug("%s: rate %lu less than parent rate %lu.\n", __func__, 173 rate, parent_rate); 174 return -EINVAL; 175 } 176 177 cdce925_pll_find_rate(rate, parent_rate, &data->n, &data->m); 178 return 0; 179 } 180 181 182 /* calculate p = max(0, 4 - int(log2 (n/m))) */ 183 static u8 cdce925_pll_calc_p(u16 n, u16 m) 184 { 185 u8 p; 186 u16 r = n / m; 187 188 if (r >= 16) 189 return 0; 190 p = 4; 191 while (r > 1) { 192 r >>= 1; 193 --p; 194 } 195 return p; 196 } 197 198 /* Returns VCO range bits for VCO1_0_RANGE */ 199 static u8 cdce925_pll_calc_range_bits(struct clk_hw *hw, u16 n, u16 m) 200 { 201 struct clk *parent = clk_get_parent(hw->clk); 202 unsigned long rate = clk_get_rate(parent); 203 204 rate = mult_frac(rate, (unsigned long)n, (unsigned long)m); 205 if (rate >= 175000000) 206 return 0x3; 207 if (rate >= 150000000) 208 return 0x02; 209 if (rate >= 125000000) 210 return 0x01; 211 return 0x00; 212 } 213 214 /* I2C clock, hence everything must happen in (un)prepare because this 215 * may sleep */ 216 static int cdce925_pll_prepare(struct clk_hw *hw) 217 { 218 struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw); 219 u16 n = data->n; 220 u16 m = data->m; 221 u16 r; 222 u8 q; 223 u8 p; 224 u16 nn; 225 u8 pll[4]; /* Bits are spread out over 4 byte registers */ 226 u8 reg_ofs = data->index * CDCE925_OFFSET_PLL; 227 unsigned i; 228 229 if ((!m || !n) || (m == n)) { 230 /* Set PLL mux to bypass mode, leave the rest as is */ 231 regmap_update_bits(data->chip->regmap, 232 reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80); 233 } else { 234 /* According to data sheet: */ 235 /* p = max(0, 4 - int(log2 (n/m))) */ 236 p = cdce925_pll_calc_p(n, m); 237 /* nn = n * 2^p */ 238 nn = n * BIT(p); 239 /* q = int(nn/m) */ 240 q = nn / m; 241 if ((q < 16) || (q > 63)) { 242 pr_debug("%s invalid q=%d\n", __func__, q); 243 return -EINVAL; 244 } 245 r = nn - (m*q); 246 if (r > 511) { 247 pr_debug("%s invalid r=%d\n", __func__, r); 248 return -EINVAL; 249 } 250 pr_debug("%s n=%d m=%d p=%d q=%d r=%d\n", __func__, 251 n, m, p, q, r); 252 /* encode into register bits */ 253 pll[0] = n >> 4; 254 pll[1] = ((n & 0x0F) << 4) | ((r >> 5) & 0x0F); 255 pll[2] = ((r & 0x1F) << 3) | ((q >> 3) & 0x07); 256 pll[3] = ((q & 0x07) << 5) | (p << 2) | 257 cdce925_pll_calc_range_bits(hw, n, m); 258 /* Write to registers */ 259 for (i = 0; i < ARRAY_SIZE(pll); ++i) 260 regmap_write(data->chip->regmap, 261 reg_ofs + CDCE925_PLL_MULDIV + i, pll[i]); 262 /* Enable PLL */ 263 regmap_update_bits(data->chip->regmap, 264 reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x00); 265 } 266 267 return 0; 268 } 269 270 static void cdce925_pll_unprepare(struct clk_hw *hw) 271 { 272 struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw); 273 u8 reg_ofs = data->index * CDCE925_OFFSET_PLL; 274 275 regmap_update_bits(data->chip->regmap, 276 reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80); 277 } 278 279 static const struct clk_ops cdce925_pll_ops = { 280 .prepare = cdce925_pll_prepare, 281 .unprepare = cdce925_pll_unprepare, 282 .recalc_rate = cdce925_pll_recalc_rate, 283 .round_rate = cdce925_pll_round_rate, 284 .set_rate = cdce925_pll_set_rate, 285 }; 286 287 288 static void cdce925_clk_set_pdiv(struct clk_cdce925_output *data, u16 pdiv) 289 { 290 switch (data->index) { 291 case 0: 292 regmap_update_bits(data->chip->regmap, 293 CDCE925_REG_Y1SPIPDIVH, 294 0x03, (pdiv >> 8) & 0x03); 295 regmap_write(data->chip->regmap, 0x03, pdiv & 0xFF); 296 break; 297 case 1: 298 regmap_update_bits(data->chip->regmap, 0x16, 0x7F, pdiv); 299 break; 300 case 2: 301 regmap_update_bits(data->chip->regmap, 0x17, 0x7F, pdiv); 302 break; 303 case 3: 304 regmap_update_bits(data->chip->regmap, 0x26, 0x7F, pdiv); 305 break; 306 case 4: 307 regmap_update_bits(data->chip->regmap, 0x27, 0x7F, pdiv); 308 break; 309 case 5: 310 regmap_update_bits(data->chip->regmap, 0x36, 0x7F, pdiv); 311 break; 312 case 6: 313 regmap_update_bits(data->chip->regmap, 0x37, 0x7F, pdiv); 314 break; 315 case 7: 316 regmap_update_bits(data->chip->regmap, 0x46, 0x7F, pdiv); 317 break; 318 case 8: 319 regmap_update_bits(data->chip->regmap, 0x47, 0x7F, pdiv); 320 break; 321 } 322 } 323 324 static void cdce925_clk_activate(struct clk_cdce925_output *data) 325 { 326 switch (data->index) { 327 case 0: 328 regmap_update_bits(data->chip->regmap, 329 CDCE925_REG_Y1SPIPDIVH, 0x0c, 0x0c); 330 break; 331 case 1: 332 case 2: 333 regmap_update_bits(data->chip->regmap, 0x14, 0x03, 0x03); 334 break; 335 case 3: 336 case 4: 337 regmap_update_bits(data->chip->regmap, 0x24, 0x03, 0x03); 338 break; 339 case 5: 340 case 6: 341 regmap_update_bits(data->chip->regmap, 0x34, 0x03, 0x03); 342 break; 343 case 7: 344 case 8: 345 regmap_update_bits(data->chip->regmap, 0x44, 0x03, 0x03); 346 break; 347 } 348 } 349 350 static int cdce925_clk_prepare(struct clk_hw *hw) 351 { 352 struct clk_cdce925_output *data = to_clk_cdce925_output(hw); 353 354 cdce925_clk_set_pdiv(data, data->pdiv); 355 cdce925_clk_activate(data); 356 return 0; 357 } 358 359 static void cdce925_clk_unprepare(struct clk_hw *hw) 360 { 361 struct clk_cdce925_output *data = to_clk_cdce925_output(hw); 362 363 /* Disable clock by setting divider to "0" */ 364 cdce925_clk_set_pdiv(data, 0); 365 } 366 367 static unsigned long cdce925_clk_recalc_rate(struct clk_hw *hw, 368 unsigned long parent_rate) 369 { 370 struct clk_cdce925_output *data = to_clk_cdce925_output(hw); 371 372 if (data->pdiv) 373 return parent_rate / data->pdiv; 374 return 0; 375 } 376 377 static u16 cdce925_calc_divider(unsigned long rate, 378 unsigned long parent_rate) 379 { 380 unsigned long divider; 381 382 if (!rate) 383 return 0; 384 if (rate >= parent_rate) 385 return 1; 386 387 divider = DIV_ROUND_CLOSEST(parent_rate, rate); 388 if (divider > 0x7F) 389 divider = 0x7F; 390 391 return (u16)divider; 392 } 393 394 static unsigned long cdce925_clk_best_parent_rate( 395 struct clk_hw *hw, unsigned long rate) 396 { 397 struct clk *pll = clk_get_parent(hw->clk); 398 struct clk *root = clk_get_parent(pll); 399 unsigned long root_rate = clk_get_rate(root); 400 unsigned long best_rate_error = rate; 401 u16 pdiv_min; 402 u16 pdiv_max; 403 u16 pdiv_best; 404 u16 pdiv_now; 405 406 if (root_rate % rate == 0) 407 return root_rate; /* Don't need the PLL, use bypass */ 408 409 pdiv_min = (u16)max(1ul, DIV_ROUND_UP(CDCE925_PLL_FREQUENCY_MIN, rate)); 410 pdiv_max = (u16)min(127ul, CDCE925_PLL_FREQUENCY_MAX / rate); 411 412 if (pdiv_min > pdiv_max) 413 return 0; /* No can do? */ 414 415 pdiv_best = pdiv_min; 416 for (pdiv_now = pdiv_min; pdiv_now < pdiv_max; ++pdiv_now) { 417 unsigned long target_rate = rate * pdiv_now; 418 long pll_rate = clk_round_rate(pll, target_rate); 419 unsigned long actual_rate; 420 unsigned long rate_error; 421 422 if (pll_rate <= 0) 423 continue; 424 actual_rate = pll_rate / pdiv_now; 425 rate_error = abs((long)actual_rate - (long)rate); 426 if (rate_error < best_rate_error) { 427 pdiv_best = pdiv_now; 428 best_rate_error = rate_error; 429 } 430 /* TODO: Consider PLL frequency based on smaller n/m values 431 * and pick the better one if the error is equal */ 432 } 433 434 return rate * pdiv_best; 435 } 436 437 static long cdce925_clk_round_rate(struct clk_hw *hw, unsigned long rate, 438 unsigned long *parent_rate) 439 { 440 unsigned long l_parent_rate = *parent_rate; 441 u16 divider = cdce925_calc_divider(rate, l_parent_rate); 442 443 if (l_parent_rate / divider != rate) { 444 l_parent_rate = cdce925_clk_best_parent_rate(hw, rate); 445 divider = cdce925_calc_divider(rate, l_parent_rate); 446 *parent_rate = l_parent_rate; 447 } 448 449 if (divider) 450 return (long)(l_parent_rate / divider); 451 return 0; 452 } 453 454 static int cdce925_clk_set_rate(struct clk_hw *hw, unsigned long rate, 455 unsigned long parent_rate) 456 { 457 struct clk_cdce925_output *data = to_clk_cdce925_output(hw); 458 459 data->pdiv = cdce925_calc_divider(rate, parent_rate); 460 461 return 0; 462 } 463 464 static const struct clk_ops cdce925_clk_ops = { 465 .prepare = cdce925_clk_prepare, 466 .unprepare = cdce925_clk_unprepare, 467 .recalc_rate = cdce925_clk_recalc_rate, 468 .round_rate = cdce925_clk_round_rate, 469 .set_rate = cdce925_clk_set_rate, 470 }; 471 472 473 static u16 cdce925_y1_calc_divider(unsigned long rate, 474 unsigned long parent_rate) 475 { 476 unsigned long divider; 477 478 if (!rate) 479 return 0; 480 if (rate >= parent_rate) 481 return 1; 482 483 divider = DIV_ROUND_CLOSEST(parent_rate, rate); 484 if (divider > 0x3FF) /* Y1 has 10-bit divider */ 485 divider = 0x3FF; 486 487 return (u16)divider; 488 } 489 490 static long cdce925_clk_y1_round_rate(struct clk_hw *hw, unsigned long rate, 491 unsigned long *parent_rate) 492 { 493 unsigned long l_parent_rate = *parent_rate; 494 u16 divider = cdce925_y1_calc_divider(rate, l_parent_rate); 495 496 if (divider) 497 return (long)(l_parent_rate / divider); 498 return 0; 499 } 500 501 static int cdce925_clk_y1_set_rate(struct clk_hw *hw, unsigned long rate, 502 unsigned long parent_rate) 503 { 504 struct clk_cdce925_output *data = to_clk_cdce925_output(hw); 505 506 data->pdiv = cdce925_y1_calc_divider(rate, parent_rate); 507 508 return 0; 509 } 510 511 static const struct clk_ops cdce925_clk_y1_ops = { 512 .prepare = cdce925_clk_prepare, 513 .unprepare = cdce925_clk_unprepare, 514 .recalc_rate = cdce925_clk_recalc_rate, 515 .round_rate = cdce925_clk_y1_round_rate, 516 .set_rate = cdce925_clk_y1_set_rate, 517 }; 518 519 #define CDCE925_I2C_COMMAND_BLOCK_TRANSFER 0x00 520 #define CDCE925_I2C_COMMAND_BYTE_TRANSFER 0x80 521 522 static int cdce925_regmap_i2c_write( 523 void *context, const void *data, size_t count) 524 { 525 struct device *dev = context; 526 struct i2c_client *i2c = to_i2c_client(dev); 527 int ret; 528 u8 reg_data[2]; 529 530 if (count != 2) 531 return -ENOTSUPP; 532 533 /* First byte is command code */ 534 reg_data[0] = CDCE925_I2C_COMMAND_BYTE_TRANSFER | ((u8 *)data)[0]; 535 reg_data[1] = ((u8 *)data)[1]; 536 537 dev_dbg(&i2c->dev, "%s(%zu) %#x %#x\n", __func__, count, 538 reg_data[0], reg_data[1]); 539 540 ret = i2c_master_send(i2c, reg_data, count); 541 if (likely(ret == count)) 542 return 0; 543 else if (ret < 0) 544 return ret; 545 else 546 return -EIO; 547 } 548 549 static int cdce925_regmap_i2c_read(void *context, 550 const void *reg, size_t reg_size, void *val, size_t val_size) 551 { 552 struct device *dev = context; 553 struct i2c_client *i2c = to_i2c_client(dev); 554 struct i2c_msg xfer[2]; 555 int ret; 556 u8 reg_data[2]; 557 558 if (reg_size != 1) 559 return -ENOTSUPP; 560 561 xfer[0].addr = i2c->addr; 562 xfer[0].flags = 0; 563 xfer[0].buf = reg_data; 564 if (val_size == 1) { 565 reg_data[0] = 566 CDCE925_I2C_COMMAND_BYTE_TRANSFER | ((u8 *)reg)[0]; 567 xfer[0].len = 1; 568 } else { 569 reg_data[0] = 570 CDCE925_I2C_COMMAND_BLOCK_TRANSFER | ((u8 *)reg)[0]; 571 reg_data[1] = val_size; 572 xfer[0].len = 2; 573 } 574 575 xfer[1].addr = i2c->addr; 576 xfer[1].flags = I2C_M_RD; 577 xfer[1].len = val_size; 578 xfer[1].buf = val; 579 580 ret = i2c_transfer(i2c->adapter, xfer, 2); 581 if (likely(ret == 2)) { 582 dev_dbg(&i2c->dev, "%s(%zu, %zu) %#x %#x\n", __func__, 583 reg_size, val_size, reg_data[0], *((u8 *)val)); 584 return 0; 585 } else if (ret < 0) 586 return ret; 587 else 588 return -EIO; 589 } 590 591 static struct clk_hw * 592 of_clk_cdce925_get(struct of_phandle_args *clkspec, void *_data) 593 { 594 struct clk_cdce925_chip *data = _data; 595 unsigned int idx = clkspec->args[0]; 596 597 if (idx >= ARRAY_SIZE(data->clk)) { 598 pr_err("%s: invalid index %u\n", __func__, idx); 599 return ERR_PTR(-EINVAL); 600 } 601 602 return &data->clk[idx].hw; 603 } 604 605 /* The CDCE925 uses a funky way to read/write registers. Bulk mode is 606 * just weird, so just use the single byte mode exclusively. */ 607 static struct regmap_bus regmap_cdce925_bus = { 608 .write = cdce925_regmap_i2c_write, 609 .read = cdce925_regmap_i2c_read, 610 }; 611 612 static int cdce925_probe(struct i2c_client *client, 613 const struct i2c_device_id *id) 614 { 615 struct clk_cdce925_chip *data; 616 struct device_node *node = client->dev.of_node; 617 const char *parent_name; 618 const char *pll_clk_name[MAX_NUMBER_OF_PLLS] = {NULL,}; 619 struct clk_init_data init; 620 u32 value; 621 int i; 622 int err; 623 struct device_node *np_output; 624 char child_name[6]; 625 struct regmap_config config = { 626 .name = "configuration0", 627 .reg_bits = 8, 628 .val_bits = 8, 629 .cache_type = REGCACHE_RBTREE, 630 }; 631 632 dev_dbg(&client->dev, "%s\n", __func__); 633 data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL); 634 if (!data) 635 return -ENOMEM; 636 637 data->i2c_client = client; 638 data->chip_info = &clk_cdce925_chip_info_tbl[id->driver_data]; 639 config.max_register = CDCE925_OFFSET_PLL + 640 data->chip_info->num_plls * 0x10 - 1; 641 data->regmap = devm_regmap_init(&client->dev, ®map_cdce925_bus, 642 &client->dev, &config); 643 if (IS_ERR(data->regmap)) { 644 dev_err(&client->dev, "failed to allocate register map\n"); 645 return PTR_ERR(data->regmap); 646 } 647 i2c_set_clientdata(client, data); 648 649 parent_name = of_clk_get_parent_name(node, 0); 650 if (!parent_name) { 651 dev_err(&client->dev, "missing parent clock\n"); 652 return -ENODEV; 653 } 654 dev_dbg(&client->dev, "parent is: %s\n", parent_name); 655 656 if (of_property_read_u32(node, "xtal-load-pf", &value) == 0) 657 regmap_write(data->regmap, 658 CDCE925_REG_XCSEL, (value << 3) & 0xF8); 659 /* PWDN bit */ 660 regmap_update_bits(data->regmap, CDCE925_REG_GLOBAL1, BIT(4), 0); 661 662 /* Set input source for Y1 to be the XTAL */ 663 regmap_update_bits(data->regmap, 0x02, BIT(7), 0); 664 665 init.ops = &cdce925_pll_ops; 666 init.flags = 0; 667 init.parent_names = &parent_name; 668 init.num_parents = 1; 669 670 /* Register PLL clocks */ 671 for (i = 0; i < data->chip_info->num_plls; ++i) { 672 pll_clk_name[i] = kasprintf(GFP_KERNEL, "%pOFn.pll%d", 673 client->dev.of_node, i); 674 init.name = pll_clk_name[i]; 675 data->pll[i].chip = data; 676 data->pll[i].hw.init = &init; 677 data->pll[i].index = i; 678 err = devm_clk_hw_register(&client->dev, &data->pll[i].hw); 679 if (err) { 680 dev_err(&client->dev, "Failed register PLL %d\n", i); 681 goto error; 682 } 683 sprintf(child_name, "PLL%d", i+1); 684 np_output = of_get_child_by_name(node, child_name); 685 if (!np_output) 686 continue; 687 if (!of_property_read_u32(np_output, 688 "clock-frequency", &value)) { 689 err = clk_set_rate(data->pll[i].hw.clk, value); 690 if (err) 691 dev_err(&client->dev, 692 "unable to set PLL frequency %ud\n", 693 value); 694 } 695 if (!of_property_read_u32(np_output, 696 "spread-spectrum", &value)) { 697 u8 flag = of_property_read_bool(np_output, 698 "spread-spectrum-center") ? 0x80 : 0x00; 699 regmap_update_bits(data->regmap, 700 0x16 + (i*CDCE925_OFFSET_PLL), 701 0x80, flag); 702 regmap_update_bits(data->regmap, 703 0x12 + (i*CDCE925_OFFSET_PLL), 704 0x07, value & 0x07); 705 } 706 of_node_put(np_output); 707 } 708 709 /* Register output clock Y1 */ 710 init.ops = &cdce925_clk_y1_ops; 711 init.flags = 0; 712 init.num_parents = 1; 713 init.parent_names = &parent_name; /* Mux Y1 to input */ 714 init.name = kasprintf(GFP_KERNEL, "%pOFn.Y1", client->dev.of_node); 715 data->clk[0].chip = data; 716 data->clk[0].hw.init = &init; 717 data->clk[0].index = 0; 718 data->clk[0].pdiv = 1; 719 err = devm_clk_hw_register(&client->dev, &data->clk[0].hw); 720 kfree(init.name); /* clock framework made a copy of the name */ 721 if (err) { 722 dev_err(&client->dev, "clock registration Y1 failed\n"); 723 goto error; 724 } 725 726 /* Register output clocks Y2 .. Y5*/ 727 init.ops = &cdce925_clk_ops; 728 init.flags = CLK_SET_RATE_PARENT; 729 init.num_parents = 1; 730 for (i = 1; i < data->chip_info->num_outputs; ++i) { 731 init.name = kasprintf(GFP_KERNEL, "%pOFn.Y%d", 732 client->dev.of_node, i+1); 733 data->clk[i].chip = data; 734 data->clk[i].hw.init = &init; 735 data->clk[i].index = i; 736 data->clk[i].pdiv = 1; 737 switch (i) { 738 case 1: 739 case 2: 740 /* Mux Y2/3 to PLL1 */ 741 init.parent_names = &pll_clk_name[0]; 742 break; 743 case 3: 744 case 4: 745 /* Mux Y4/5 to PLL2 */ 746 init.parent_names = &pll_clk_name[1]; 747 break; 748 case 5: 749 case 6: 750 /* Mux Y6/7 to PLL3 */ 751 init.parent_names = &pll_clk_name[2]; 752 break; 753 case 7: 754 case 8: 755 /* Mux Y8/9 to PLL4 */ 756 init.parent_names = &pll_clk_name[3]; 757 break; 758 } 759 err = devm_clk_hw_register(&client->dev, &data->clk[i].hw); 760 kfree(init.name); /* clock framework made a copy of the name */ 761 if (err) { 762 dev_err(&client->dev, "clock registration failed\n"); 763 goto error; 764 } 765 } 766 767 /* Register the output clocks */ 768 err = of_clk_add_hw_provider(client->dev.of_node, of_clk_cdce925_get, 769 data); 770 if (err) 771 dev_err(&client->dev, "unable to add OF clock provider\n"); 772 773 err = 0; 774 775 error: 776 for (i = 0; i < data->chip_info->num_plls; ++i) 777 /* clock framework made a copy of the name */ 778 kfree(pll_clk_name[i]); 779 780 return err; 781 } 782 783 static const struct i2c_device_id cdce925_id[] = { 784 { "cdce913", CDCE913 }, 785 { "cdce925", CDCE925 }, 786 { "cdce937", CDCE937 }, 787 { "cdce949", CDCE949 }, 788 { } 789 }; 790 MODULE_DEVICE_TABLE(i2c, cdce925_id); 791 792 static const struct of_device_id clk_cdce925_of_match[] = { 793 { .compatible = "ti,cdce913" }, 794 { .compatible = "ti,cdce925" }, 795 { .compatible = "ti,cdce937" }, 796 { .compatible = "ti,cdce949" }, 797 { }, 798 }; 799 MODULE_DEVICE_TABLE(of, clk_cdce925_of_match); 800 801 static struct i2c_driver cdce925_driver = { 802 .driver = { 803 .name = "cdce925", 804 .of_match_table = of_match_ptr(clk_cdce925_of_match), 805 }, 806 .probe = cdce925_probe, 807 .id_table = cdce925_id, 808 }; 809 module_i2c_driver(cdce925_driver); 810 811 MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>"); 812 MODULE_DESCRIPTION("TI CDCE913/925/937/949 driver"); 813 MODULE_LICENSE("GPL"); 814