1 /* 2 * Driver for TI Multi PLL CDCE913/925/937/949 clock synthesizer 3 * 4 * This driver always connects the Y1 to the input clock, Y2/Y3 to PLL1, 5 * Y4/Y5 to PLL2, and so on. PLL frequency is set on a first-come-first-serve 6 * basis. Clients can directly request any frequency that the chip can 7 * deliver using the standard clk framework. In addition, the device can 8 * be configured and activated via the devicetree. 9 * 10 * Copyright (C) 2014, Topic Embedded Products 11 * Licenced under GPL 12 */ 13 #include <linux/clk.h> 14 #include <linux/clk-provider.h> 15 #include <linux/delay.h> 16 #include <linux/module.h> 17 #include <linux/i2c.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/slab.h> 21 #include <linux/gcd.h> 22 23 /* Each chip has different number of PLLs and outputs, for example: 24 * The CECE925 has 2 PLLs which can be routed through dividers to 5 outputs. 25 * Model this as 2 PLL clocks which are parents to the outputs. 26 */ 27 28 enum { 29 CDCE913, 30 CDCE925, 31 CDCE937, 32 CDCE949, 33 }; 34 35 struct clk_cdce925_chip_info { 36 int num_plls; 37 int num_outputs; 38 }; 39 40 static const struct clk_cdce925_chip_info clk_cdce925_chip_info_tbl[] = { 41 [CDCE913] = { .num_plls = 1, .num_outputs = 3 }, 42 [CDCE925] = { .num_plls = 2, .num_outputs = 5 }, 43 [CDCE937] = { .num_plls = 3, .num_outputs = 7 }, 44 [CDCE949] = { .num_plls = 4, .num_outputs = 9 }, 45 }; 46 47 #define MAX_NUMBER_OF_PLLS 4 48 #define MAX_NUMBER_OF_OUTPUTS 9 49 50 #define CDCE925_REG_GLOBAL1 0x01 51 #define CDCE925_REG_Y1SPIPDIVH 0x02 52 #define CDCE925_REG_PDIVL 0x03 53 #define CDCE925_REG_XCSEL 0x05 54 /* PLL parameters start at 0x10, steps of 0x10 */ 55 #define CDCE925_OFFSET_PLL 0x10 56 /* Add CDCE925_OFFSET_PLL * (pll) to these registers before sending */ 57 #define CDCE925_PLL_MUX_OUTPUTS 0x14 58 #define CDCE925_PLL_MULDIV 0x18 59 60 #define CDCE925_PLL_FREQUENCY_MIN 80000000ul 61 #define CDCE925_PLL_FREQUENCY_MAX 230000000ul 62 struct clk_cdce925_chip; 63 64 struct clk_cdce925_output { 65 struct clk_hw hw; 66 struct clk_cdce925_chip *chip; 67 u8 index; 68 u16 pdiv; /* 1..127 for Y2-Y9; 1..1023 for Y1 */ 69 }; 70 #define to_clk_cdce925_output(_hw) \ 71 container_of(_hw, struct clk_cdce925_output, hw) 72 73 struct clk_cdce925_pll { 74 struct clk_hw hw; 75 struct clk_cdce925_chip *chip; 76 u8 index; 77 u16 m; /* 1..511 */ 78 u16 n; /* 1..4095 */ 79 }; 80 #define to_clk_cdce925_pll(_hw) container_of(_hw, struct clk_cdce925_pll, hw) 81 82 struct clk_cdce925_chip { 83 struct regmap *regmap; 84 struct i2c_client *i2c_client; 85 const struct clk_cdce925_chip_info *chip_info; 86 struct clk_cdce925_pll pll[MAX_NUMBER_OF_PLLS]; 87 struct clk_cdce925_output clk[MAX_NUMBER_OF_OUTPUTS]; 88 }; 89 90 /* ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** */ 91 92 static unsigned long cdce925_pll_calculate_rate(unsigned long parent_rate, 93 u16 n, u16 m) 94 { 95 if ((!m || !n) || (m == n)) 96 return parent_rate; /* In bypass mode runs at same frequency */ 97 return mult_frac(parent_rate, (unsigned long)n, (unsigned long)m); 98 } 99 100 static unsigned long cdce925_pll_recalc_rate(struct clk_hw *hw, 101 unsigned long parent_rate) 102 { 103 /* Output frequency of PLL is Fout = (Fin/Pdiv)*(N/M) */ 104 struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw); 105 106 return cdce925_pll_calculate_rate(parent_rate, data->n, data->m); 107 } 108 109 static void cdce925_pll_find_rate(unsigned long rate, 110 unsigned long parent_rate, u16 *n, u16 *m) 111 { 112 unsigned long un; 113 unsigned long um; 114 unsigned long g; 115 116 if (rate <= parent_rate) { 117 /* Can always deliver parent_rate in bypass mode */ 118 rate = parent_rate; 119 *n = 0; 120 *m = 0; 121 } else { 122 /* In PLL mode, need to apply min/max range */ 123 if (rate < CDCE925_PLL_FREQUENCY_MIN) 124 rate = CDCE925_PLL_FREQUENCY_MIN; 125 else if (rate > CDCE925_PLL_FREQUENCY_MAX) 126 rate = CDCE925_PLL_FREQUENCY_MAX; 127 128 g = gcd(rate, parent_rate); 129 um = parent_rate / g; 130 un = rate / g; 131 /* When outside hw range, reduce to fit (rounding errors) */ 132 while ((un > 4095) || (um > 511)) { 133 un >>= 1; 134 um >>= 1; 135 } 136 if (un == 0) 137 un = 1; 138 if (um == 0) 139 um = 1; 140 141 *n = un; 142 *m = um; 143 } 144 } 145 146 static long cdce925_pll_round_rate(struct clk_hw *hw, unsigned long rate, 147 unsigned long *parent_rate) 148 { 149 u16 n, m; 150 151 cdce925_pll_find_rate(rate, *parent_rate, &n, &m); 152 return (long)cdce925_pll_calculate_rate(*parent_rate, n, m); 153 } 154 155 static int cdce925_pll_set_rate(struct clk_hw *hw, unsigned long rate, 156 unsigned long parent_rate) 157 { 158 struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw); 159 160 if (!rate || (rate == parent_rate)) { 161 data->m = 0; /* Bypass mode */ 162 data->n = 0; 163 return 0; 164 } 165 166 if ((rate < CDCE925_PLL_FREQUENCY_MIN) || 167 (rate > CDCE925_PLL_FREQUENCY_MAX)) { 168 pr_debug("%s: rate %lu outside PLL range.\n", __func__, rate); 169 return -EINVAL; 170 } 171 172 if (rate < parent_rate) { 173 pr_debug("%s: rate %lu less than parent rate %lu.\n", __func__, 174 rate, parent_rate); 175 return -EINVAL; 176 } 177 178 cdce925_pll_find_rate(rate, parent_rate, &data->n, &data->m); 179 return 0; 180 } 181 182 183 /* calculate p = max(0, 4 - int(log2 (n/m))) */ 184 static u8 cdce925_pll_calc_p(u16 n, u16 m) 185 { 186 u8 p; 187 u16 r = n / m; 188 189 if (r >= 16) 190 return 0; 191 p = 4; 192 while (r > 1) { 193 r >>= 1; 194 --p; 195 } 196 return p; 197 } 198 199 /* Returns VCO range bits for VCO1_0_RANGE */ 200 static u8 cdce925_pll_calc_range_bits(struct clk_hw *hw, u16 n, u16 m) 201 { 202 struct clk *parent = clk_get_parent(hw->clk); 203 unsigned long rate = clk_get_rate(parent); 204 205 rate = mult_frac(rate, (unsigned long)n, (unsigned long)m); 206 if (rate >= 175000000) 207 return 0x3; 208 if (rate >= 150000000) 209 return 0x02; 210 if (rate >= 125000000) 211 return 0x01; 212 return 0x00; 213 } 214 215 /* I2C clock, hence everything must happen in (un)prepare because this 216 * may sleep */ 217 static int cdce925_pll_prepare(struct clk_hw *hw) 218 { 219 struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw); 220 u16 n = data->n; 221 u16 m = data->m; 222 u16 r; 223 u8 q; 224 u8 p; 225 u16 nn; 226 u8 pll[4]; /* Bits are spread out over 4 byte registers */ 227 u8 reg_ofs = data->index * CDCE925_OFFSET_PLL; 228 unsigned i; 229 230 if ((!m || !n) || (m == n)) { 231 /* Set PLL mux to bypass mode, leave the rest as is */ 232 regmap_update_bits(data->chip->regmap, 233 reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80); 234 } else { 235 /* According to data sheet: */ 236 /* p = max(0, 4 - int(log2 (n/m))) */ 237 p = cdce925_pll_calc_p(n, m); 238 /* nn = n * 2^p */ 239 nn = n * BIT(p); 240 /* q = int(nn/m) */ 241 q = nn / m; 242 if ((q < 16) || (q > 63)) { 243 pr_debug("%s invalid q=%d\n", __func__, q); 244 return -EINVAL; 245 } 246 r = nn - (m*q); 247 if (r > 511) { 248 pr_debug("%s invalid r=%d\n", __func__, r); 249 return -EINVAL; 250 } 251 pr_debug("%s n=%d m=%d p=%d q=%d r=%d\n", __func__, 252 n, m, p, q, r); 253 /* encode into register bits */ 254 pll[0] = n >> 4; 255 pll[1] = ((n & 0x0F) << 4) | ((r >> 5) & 0x0F); 256 pll[2] = ((r & 0x1F) << 3) | ((q >> 3) & 0x07); 257 pll[3] = ((q & 0x07) << 5) | (p << 2) | 258 cdce925_pll_calc_range_bits(hw, n, m); 259 /* Write to registers */ 260 for (i = 0; i < ARRAY_SIZE(pll); ++i) 261 regmap_write(data->chip->regmap, 262 reg_ofs + CDCE925_PLL_MULDIV + i, pll[i]); 263 /* Enable PLL */ 264 regmap_update_bits(data->chip->regmap, 265 reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x00); 266 } 267 268 return 0; 269 } 270 271 static void cdce925_pll_unprepare(struct clk_hw *hw) 272 { 273 struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw); 274 u8 reg_ofs = data->index * CDCE925_OFFSET_PLL; 275 276 regmap_update_bits(data->chip->regmap, 277 reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80); 278 } 279 280 static const struct clk_ops cdce925_pll_ops = { 281 .prepare = cdce925_pll_prepare, 282 .unprepare = cdce925_pll_unprepare, 283 .recalc_rate = cdce925_pll_recalc_rate, 284 .round_rate = cdce925_pll_round_rate, 285 .set_rate = cdce925_pll_set_rate, 286 }; 287 288 289 static void cdce925_clk_set_pdiv(struct clk_cdce925_output *data, u16 pdiv) 290 { 291 switch (data->index) { 292 case 0: 293 regmap_update_bits(data->chip->regmap, 294 CDCE925_REG_Y1SPIPDIVH, 295 0x03, (pdiv >> 8) & 0x03); 296 regmap_write(data->chip->regmap, 0x03, pdiv & 0xFF); 297 break; 298 case 1: 299 regmap_update_bits(data->chip->regmap, 0x16, 0x7F, pdiv); 300 break; 301 case 2: 302 regmap_update_bits(data->chip->regmap, 0x17, 0x7F, pdiv); 303 break; 304 case 3: 305 regmap_update_bits(data->chip->regmap, 0x26, 0x7F, pdiv); 306 break; 307 case 4: 308 regmap_update_bits(data->chip->regmap, 0x27, 0x7F, pdiv); 309 break; 310 case 5: 311 regmap_update_bits(data->chip->regmap, 0x36, 0x7F, pdiv); 312 break; 313 case 6: 314 regmap_update_bits(data->chip->regmap, 0x37, 0x7F, pdiv); 315 break; 316 case 7: 317 regmap_update_bits(data->chip->regmap, 0x46, 0x7F, pdiv); 318 break; 319 case 8: 320 regmap_update_bits(data->chip->regmap, 0x47, 0x7F, pdiv); 321 break; 322 } 323 } 324 325 static void cdce925_clk_activate(struct clk_cdce925_output *data) 326 { 327 switch (data->index) { 328 case 0: 329 regmap_update_bits(data->chip->regmap, 330 CDCE925_REG_Y1SPIPDIVH, 0x0c, 0x0c); 331 break; 332 case 1: 333 case 2: 334 regmap_update_bits(data->chip->regmap, 0x14, 0x03, 0x03); 335 break; 336 case 3: 337 case 4: 338 regmap_update_bits(data->chip->regmap, 0x24, 0x03, 0x03); 339 break; 340 case 5: 341 case 6: 342 regmap_update_bits(data->chip->regmap, 0x34, 0x03, 0x03); 343 break; 344 case 7: 345 case 8: 346 regmap_update_bits(data->chip->regmap, 0x44, 0x03, 0x03); 347 break; 348 } 349 } 350 351 static int cdce925_clk_prepare(struct clk_hw *hw) 352 { 353 struct clk_cdce925_output *data = to_clk_cdce925_output(hw); 354 355 cdce925_clk_set_pdiv(data, data->pdiv); 356 cdce925_clk_activate(data); 357 return 0; 358 } 359 360 static void cdce925_clk_unprepare(struct clk_hw *hw) 361 { 362 struct clk_cdce925_output *data = to_clk_cdce925_output(hw); 363 364 /* Disable clock by setting divider to "0" */ 365 cdce925_clk_set_pdiv(data, 0); 366 } 367 368 static unsigned long cdce925_clk_recalc_rate(struct clk_hw *hw, 369 unsigned long parent_rate) 370 { 371 struct clk_cdce925_output *data = to_clk_cdce925_output(hw); 372 373 if (data->pdiv) 374 return parent_rate / data->pdiv; 375 return 0; 376 } 377 378 static u16 cdce925_calc_divider(unsigned long rate, 379 unsigned long parent_rate) 380 { 381 unsigned long divider; 382 383 if (!rate) 384 return 0; 385 if (rate >= parent_rate) 386 return 1; 387 388 divider = DIV_ROUND_CLOSEST(parent_rate, rate); 389 if (divider > 0x7F) 390 divider = 0x7F; 391 392 return (u16)divider; 393 } 394 395 static unsigned long cdce925_clk_best_parent_rate( 396 struct clk_hw *hw, unsigned long rate) 397 { 398 struct clk *pll = clk_get_parent(hw->clk); 399 struct clk *root = clk_get_parent(pll); 400 unsigned long root_rate = clk_get_rate(root); 401 unsigned long best_rate_error = rate; 402 u16 pdiv_min; 403 u16 pdiv_max; 404 u16 pdiv_best; 405 u16 pdiv_now; 406 407 if (root_rate % rate == 0) 408 return root_rate; /* Don't need the PLL, use bypass */ 409 410 pdiv_min = (u16)max(1ul, DIV_ROUND_UP(CDCE925_PLL_FREQUENCY_MIN, rate)); 411 pdiv_max = (u16)min(127ul, CDCE925_PLL_FREQUENCY_MAX / rate); 412 413 if (pdiv_min > pdiv_max) 414 return 0; /* No can do? */ 415 416 pdiv_best = pdiv_min; 417 for (pdiv_now = pdiv_min; pdiv_now < pdiv_max; ++pdiv_now) { 418 unsigned long target_rate = rate * pdiv_now; 419 long pll_rate = clk_round_rate(pll, target_rate); 420 unsigned long actual_rate; 421 unsigned long rate_error; 422 423 if (pll_rate <= 0) 424 continue; 425 actual_rate = pll_rate / pdiv_now; 426 rate_error = abs((long)actual_rate - (long)rate); 427 if (rate_error < best_rate_error) { 428 pdiv_best = pdiv_now; 429 best_rate_error = rate_error; 430 } 431 /* TODO: Consider PLL frequency based on smaller n/m values 432 * and pick the better one if the error is equal */ 433 } 434 435 return rate * pdiv_best; 436 } 437 438 static long cdce925_clk_round_rate(struct clk_hw *hw, unsigned long rate, 439 unsigned long *parent_rate) 440 { 441 unsigned long l_parent_rate = *parent_rate; 442 u16 divider = cdce925_calc_divider(rate, l_parent_rate); 443 444 if (l_parent_rate / divider != rate) { 445 l_parent_rate = cdce925_clk_best_parent_rate(hw, rate); 446 divider = cdce925_calc_divider(rate, l_parent_rate); 447 *parent_rate = l_parent_rate; 448 } 449 450 if (divider) 451 return (long)(l_parent_rate / divider); 452 return 0; 453 } 454 455 static int cdce925_clk_set_rate(struct clk_hw *hw, unsigned long rate, 456 unsigned long parent_rate) 457 { 458 struct clk_cdce925_output *data = to_clk_cdce925_output(hw); 459 460 data->pdiv = cdce925_calc_divider(rate, parent_rate); 461 462 return 0; 463 } 464 465 static const struct clk_ops cdce925_clk_ops = { 466 .prepare = cdce925_clk_prepare, 467 .unprepare = cdce925_clk_unprepare, 468 .recalc_rate = cdce925_clk_recalc_rate, 469 .round_rate = cdce925_clk_round_rate, 470 .set_rate = cdce925_clk_set_rate, 471 }; 472 473 474 static u16 cdce925_y1_calc_divider(unsigned long rate, 475 unsigned long parent_rate) 476 { 477 unsigned long divider; 478 479 if (!rate) 480 return 0; 481 if (rate >= parent_rate) 482 return 1; 483 484 divider = DIV_ROUND_CLOSEST(parent_rate, rate); 485 if (divider > 0x3FF) /* Y1 has 10-bit divider */ 486 divider = 0x3FF; 487 488 return (u16)divider; 489 } 490 491 static long cdce925_clk_y1_round_rate(struct clk_hw *hw, unsigned long rate, 492 unsigned long *parent_rate) 493 { 494 unsigned long l_parent_rate = *parent_rate; 495 u16 divider = cdce925_y1_calc_divider(rate, l_parent_rate); 496 497 if (divider) 498 return (long)(l_parent_rate / divider); 499 return 0; 500 } 501 502 static int cdce925_clk_y1_set_rate(struct clk_hw *hw, unsigned long rate, 503 unsigned long parent_rate) 504 { 505 struct clk_cdce925_output *data = to_clk_cdce925_output(hw); 506 507 data->pdiv = cdce925_y1_calc_divider(rate, parent_rate); 508 509 return 0; 510 } 511 512 static const struct clk_ops cdce925_clk_y1_ops = { 513 .prepare = cdce925_clk_prepare, 514 .unprepare = cdce925_clk_unprepare, 515 .recalc_rate = cdce925_clk_recalc_rate, 516 .round_rate = cdce925_clk_y1_round_rate, 517 .set_rate = cdce925_clk_y1_set_rate, 518 }; 519 520 #define CDCE925_I2C_COMMAND_BLOCK_TRANSFER 0x00 521 #define CDCE925_I2C_COMMAND_BYTE_TRANSFER 0x80 522 523 static int cdce925_regmap_i2c_write( 524 void *context, const void *data, size_t count) 525 { 526 struct device *dev = context; 527 struct i2c_client *i2c = to_i2c_client(dev); 528 int ret; 529 u8 reg_data[2]; 530 531 if (count != 2) 532 return -ENOTSUPP; 533 534 /* First byte is command code */ 535 reg_data[0] = CDCE925_I2C_COMMAND_BYTE_TRANSFER | ((u8 *)data)[0]; 536 reg_data[1] = ((u8 *)data)[1]; 537 538 dev_dbg(&i2c->dev, "%s(%zu) %#x %#x\n", __func__, count, 539 reg_data[0], reg_data[1]); 540 541 ret = i2c_master_send(i2c, reg_data, count); 542 if (likely(ret == count)) 543 return 0; 544 else if (ret < 0) 545 return ret; 546 else 547 return -EIO; 548 } 549 550 static int cdce925_regmap_i2c_read(void *context, 551 const void *reg, size_t reg_size, void *val, size_t val_size) 552 { 553 struct device *dev = context; 554 struct i2c_client *i2c = to_i2c_client(dev); 555 struct i2c_msg xfer[2]; 556 int ret; 557 u8 reg_data[2]; 558 559 if (reg_size != 1) 560 return -ENOTSUPP; 561 562 xfer[0].addr = i2c->addr; 563 xfer[0].flags = 0; 564 xfer[0].buf = reg_data; 565 if (val_size == 1) { 566 reg_data[0] = 567 CDCE925_I2C_COMMAND_BYTE_TRANSFER | ((u8 *)reg)[0]; 568 xfer[0].len = 1; 569 } else { 570 reg_data[0] = 571 CDCE925_I2C_COMMAND_BLOCK_TRANSFER | ((u8 *)reg)[0]; 572 reg_data[1] = val_size; 573 xfer[0].len = 2; 574 } 575 576 xfer[1].addr = i2c->addr; 577 xfer[1].flags = I2C_M_RD; 578 xfer[1].len = val_size; 579 xfer[1].buf = val; 580 581 ret = i2c_transfer(i2c->adapter, xfer, 2); 582 if (likely(ret == 2)) { 583 dev_dbg(&i2c->dev, "%s(%zu, %zu) %#x %#x\n", __func__, 584 reg_size, val_size, reg_data[0], *((u8 *)val)); 585 return 0; 586 } else if (ret < 0) 587 return ret; 588 else 589 return -EIO; 590 } 591 592 static struct clk_hw * 593 of_clk_cdce925_get(struct of_phandle_args *clkspec, void *_data) 594 { 595 struct clk_cdce925_chip *data = _data; 596 unsigned int idx = clkspec->args[0]; 597 598 if (idx >= ARRAY_SIZE(data->clk)) { 599 pr_err("%s: invalid index %u\n", __func__, idx); 600 return ERR_PTR(-EINVAL); 601 } 602 603 return &data->clk[idx].hw; 604 } 605 606 static void cdce925_regulator_disable(void *regulator) 607 { 608 regulator_disable(regulator); 609 } 610 611 static int cdce925_regulator_enable(struct device *dev, const char *name) 612 { 613 struct regulator *regulator; 614 int err; 615 616 regulator = devm_regulator_get(dev, name); 617 if (IS_ERR(regulator)) 618 return PTR_ERR(regulator); 619 620 err = regulator_enable(regulator); 621 if (err) { 622 dev_err(dev, "Failed to enable %s: %d\n", name, err); 623 return err; 624 } 625 626 return devm_add_action_or_reset(dev, cdce925_regulator_disable, 627 regulator); 628 } 629 630 /* The CDCE925 uses a funky way to read/write registers. Bulk mode is 631 * just weird, so just use the single byte mode exclusively. */ 632 static struct regmap_bus regmap_cdce925_bus = { 633 .write = cdce925_regmap_i2c_write, 634 .read = cdce925_regmap_i2c_read, 635 }; 636 637 static const struct i2c_device_id cdce925_id[] = { 638 { "cdce913", CDCE913 }, 639 { "cdce925", CDCE925 }, 640 { "cdce937", CDCE937 }, 641 { "cdce949", CDCE949 }, 642 { } 643 }; 644 MODULE_DEVICE_TABLE(i2c, cdce925_id); 645 646 static int cdce925_probe(struct i2c_client *client) 647 { 648 struct clk_cdce925_chip *data; 649 struct device_node *node = client->dev.of_node; 650 const struct i2c_device_id *id = i2c_match_id(cdce925_id, client); 651 const char *parent_name; 652 const char *pll_clk_name[MAX_NUMBER_OF_PLLS] = {NULL,}; 653 struct clk_init_data init; 654 u32 value; 655 int i; 656 int err; 657 struct device_node *np_output; 658 char child_name[6]; 659 struct regmap_config config = { 660 .name = "configuration0", 661 .reg_bits = 8, 662 .val_bits = 8, 663 .cache_type = REGCACHE_RBTREE, 664 }; 665 666 dev_dbg(&client->dev, "%s\n", __func__); 667 668 err = cdce925_regulator_enable(&client->dev, "vdd"); 669 if (err) 670 return err; 671 672 err = cdce925_regulator_enable(&client->dev, "vddout"); 673 if (err) 674 return err; 675 676 data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL); 677 if (!data) 678 return -ENOMEM; 679 680 data->i2c_client = client; 681 data->chip_info = &clk_cdce925_chip_info_tbl[id->driver_data]; 682 config.max_register = CDCE925_OFFSET_PLL + 683 data->chip_info->num_plls * 0x10 - 1; 684 data->regmap = devm_regmap_init(&client->dev, ®map_cdce925_bus, 685 &client->dev, &config); 686 if (IS_ERR(data->regmap)) { 687 dev_err(&client->dev, "failed to allocate register map\n"); 688 return PTR_ERR(data->regmap); 689 } 690 i2c_set_clientdata(client, data); 691 692 parent_name = of_clk_get_parent_name(node, 0); 693 if (!parent_name) { 694 dev_err(&client->dev, "missing parent clock\n"); 695 return -ENODEV; 696 } 697 dev_dbg(&client->dev, "parent is: %s\n", parent_name); 698 699 if (of_property_read_u32(node, "xtal-load-pf", &value) == 0) 700 regmap_write(data->regmap, 701 CDCE925_REG_XCSEL, (value << 3) & 0xF8); 702 /* PWDN bit */ 703 regmap_update_bits(data->regmap, CDCE925_REG_GLOBAL1, BIT(4), 0); 704 705 /* Set input source for Y1 to be the XTAL */ 706 regmap_update_bits(data->regmap, 0x02, BIT(7), 0); 707 708 init.ops = &cdce925_pll_ops; 709 init.flags = 0; 710 init.parent_names = &parent_name; 711 init.num_parents = 1; 712 713 /* Register PLL clocks */ 714 for (i = 0; i < data->chip_info->num_plls; ++i) { 715 pll_clk_name[i] = kasprintf(GFP_KERNEL, "%pOFn.pll%d", 716 client->dev.of_node, i); 717 init.name = pll_clk_name[i]; 718 data->pll[i].chip = data; 719 data->pll[i].hw.init = &init; 720 data->pll[i].index = i; 721 err = devm_clk_hw_register(&client->dev, &data->pll[i].hw); 722 if (err) { 723 dev_err(&client->dev, "Failed register PLL %d\n", i); 724 goto error; 725 } 726 sprintf(child_name, "PLL%d", i+1); 727 np_output = of_get_child_by_name(node, child_name); 728 if (!np_output) 729 continue; 730 if (!of_property_read_u32(np_output, 731 "clock-frequency", &value)) { 732 err = clk_set_rate(data->pll[i].hw.clk, value); 733 if (err) 734 dev_err(&client->dev, 735 "unable to set PLL frequency %ud\n", 736 value); 737 } 738 if (!of_property_read_u32(np_output, 739 "spread-spectrum", &value)) { 740 u8 flag = of_property_read_bool(np_output, 741 "spread-spectrum-center") ? 0x80 : 0x00; 742 regmap_update_bits(data->regmap, 743 0x16 + (i*CDCE925_OFFSET_PLL), 744 0x80, flag); 745 regmap_update_bits(data->regmap, 746 0x12 + (i*CDCE925_OFFSET_PLL), 747 0x07, value & 0x07); 748 } 749 of_node_put(np_output); 750 } 751 752 /* Register output clock Y1 */ 753 init.ops = &cdce925_clk_y1_ops; 754 init.flags = 0; 755 init.num_parents = 1; 756 init.parent_names = &parent_name; /* Mux Y1 to input */ 757 init.name = kasprintf(GFP_KERNEL, "%pOFn.Y1", client->dev.of_node); 758 data->clk[0].chip = data; 759 data->clk[0].hw.init = &init; 760 data->clk[0].index = 0; 761 data->clk[0].pdiv = 1; 762 err = devm_clk_hw_register(&client->dev, &data->clk[0].hw); 763 kfree(init.name); /* clock framework made a copy of the name */ 764 if (err) { 765 dev_err(&client->dev, "clock registration Y1 failed\n"); 766 goto error; 767 } 768 769 /* Register output clocks Y2 .. Y5*/ 770 init.ops = &cdce925_clk_ops; 771 init.flags = CLK_SET_RATE_PARENT; 772 init.num_parents = 1; 773 for (i = 1; i < data->chip_info->num_outputs; ++i) { 774 init.name = kasprintf(GFP_KERNEL, "%pOFn.Y%d", 775 client->dev.of_node, i+1); 776 data->clk[i].chip = data; 777 data->clk[i].hw.init = &init; 778 data->clk[i].index = i; 779 data->clk[i].pdiv = 1; 780 switch (i) { 781 case 1: 782 case 2: 783 /* Mux Y2/3 to PLL1 */ 784 init.parent_names = &pll_clk_name[0]; 785 break; 786 case 3: 787 case 4: 788 /* Mux Y4/5 to PLL2 */ 789 init.parent_names = &pll_clk_name[1]; 790 break; 791 case 5: 792 case 6: 793 /* Mux Y6/7 to PLL3 */ 794 init.parent_names = &pll_clk_name[2]; 795 break; 796 case 7: 797 case 8: 798 /* Mux Y8/9 to PLL4 */ 799 init.parent_names = &pll_clk_name[3]; 800 break; 801 } 802 err = devm_clk_hw_register(&client->dev, &data->clk[i].hw); 803 kfree(init.name); /* clock framework made a copy of the name */ 804 if (err) { 805 dev_err(&client->dev, "clock registration failed\n"); 806 goto error; 807 } 808 } 809 810 /* Register the output clocks */ 811 err = of_clk_add_hw_provider(client->dev.of_node, of_clk_cdce925_get, 812 data); 813 if (err) 814 dev_err(&client->dev, "unable to add OF clock provider\n"); 815 816 err = 0; 817 818 error: 819 for (i = 0; i < data->chip_info->num_plls; ++i) 820 /* clock framework made a copy of the name */ 821 kfree(pll_clk_name[i]); 822 823 return err; 824 } 825 826 static const struct of_device_id clk_cdce925_of_match[] = { 827 { .compatible = "ti,cdce913" }, 828 { .compatible = "ti,cdce925" }, 829 { .compatible = "ti,cdce937" }, 830 { .compatible = "ti,cdce949" }, 831 { }, 832 }; 833 MODULE_DEVICE_TABLE(of, clk_cdce925_of_match); 834 835 static struct i2c_driver cdce925_driver = { 836 .driver = { 837 .name = "cdce925", 838 .of_match_table = of_match_ptr(clk_cdce925_of_match), 839 }, 840 .probe_new = cdce925_probe, 841 .id_table = cdce925_id, 842 }; 843 module_i2c_driver(cdce925_driver); 844 845 MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>"); 846 MODULE_DESCRIPTION("TI CDCE913/925/937/949 driver"); 847 MODULE_LICENSE("GPL"); 848