1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Bitmain BM1880 SoC clock driver 4 * 5 * Copyright (c) 2019 Linaro Ltd. 6 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 7 */ 8 9 #include <linux/clk-provider.h> 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/of_address.h> 13 #include <linux/of_device.h> 14 #include <linux/platform_device.h> 15 #include <linux/slab.h> 16 17 #include <dt-bindings/clock/bm1880-clock.h> 18 19 #define BM1880_CLK_MPLL_CTL 0x00 20 #define BM1880_CLK_SPLL_CTL 0x04 21 #define BM1880_CLK_FPLL_CTL 0x08 22 #define BM1880_CLK_DDRPLL_CTL 0x0c 23 24 #define BM1880_CLK_ENABLE0 0x00 25 #define BM1880_CLK_ENABLE1 0x04 26 #define BM1880_CLK_SELECT 0x20 27 #define BM1880_CLK_DIV0 0x40 28 #define BM1880_CLK_DIV1 0x44 29 #define BM1880_CLK_DIV2 0x48 30 #define BM1880_CLK_DIV3 0x4c 31 #define BM1880_CLK_DIV4 0x50 32 #define BM1880_CLK_DIV5 0x54 33 #define BM1880_CLK_DIV6 0x58 34 #define BM1880_CLK_DIV7 0x5c 35 #define BM1880_CLK_DIV8 0x60 36 #define BM1880_CLK_DIV9 0x64 37 #define BM1880_CLK_DIV10 0x68 38 #define BM1880_CLK_DIV11 0x6c 39 #define BM1880_CLK_DIV12 0x70 40 #define BM1880_CLK_DIV13 0x74 41 #define BM1880_CLK_DIV14 0x78 42 #define BM1880_CLK_DIV15 0x7c 43 #define BM1880_CLK_DIV16 0x80 44 #define BM1880_CLK_DIV17 0x84 45 #define BM1880_CLK_DIV18 0x88 46 #define BM1880_CLK_DIV19 0x8c 47 #define BM1880_CLK_DIV20 0x90 48 #define BM1880_CLK_DIV21 0x94 49 #define BM1880_CLK_DIV22 0x98 50 #define BM1880_CLK_DIV23 0x9c 51 #define BM1880_CLK_DIV24 0xa0 52 #define BM1880_CLK_DIV25 0xa4 53 #define BM1880_CLK_DIV26 0xa8 54 #define BM1880_CLK_DIV27 0xac 55 #define BM1880_CLK_DIV28 0xb0 56 57 #define to_bm1880_pll_clk(_hw) container_of(_hw, struct bm1880_pll_hw_clock, hw) 58 #define to_bm1880_div_clk(_hw) container_of(_hw, struct bm1880_div_hw_clock, hw) 59 60 static DEFINE_SPINLOCK(bm1880_clk_lock); 61 62 struct bm1880_clock_data { 63 void __iomem *pll_base; 64 void __iomem *sys_base; 65 struct clk_hw_onecell_data hw_data; 66 }; 67 68 struct bm1880_gate_clock { 69 unsigned int id; 70 const char *name; 71 const char *parent; 72 u32 gate_reg; 73 s8 gate_shift; 74 unsigned long flags; 75 }; 76 77 struct bm1880_mux_clock { 78 unsigned int id; 79 const char *name; 80 const char * const *parents; 81 s8 num_parents; 82 u32 reg; 83 s8 shift; 84 unsigned long flags; 85 }; 86 87 struct bm1880_div_clock { 88 unsigned int id; 89 const char *name; 90 u32 reg; 91 u8 shift; 92 u8 width; 93 u32 initval; 94 const struct clk_div_table *table; 95 unsigned long flags; 96 }; 97 98 struct bm1880_div_hw_clock { 99 struct bm1880_div_clock div; 100 void __iomem *base; 101 spinlock_t *lock; 102 struct clk_hw hw; 103 struct clk_init_data init; 104 }; 105 106 struct bm1880_composite_clock { 107 unsigned int id; 108 const char *name; 109 const char *parent; 110 const char * const *parents; 111 unsigned int num_parents; 112 unsigned long flags; 113 114 u32 gate_reg; 115 u32 mux_reg; 116 u32 div_reg; 117 118 s8 gate_shift; 119 s8 mux_shift; 120 s8 div_shift; 121 s8 div_width; 122 s16 div_initval; 123 const struct clk_div_table *table; 124 }; 125 126 struct bm1880_pll_clock { 127 unsigned int id; 128 const char *name; 129 u32 reg; 130 unsigned long flags; 131 }; 132 133 struct bm1880_pll_hw_clock { 134 struct bm1880_pll_clock pll; 135 void __iomem *base; 136 struct clk_hw hw; 137 struct clk_init_data init; 138 }; 139 140 static const struct clk_ops bm1880_pll_ops; 141 static const struct clk_ops bm1880_clk_div_ops; 142 143 #define GATE_DIV(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, \ 144 _div_shift, _div_width, _div_initval, _table, \ 145 _flags) { \ 146 .id = _id, \ 147 .parent = _parent, \ 148 .name = _name, \ 149 .gate_reg = _gate_reg, \ 150 .gate_shift = _gate_shift, \ 151 .div_reg = _div_reg, \ 152 .div_shift = _div_shift, \ 153 .div_width = _div_width, \ 154 .div_initval = _div_initval, \ 155 .table = _table, \ 156 .mux_shift = -1, \ 157 .flags = _flags, \ 158 } 159 160 #define GATE_MUX(_id, _name, _parents, _gate_reg, _gate_shift, \ 161 _mux_reg, _mux_shift, _flags) { \ 162 .id = _id, \ 163 .parents = _parents, \ 164 .num_parents = ARRAY_SIZE(_parents), \ 165 .name = _name, \ 166 .gate_reg = _gate_reg, \ 167 .gate_shift = _gate_shift, \ 168 .div_shift = -1, \ 169 .mux_reg = _mux_reg, \ 170 .mux_shift = _mux_shift, \ 171 .flags = _flags, \ 172 } 173 174 #define CLK_PLL(_id, _name, _parent, _reg, _flags) { \ 175 .pll.id = _id, \ 176 .pll.name = _name, \ 177 .pll.reg = _reg, \ 178 .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, _parent, \ 179 &bm1880_pll_ops, \ 180 _flags), \ 181 } 182 183 #define CLK_DIV(_id, _name, _parent, _reg, _shift, _width, _initval, \ 184 _table, _flags) { \ 185 .div.id = _id, \ 186 .div.name = _name, \ 187 .div.reg = _reg, \ 188 .div.shift = _shift, \ 189 .div.width = _width, \ 190 .div.initval = _initval, \ 191 .div.table = _table, \ 192 .hw.init = CLK_HW_INIT_HW(_name, _parent, \ 193 &bm1880_clk_div_ops, \ 194 _flags), \ 195 } 196 197 static struct clk_parent_data bm1880_pll_parent[] = { 198 { .fw_name = "osc", .name = "osc" }, 199 }; 200 201 /* 202 * All PLL clocks are marked as CRITICAL, hence they are very crucial 203 * for the functioning of the SoC 204 */ 205 static struct bm1880_pll_hw_clock bm1880_pll_clks[] = { 206 CLK_PLL(BM1880_CLK_MPLL, "clk_mpll", bm1880_pll_parent, 207 BM1880_CLK_MPLL_CTL, 0), 208 CLK_PLL(BM1880_CLK_SPLL, "clk_spll", bm1880_pll_parent, 209 BM1880_CLK_SPLL_CTL, 0), 210 CLK_PLL(BM1880_CLK_FPLL, "clk_fpll", bm1880_pll_parent, 211 BM1880_CLK_FPLL_CTL, 0), 212 CLK_PLL(BM1880_CLK_DDRPLL, "clk_ddrpll", bm1880_pll_parent, 213 BM1880_CLK_DDRPLL_CTL, 0), 214 }; 215 216 /* 217 * Clocks marked as CRITICAL are needed for the proper functioning 218 * of the SoC. 219 */ 220 static const struct bm1880_gate_clock bm1880_gate_clks[] = { 221 { BM1880_CLK_AHB_ROM, "clk_ahb_rom", "clk_mux_axi6", 222 BM1880_CLK_ENABLE0, 2, 0 }, 223 { BM1880_CLK_AXI_SRAM, "clk_axi_sram", "clk_axi1", 224 BM1880_CLK_ENABLE0, 3, 0 }, 225 /* 226 * Since this clock is sourcing the DDR memory, let's mark it as 227 * critical to avoid gating. 228 */ 229 { BM1880_CLK_DDR_AXI, "clk_ddr_axi", "clk_mux_axi6", 230 BM1880_CLK_ENABLE0, 4, CLK_IS_CRITICAL }, 231 { BM1880_CLK_APB_EFUSE, "clk_apb_efuse", "clk_mux_axi6", 232 BM1880_CLK_ENABLE0, 6, 0 }, 233 { BM1880_CLK_AXI5_EMMC, "clk_axi5_emmc", "clk_axi5", 234 BM1880_CLK_ENABLE0, 7, 0 }, 235 { BM1880_CLK_AXI5_SD, "clk_axi5_sd", "clk_axi5", 236 BM1880_CLK_ENABLE0, 10, 0 }, 237 { BM1880_CLK_AXI4_ETH0, "clk_axi4_eth0", "clk_axi4", 238 BM1880_CLK_ENABLE0, 14, 0 }, 239 { BM1880_CLK_AXI4_ETH1, "clk_axi4_eth1", "clk_axi4", 240 BM1880_CLK_ENABLE0, 16, 0 }, 241 { BM1880_CLK_AXI1_GDMA, "clk_axi1_gdma", "clk_axi1", 242 BM1880_CLK_ENABLE0, 17, 0 }, 243 /* Don't gate GPIO clocks as it is not owned by the GPIO driver */ 244 { BM1880_CLK_APB_GPIO, "clk_apb_gpio", "clk_mux_axi6", 245 BM1880_CLK_ENABLE0, 18, CLK_IGNORE_UNUSED }, 246 { BM1880_CLK_APB_GPIO_INTR, "clk_apb_gpio_intr", "clk_mux_axi6", 247 BM1880_CLK_ENABLE0, 19, CLK_IGNORE_UNUSED }, 248 { BM1880_CLK_AXI1_MINER, "clk_axi1_miner", "clk_axi1", 249 BM1880_CLK_ENABLE0, 21, 0 }, 250 { BM1880_CLK_AHB_SF, "clk_ahb_sf", "clk_mux_axi6", 251 BM1880_CLK_ENABLE0, 22, 0 }, 252 /* 253 * Not sure which module this clock is sourcing but gating this clock 254 * prevents the system from booting. So, let's mark it as critical. 255 */ 256 { BM1880_CLK_SDMA_AXI, "clk_sdma_axi", "clk_axi5", 257 BM1880_CLK_ENABLE0, 23, CLK_IS_CRITICAL }, 258 { BM1880_CLK_APB_I2C, "clk_apb_i2c", "clk_mux_axi6", 259 BM1880_CLK_ENABLE0, 25, 0 }, 260 { BM1880_CLK_APB_WDT, "clk_apb_wdt", "clk_mux_axi6", 261 BM1880_CLK_ENABLE0, 26, 0 }, 262 { BM1880_CLK_APB_JPEG, "clk_apb_jpeg", "clk_axi6", 263 BM1880_CLK_ENABLE0, 27, 0 }, 264 { BM1880_CLK_AXI5_NF, "clk_axi5_nf", "clk_axi5", 265 BM1880_CLK_ENABLE0, 29, 0 }, 266 { BM1880_CLK_APB_NF, "clk_apb_nf", "clk_axi6", 267 BM1880_CLK_ENABLE0, 30, 0 }, 268 { BM1880_CLK_APB_PWM, "clk_apb_pwm", "clk_mux_axi6", 269 BM1880_CLK_ENABLE1, 0, 0 }, 270 { BM1880_CLK_RV, "clk_rv", "clk_mux_rv", 271 BM1880_CLK_ENABLE1, 1, 0 }, 272 { BM1880_CLK_APB_SPI, "clk_apb_spi", "clk_mux_axi6", 273 BM1880_CLK_ENABLE1, 2, 0 }, 274 { BM1880_CLK_UART_500M, "clk_uart_500m", "clk_div_uart_500m", 275 BM1880_CLK_ENABLE1, 4, 0 }, 276 { BM1880_CLK_APB_UART, "clk_apb_uart", "clk_axi6", 277 BM1880_CLK_ENABLE1, 5, 0 }, 278 { BM1880_CLK_APB_I2S, "clk_apb_i2s", "clk_axi6", 279 BM1880_CLK_ENABLE1, 6, 0 }, 280 { BM1880_CLK_AXI4_USB, "clk_axi4_usb", "clk_axi4", 281 BM1880_CLK_ENABLE1, 7, 0 }, 282 { BM1880_CLK_APB_USB, "clk_apb_usb", "clk_axi6", 283 BM1880_CLK_ENABLE1, 8, 0 }, 284 { BM1880_CLK_12M_USB, "clk_12m_usb", "clk_div_12m_usb", 285 BM1880_CLK_ENABLE1, 11, 0 }, 286 { BM1880_CLK_APB_VIDEO, "clk_apb_video", "clk_axi6", 287 BM1880_CLK_ENABLE1, 12, 0 }, 288 { BM1880_CLK_APB_VPP, "clk_apb_vpp", "clk_axi6", 289 BM1880_CLK_ENABLE1, 15, 0 }, 290 { BM1880_CLK_AXI6, "clk_axi6", "clk_mux_axi6", 291 BM1880_CLK_ENABLE1, 21, 0 }, 292 }; 293 294 static const char * const clk_a53_parents[] = { "clk_spll", "clk_mpll" }; 295 static const char * const clk_rv_parents[] = { "clk_div_1_rv", "clk_div_0_rv" }; 296 static const char * const clk_axi1_parents[] = { "clk_div_1_axi1", "clk_div_0_axi1" }; 297 static const char * const clk_axi6_parents[] = { "clk_div_1_axi6", "clk_div_0_axi6" }; 298 299 static const struct bm1880_mux_clock bm1880_mux_clks[] = { 300 { BM1880_CLK_MUX_RV, "clk_mux_rv", clk_rv_parents, 2, 301 BM1880_CLK_SELECT, 1, 0 }, 302 { BM1880_CLK_MUX_AXI6, "clk_mux_axi6", clk_axi6_parents, 2, 303 BM1880_CLK_SELECT, 3, 0 }, 304 }; 305 306 static const struct clk_div_table bm1880_div_table_0[] = { 307 { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 }, 308 { 4, 5 }, { 5, 6 }, { 6, 7 }, { 7, 8 }, 309 { 8, 9 }, { 9, 10 }, { 10, 11 }, { 11, 12 }, 310 { 12, 13 }, { 13, 14 }, { 14, 15 }, { 15, 16 }, 311 { 16, 17 }, { 17, 18 }, { 18, 19 }, { 19, 20 }, 312 { 20, 21 }, { 21, 22 }, { 22, 23 }, { 23, 24 }, 313 { 24, 25 }, { 25, 26 }, { 26, 27 }, { 27, 28 }, 314 { 28, 29 }, { 29, 30 }, { 30, 31 }, { 31, 32 }, 315 { 0, 0 } 316 }; 317 318 static const struct clk_div_table bm1880_div_table_1[] = { 319 { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 }, 320 { 4, 5 }, { 5, 6 }, { 6, 7 }, { 7, 8 }, 321 { 8, 9 }, { 9, 10 }, { 10, 11 }, { 11, 12 }, 322 { 12, 13 }, { 13, 14 }, { 14, 15 }, { 15, 16 }, 323 { 16, 17 }, { 17, 18 }, { 18, 19 }, { 19, 20 }, 324 { 20, 21 }, { 21, 22 }, { 22, 23 }, { 23, 24 }, 325 { 24, 25 }, { 25, 26 }, { 26, 27 }, { 27, 28 }, 326 { 28, 29 }, { 29, 30 }, { 30, 31 }, { 31, 32 }, 327 { 127, 128 }, { 0, 0 } 328 }; 329 330 static const struct clk_div_table bm1880_div_table_2[] = { 331 { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 }, 332 { 4, 5 }, { 5, 6 }, { 6, 7 }, { 7, 8 }, 333 { 8, 9 }, { 9, 10 }, { 10, 11 }, { 11, 12 }, 334 { 12, 13 }, { 13, 14 }, { 14, 15 }, { 15, 16 }, 335 { 16, 17 }, { 17, 18 }, { 18, 19 }, { 19, 20 }, 336 { 20, 21 }, { 21, 22 }, { 22, 23 }, { 23, 24 }, 337 { 24, 25 }, { 25, 26 }, { 26, 27 }, { 27, 28 }, 338 { 28, 29 }, { 29, 30 }, { 30, 31 }, { 31, 32 }, 339 { 127, 128 }, { 255, 256 }, { 0, 0 } 340 }; 341 342 static const struct clk_div_table bm1880_div_table_3[] = { 343 { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 }, 344 { 4, 5 }, { 5, 6 }, { 6, 7 }, { 7, 8 }, 345 { 8, 9 }, { 9, 10 }, { 10, 11 }, { 11, 12 }, 346 { 12, 13 }, { 13, 14 }, { 14, 15 }, { 15, 16 }, 347 { 16, 17 }, { 17, 18 }, { 18, 19 }, { 19, 20 }, 348 { 20, 21 }, { 21, 22 }, { 22, 23 }, { 23, 24 }, 349 { 24, 25 }, { 25, 26 }, { 26, 27 }, { 27, 28 }, 350 { 28, 29 }, { 29, 30 }, { 30, 31 }, { 31, 32 }, 351 { 127, 128 }, { 255, 256 }, { 511, 512 }, { 0, 0 } 352 }; 353 354 static const struct clk_div_table bm1880_div_table_4[] = { 355 { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 }, 356 { 4, 5 }, { 5, 6 }, { 6, 7 }, { 7, 8 }, 357 { 8, 9 }, { 9, 10 }, { 10, 11 }, { 11, 12 }, 358 { 12, 13 }, { 13, 14 }, { 14, 15 }, { 15, 16 }, 359 { 16, 17 }, { 17, 18 }, { 18, 19 }, { 19, 20 }, 360 { 20, 21 }, { 21, 22 }, { 22, 23 }, { 23, 24 }, 361 { 24, 25 }, { 25, 26 }, { 26, 27 }, { 27, 28 }, 362 { 28, 29 }, { 29, 30 }, { 30, 31 }, { 31, 32 }, 363 { 127, 128 }, { 255, 256 }, { 511, 512 }, { 65535, 65536 }, 364 { 0, 0 } 365 }; 366 367 /* 368 * Clocks marked as CRITICAL are needed for the proper functioning 369 * of the SoC. 370 */ 371 static struct bm1880_div_hw_clock bm1880_div_clks[] = { 372 CLK_DIV(BM1880_CLK_DIV_0_RV, "clk_div_0_rv", &bm1880_pll_clks[1].hw, 373 BM1880_CLK_DIV12, 16, 5, 1, bm1880_div_table_0, 0), 374 CLK_DIV(BM1880_CLK_DIV_1_RV, "clk_div_1_rv", &bm1880_pll_clks[2].hw, 375 BM1880_CLK_DIV13, 16, 5, 1, bm1880_div_table_0, 0), 376 CLK_DIV(BM1880_CLK_DIV_UART_500M, "clk_div_uart_500m", &bm1880_pll_clks[2].hw, 377 BM1880_CLK_DIV15, 16, 7, 3, bm1880_div_table_1, 0), 378 CLK_DIV(BM1880_CLK_DIV_0_AXI1, "clk_div_0_axi1", &bm1880_pll_clks[0].hw, 379 BM1880_CLK_DIV21, 16, 5, 2, bm1880_div_table_0, 380 0), 381 CLK_DIV(BM1880_CLK_DIV_1_AXI1, "clk_div_1_axi1", &bm1880_pll_clks[2].hw, 382 BM1880_CLK_DIV22, 16, 5, 3, bm1880_div_table_0, 383 0), 384 CLK_DIV(BM1880_CLK_DIV_0_AXI6, "clk_div_0_axi6", &bm1880_pll_clks[2].hw, 385 BM1880_CLK_DIV27, 16, 5, 15, bm1880_div_table_0, 386 0), 387 CLK_DIV(BM1880_CLK_DIV_1_AXI6, "clk_div_1_axi6", &bm1880_pll_clks[0].hw, 388 BM1880_CLK_DIV28, 16, 5, 11, bm1880_div_table_0, 389 0), 390 CLK_DIV(BM1880_CLK_DIV_12M_USB, "clk_div_12m_usb", &bm1880_pll_clks[2].hw, 391 BM1880_CLK_DIV18, 16, 7, 125, bm1880_div_table_1, 0), 392 }; 393 394 /* 395 * Clocks marked as CRITICAL are all needed for the proper functioning 396 * of the SoC. 397 */ 398 static struct bm1880_composite_clock bm1880_composite_clks[] = { 399 /* 400 * Since clk_a53 and clk_50m_a53 clocks are sourcing the CPU core, 401 * let's mark them as critical to avoid gating. 402 */ 403 GATE_MUX(BM1880_CLK_A53, "clk_a53", clk_a53_parents, 404 BM1880_CLK_ENABLE0, 0, BM1880_CLK_SELECT, 0, 405 CLK_IS_CRITICAL), 406 GATE_DIV(BM1880_CLK_50M_A53, "clk_50m_a53", "clk_fpll", 407 BM1880_CLK_ENABLE0, 1, BM1880_CLK_DIV0, 16, 5, 30, 408 bm1880_div_table_0, CLK_IS_CRITICAL), 409 GATE_DIV(BM1880_CLK_EFUSE, "clk_efuse", "clk_fpll", 410 BM1880_CLK_ENABLE0, 5, BM1880_CLK_DIV1, 16, 7, 60, 411 bm1880_div_table_1, 0), 412 GATE_DIV(BM1880_CLK_EMMC, "clk_emmc", "clk_fpll", 413 BM1880_CLK_ENABLE0, 8, BM1880_CLK_DIV2, 16, 5, 15, 414 bm1880_div_table_0, 0), 415 GATE_DIV(BM1880_CLK_100K_EMMC, "clk_100k_emmc", "clk_div_12m_usb", 416 BM1880_CLK_ENABLE0, 9, BM1880_CLK_DIV3, 16, 8, 120, 417 bm1880_div_table_2, 0), 418 GATE_DIV(BM1880_CLK_SD, "clk_sd", "clk_fpll", 419 BM1880_CLK_ENABLE0, 11, BM1880_CLK_DIV4, 16, 5, 15, 420 bm1880_div_table_0, 0), 421 GATE_DIV(BM1880_CLK_100K_SD, "clk_100k_sd", "clk_div_12m_usb", 422 BM1880_CLK_ENABLE0, 12, BM1880_CLK_DIV5, 16, 8, 120, 423 bm1880_div_table_2, 0), 424 GATE_DIV(BM1880_CLK_500M_ETH0, "clk_500m_eth0", "clk_fpll", 425 BM1880_CLK_ENABLE0, 13, BM1880_CLK_DIV6, 16, 5, 3, 426 bm1880_div_table_0, 0), 427 GATE_DIV(BM1880_CLK_500M_ETH1, "clk_500m_eth1", "clk_fpll", 428 BM1880_CLK_ENABLE0, 15, BM1880_CLK_DIV7, 16, 5, 3, 429 bm1880_div_table_0, 0), 430 /* Don't gate GPIO clocks as it is not owned by the GPIO driver */ 431 GATE_DIV(BM1880_CLK_GPIO_DB, "clk_gpio_db", "clk_div_12m_usb", 432 BM1880_CLK_ENABLE0, 20, BM1880_CLK_DIV8, 16, 16, 120, 433 bm1880_div_table_4, CLK_IGNORE_UNUSED), 434 GATE_DIV(BM1880_CLK_SDMA_AUD, "clk_sdma_aud", "clk_fpll", 435 BM1880_CLK_ENABLE0, 24, BM1880_CLK_DIV9, 16, 7, 61, 436 bm1880_div_table_1, 0), 437 GATE_DIV(BM1880_CLK_JPEG_AXI, "clk_jpeg_axi", "clk_fpll", 438 BM1880_CLK_ENABLE0, 28, BM1880_CLK_DIV10, 16, 5, 4, 439 bm1880_div_table_0, 0), 440 GATE_DIV(BM1880_CLK_NF, "clk_nf", "clk_fpll", 441 BM1880_CLK_ENABLE0, 31, BM1880_CLK_DIV11, 16, 5, 30, 442 bm1880_div_table_0, 0), 443 GATE_DIV(BM1880_CLK_TPU_AXI, "clk_tpu_axi", "clk_spll", 444 BM1880_CLK_ENABLE1, 3, BM1880_CLK_DIV14, 16, 5, 1, 445 bm1880_div_table_0, 0), 446 GATE_DIV(BM1880_CLK_125M_USB, "clk_125m_usb", "clk_fpll", 447 BM1880_CLK_ENABLE1, 9, BM1880_CLK_DIV16, 16, 5, 12, 448 bm1880_div_table_0, 0), 449 GATE_DIV(BM1880_CLK_33K_USB, "clk_33k_usb", "clk_div_12m_usb", 450 BM1880_CLK_ENABLE1, 10, BM1880_CLK_DIV17, 16, 9, 363, 451 bm1880_div_table_3, 0), 452 GATE_DIV(BM1880_CLK_VIDEO_AXI, "clk_video_axi", "clk_fpll", 453 BM1880_CLK_ENABLE1, 13, BM1880_CLK_DIV19, 16, 5, 4, 454 bm1880_div_table_0, 0), 455 GATE_DIV(BM1880_CLK_VPP_AXI, "clk_vpp_axi", "clk_fpll", 456 BM1880_CLK_ENABLE1, 14, BM1880_CLK_DIV20, 16, 5, 4, 457 bm1880_div_table_0, 0), 458 GATE_MUX(BM1880_CLK_AXI1, "clk_axi1", clk_axi1_parents, 459 BM1880_CLK_ENABLE1, 15, BM1880_CLK_SELECT, 2, 0), 460 GATE_DIV(BM1880_CLK_AXI2, "clk_axi2", "clk_fpll", 461 BM1880_CLK_ENABLE1, 17, BM1880_CLK_DIV23, 16, 5, 3, 462 bm1880_div_table_0, 0), 463 GATE_DIV(BM1880_CLK_AXI3, "clk_axi3", "clk_mux_rv", 464 BM1880_CLK_ENABLE1, 18, BM1880_CLK_DIV24, 16, 5, 2, 465 bm1880_div_table_0, 0), 466 GATE_DIV(BM1880_CLK_AXI4, "clk_axi4", "clk_fpll", 467 BM1880_CLK_ENABLE1, 19, BM1880_CLK_DIV25, 16, 5, 6, 468 bm1880_div_table_0, 0), 469 GATE_DIV(BM1880_CLK_AXI5, "clk_axi5", "clk_fpll", 470 BM1880_CLK_ENABLE1, 20, BM1880_CLK_DIV26, 16, 5, 15, 471 bm1880_div_table_0, 0), 472 }; 473 474 static unsigned long bm1880_pll_rate_calc(u32 regval, unsigned long parent_rate) 475 { 476 u64 numerator; 477 u32 fbdiv, fref, refdiv; 478 u32 postdiv1, postdiv2, denominator; 479 480 fbdiv = (regval >> 16) & 0xfff; 481 fref = parent_rate; 482 refdiv = regval & 0x1f; 483 postdiv1 = (regval >> 8) & 0x7; 484 postdiv2 = (regval >> 12) & 0x7; 485 486 numerator = parent_rate * fbdiv; 487 denominator = refdiv * postdiv1 * postdiv2; 488 do_div(numerator, denominator); 489 490 return (unsigned long)numerator; 491 } 492 493 static unsigned long bm1880_pll_recalc_rate(struct clk_hw *hw, 494 unsigned long parent_rate) 495 { 496 struct bm1880_pll_hw_clock *pll_hw = to_bm1880_pll_clk(hw); 497 unsigned long rate; 498 u32 regval; 499 500 regval = readl(pll_hw->base + pll_hw->pll.reg); 501 rate = bm1880_pll_rate_calc(regval, parent_rate); 502 503 return rate; 504 } 505 506 static const struct clk_ops bm1880_pll_ops = { 507 .recalc_rate = bm1880_pll_recalc_rate, 508 }; 509 510 static struct clk_hw *bm1880_clk_register_pll(struct bm1880_pll_hw_clock *pll_clk, 511 void __iomem *sys_base) 512 { 513 struct clk_hw *hw; 514 int err; 515 516 pll_clk->base = sys_base; 517 hw = &pll_clk->hw; 518 519 err = clk_hw_register(NULL, hw); 520 if (err) 521 return ERR_PTR(err); 522 523 return hw; 524 } 525 526 static void bm1880_clk_unregister_pll(struct clk_hw *hw) 527 { 528 struct bm1880_pll_hw_clock *pll_hw = to_bm1880_pll_clk(hw); 529 530 clk_hw_unregister(hw); 531 kfree(pll_hw); 532 } 533 534 static int bm1880_clk_register_plls(struct bm1880_pll_hw_clock *clks, 535 int num_clks, 536 struct bm1880_clock_data *data) 537 { 538 struct clk_hw *hw; 539 void __iomem *pll_base = data->pll_base; 540 int i; 541 542 for (i = 0; i < num_clks; i++) { 543 struct bm1880_pll_hw_clock *bm1880_clk = &clks[i]; 544 545 hw = bm1880_clk_register_pll(bm1880_clk, pll_base); 546 if (IS_ERR(hw)) { 547 pr_err("%s: failed to register clock %s\n", 548 __func__, bm1880_clk->pll.name); 549 goto err_clk; 550 } 551 552 data->hw_data.hws[clks[i].pll.id] = hw; 553 } 554 555 return 0; 556 557 err_clk: 558 while (i--) 559 bm1880_clk_unregister_pll(data->hw_data.hws[clks[i].pll.id]); 560 561 return PTR_ERR(hw); 562 } 563 564 static int bm1880_clk_register_mux(const struct bm1880_mux_clock *clks, 565 int num_clks, 566 struct bm1880_clock_data *data) 567 { 568 struct clk_hw *hw; 569 void __iomem *sys_base = data->sys_base; 570 int i; 571 572 for (i = 0; i < num_clks; i++) { 573 hw = clk_hw_register_mux(NULL, clks[i].name, 574 clks[i].parents, 575 clks[i].num_parents, 576 clks[i].flags, 577 sys_base + clks[i].reg, 578 clks[i].shift, 1, 0, 579 &bm1880_clk_lock); 580 if (IS_ERR(hw)) { 581 pr_err("%s: failed to register clock %s\n", 582 __func__, clks[i].name); 583 goto err_clk; 584 } 585 586 data->hw_data.hws[clks[i].id] = hw; 587 } 588 589 return 0; 590 591 err_clk: 592 while (i--) 593 clk_hw_unregister_mux(data->hw_data.hws[clks[i].id]); 594 595 return PTR_ERR(hw); 596 } 597 598 static unsigned long bm1880_clk_div_recalc_rate(struct clk_hw *hw, 599 unsigned long parent_rate) 600 { 601 struct bm1880_div_hw_clock *div_hw = to_bm1880_div_clk(hw); 602 struct bm1880_div_clock *div = &div_hw->div; 603 void __iomem *reg_addr = div_hw->base + div->reg; 604 unsigned int val; 605 unsigned long rate; 606 607 if (!(readl(reg_addr) & BIT(3))) { 608 val = div->initval; 609 } else { 610 val = readl(reg_addr) >> div->shift; 611 val &= clk_div_mask(div->width); 612 } 613 614 rate = divider_recalc_rate(hw, parent_rate, val, div->table, 615 div->flags, div->width); 616 617 return rate; 618 } 619 620 static long bm1880_clk_div_round_rate(struct clk_hw *hw, unsigned long rate, 621 unsigned long *prate) 622 { 623 struct bm1880_div_hw_clock *div_hw = to_bm1880_div_clk(hw); 624 struct bm1880_div_clock *div = &div_hw->div; 625 void __iomem *reg_addr = div_hw->base + div->reg; 626 627 if (div->flags & CLK_DIVIDER_READ_ONLY) { 628 u32 val; 629 630 val = readl(reg_addr) >> div->shift; 631 val &= clk_div_mask(div->width); 632 633 return divider_ro_round_rate(hw, rate, prate, div->table, 634 div->width, div->flags, 635 val); 636 } 637 638 return divider_round_rate(hw, rate, prate, div->table, 639 div->width, div->flags); 640 } 641 642 static int bm1880_clk_div_set_rate(struct clk_hw *hw, unsigned long rate, 643 unsigned long parent_rate) 644 { 645 struct bm1880_div_hw_clock *div_hw = to_bm1880_div_clk(hw); 646 struct bm1880_div_clock *div = &div_hw->div; 647 void __iomem *reg_addr = div_hw->base + div->reg; 648 unsigned long flags = 0; 649 int value; 650 u32 val; 651 652 value = divider_get_val(rate, parent_rate, div->table, 653 div->width, div_hw->div.flags); 654 if (value < 0) 655 return value; 656 657 if (div_hw->lock) 658 spin_lock_irqsave(div_hw->lock, flags); 659 else 660 __acquire(div_hw->lock); 661 662 val = readl(reg_addr); 663 val &= ~(clk_div_mask(div->width) << div_hw->div.shift); 664 val |= (u32)value << div->shift; 665 writel(val, reg_addr); 666 667 if (div_hw->lock) 668 spin_unlock_irqrestore(div_hw->lock, flags); 669 else 670 __release(div_hw->lock); 671 672 return 0; 673 } 674 675 static const struct clk_ops bm1880_clk_div_ops = { 676 .recalc_rate = bm1880_clk_div_recalc_rate, 677 .round_rate = bm1880_clk_div_round_rate, 678 .set_rate = bm1880_clk_div_set_rate, 679 }; 680 681 static struct clk_hw *bm1880_clk_register_div(struct bm1880_div_hw_clock *div_clk, 682 void __iomem *sys_base) 683 { 684 struct clk_hw *hw; 685 int err; 686 687 div_clk->div.flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO; 688 div_clk->base = sys_base; 689 div_clk->lock = &bm1880_clk_lock; 690 691 hw = &div_clk->hw; 692 err = clk_hw_register(NULL, hw); 693 if (err) 694 return ERR_PTR(err); 695 696 return hw; 697 } 698 699 static void bm1880_clk_unregister_div(struct clk_hw *hw) 700 { 701 struct bm1880_div_hw_clock *div_hw = to_bm1880_div_clk(hw); 702 703 clk_hw_unregister(hw); 704 kfree(div_hw); 705 } 706 707 static int bm1880_clk_register_divs(struct bm1880_div_hw_clock *clks, 708 int num_clks, 709 struct bm1880_clock_data *data) 710 { 711 struct clk_hw *hw; 712 void __iomem *sys_base = data->sys_base; 713 unsigned int i, id; 714 715 for (i = 0; i < num_clks; i++) { 716 struct bm1880_div_hw_clock *bm1880_clk = &clks[i]; 717 718 hw = bm1880_clk_register_div(bm1880_clk, sys_base); 719 if (IS_ERR(hw)) { 720 pr_err("%s: failed to register clock %s\n", 721 __func__, bm1880_clk->div.name); 722 goto err_clk; 723 } 724 725 id = clks[i].div.id; 726 data->hw_data.hws[id] = hw; 727 } 728 729 return 0; 730 731 err_clk: 732 while (i--) 733 bm1880_clk_unregister_div(data->hw_data.hws[clks[i].div.id]); 734 735 return PTR_ERR(hw); 736 } 737 738 static int bm1880_clk_register_gate(const struct bm1880_gate_clock *clks, 739 int num_clks, 740 struct bm1880_clock_data *data) 741 { 742 struct clk_hw *hw; 743 void __iomem *sys_base = data->sys_base; 744 int i; 745 746 for (i = 0; i < num_clks; i++) { 747 hw = clk_hw_register_gate(NULL, clks[i].name, 748 clks[i].parent, 749 clks[i].flags, 750 sys_base + clks[i].gate_reg, 751 clks[i].gate_shift, 0, 752 &bm1880_clk_lock); 753 if (IS_ERR(hw)) { 754 pr_err("%s: failed to register clock %s\n", 755 __func__, clks[i].name); 756 goto err_clk; 757 } 758 759 data->hw_data.hws[clks[i].id] = hw; 760 } 761 762 return 0; 763 764 err_clk: 765 while (i--) 766 clk_hw_unregister_gate(data->hw_data.hws[clks[i].id]); 767 768 return PTR_ERR(hw); 769 } 770 771 static struct clk_hw *bm1880_clk_register_composite(struct bm1880_composite_clock *clks, 772 void __iomem *sys_base) 773 { 774 struct clk_hw *hw; 775 struct clk_mux *mux = NULL; 776 struct clk_gate *gate = NULL; 777 struct bm1880_div_hw_clock *div_hws = NULL; 778 struct clk_hw *mux_hw = NULL, *gate_hw = NULL, *div_hw = NULL; 779 const struct clk_ops *mux_ops = NULL, *gate_ops = NULL, *div_ops = NULL; 780 const char * const *parent_names; 781 const char *parent; 782 int num_parents; 783 int ret; 784 785 if (clks->mux_shift >= 0) { 786 mux = kzalloc(sizeof(*mux), GFP_KERNEL); 787 if (!mux) 788 return ERR_PTR(-ENOMEM); 789 790 mux->reg = sys_base + clks->mux_reg; 791 mux->mask = 1; 792 mux->shift = clks->mux_shift; 793 mux_hw = &mux->hw; 794 mux_ops = &clk_mux_ops; 795 mux->lock = &bm1880_clk_lock; 796 797 parent_names = clks->parents; 798 num_parents = clks->num_parents; 799 } else { 800 parent = clks->parent; 801 parent_names = &parent; 802 num_parents = 1; 803 } 804 805 if (clks->gate_shift >= 0) { 806 gate = kzalloc(sizeof(*gate), GFP_KERNEL); 807 if (!gate) { 808 ret = -ENOMEM; 809 goto err_out; 810 } 811 812 gate->reg = sys_base + clks->gate_reg; 813 gate->bit_idx = clks->gate_shift; 814 gate->lock = &bm1880_clk_lock; 815 816 gate_hw = &gate->hw; 817 gate_ops = &clk_gate_ops; 818 } 819 820 if (clks->div_shift >= 0) { 821 div_hws = kzalloc(sizeof(*div_hws), GFP_KERNEL); 822 if (!div_hws) { 823 ret = -ENOMEM; 824 goto err_out; 825 } 826 827 div_hws->base = sys_base; 828 div_hws->div.reg = clks->div_reg; 829 div_hws->div.shift = clks->div_shift; 830 div_hws->div.width = clks->div_width; 831 div_hws->div.table = clks->table; 832 div_hws->div.initval = clks->div_initval; 833 div_hws->lock = &bm1880_clk_lock; 834 div_hws->div.flags = CLK_DIVIDER_ONE_BASED | 835 CLK_DIVIDER_ALLOW_ZERO; 836 837 div_hw = &div_hws->hw; 838 div_ops = &bm1880_clk_div_ops; 839 } 840 841 hw = clk_hw_register_composite(NULL, clks->name, parent_names, 842 num_parents, mux_hw, mux_ops, div_hw, 843 div_ops, gate_hw, gate_ops, 844 clks->flags); 845 846 if (IS_ERR(hw)) { 847 ret = PTR_ERR(hw); 848 goto err_out; 849 } 850 851 return hw; 852 853 err_out: 854 kfree(div_hws); 855 kfree(gate); 856 kfree(mux); 857 858 return ERR_PTR(ret); 859 } 860 861 static int bm1880_clk_register_composites(struct bm1880_composite_clock *clks, 862 int num_clks, 863 struct bm1880_clock_data *data) 864 { 865 struct clk_hw *hw; 866 void __iomem *sys_base = data->sys_base; 867 int i; 868 869 for (i = 0; i < num_clks; i++) { 870 struct bm1880_composite_clock *bm1880_clk = &clks[i]; 871 872 hw = bm1880_clk_register_composite(bm1880_clk, sys_base); 873 if (IS_ERR(hw)) { 874 pr_err("%s: failed to register clock %s\n", 875 __func__, bm1880_clk->name); 876 goto err_clk; 877 } 878 879 data->hw_data.hws[clks[i].id] = hw; 880 } 881 882 return 0; 883 884 err_clk: 885 while (i--) 886 clk_hw_unregister_composite(data->hw_data.hws[clks[i].id]); 887 888 return PTR_ERR(hw); 889 } 890 891 static int bm1880_clk_probe(struct platform_device *pdev) 892 { 893 struct bm1880_clock_data *clk_data; 894 void __iomem *pll_base, *sys_base; 895 struct device *dev = &pdev->dev; 896 struct resource *res; 897 int num_clks, i; 898 899 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 900 pll_base = devm_ioremap_resource(&pdev->dev, res); 901 if (IS_ERR(pll_base)) 902 return PTR_ERR(pll_base); 903 904 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 905 sys_base = devm_ioremap_resource(&pdev->dev, res); 906 if (IS_ERR(sys_base)) 907 return PTR_ERR(sys_base); 908 909 num_clks = ARRAY_SIZE(bm1880_pll_clks) + 910 ARRAY_SIZE(bm1880_div_clks) + 911 ARRAY_SIZE(bm1880_mux_clks) + 912 ARRAY_SIZE(bm1880_composite_clks) + 913 ARRAY_SIZE(bm1880_gate_clks); 914 915 clk_data = devm_kzalloc(dev, struct_size(clk_data, hw_data.hws, 916 num_clks), GFP_KERNEL); 917 if (!clk_data) 918 return -ENOMEM; 919 920 clk_data->pll_base = pll_base; 921 clk_data->sys_base = sys_base; 922 923 for (i = 0; i < num_clks; i++) 924 clk_data->hw_data.hws[i] = ERR_PTR(-ENOENT); 925 926 clk_data->hw_data.num = num_clks; 927 928 bm1880_clk_register_plls(bm1880_pll_clks, 929 ARRAY_SIZE(bm1880_pll_clks), 930 clk_data); 931 932 bm1880_clk_register_divs(bm1880_div_clks, 933 ARRAY_SIZE(bm1880_div_clks), 934 clk_data); 935 936 bm1880_clk_register_mux(bm1880_mux_clks, 937 ARRAY_SIZE(bm1880_mux_clks), 938 clk_data); 939 940 bm1880_clk_register_composites(bm1880_composite_clks, 941 ARRAY_SIZE(bm1880_composite_clks), 942 clk_data); 943 944 bm1880_clk_register_gate(bm1880_gate_clks, 945 ARRAY_SIZE(bm1880_gate_clks), 946 clk_data); 947 948 return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, 949 &clk_data->hw_data); 950 } 951 952 static const struct of_device_id bm1880_of_match[] = { 953 { .compatible = "bitmain,bm1880-clk", }, 954 {} 955 }; 956 MODULE_DEVICE_TABLE(of, bm1880_of_match); 957 958 static struct platform_driver bm1880_clk_driver = { 959 .driver = { 960 .name = "bm1880-clk", 961 .of_match_table = bm1880_of_match, 962 }, 963 .probe = bm1880_clk_probe, 964 }; 965 module_platform_driver(bm1880_clk_driver); 966 967 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>"); 968 MODULE_DESCRIPTION("Clock driver for Bitmain BM1880 SoC"); 969 MODULE_LICENSE("GPL v2"); 970