xref: /openbmc/linux/drivers/clk/clk-axi-clkgen.c (revision e23feb16)
1 /*
2  * AXI clkgen driver
3  *
4  * Copyright 2012-2013 Analog Devices Inc.
5  *  Author: Lars-Peter Clausen <lars@metafoo.de>
6  *
7  * Licensed under the GPL-2.
8  *
9  */
10 
11 #include <linux/platform_device.h>
12 #include <linux/clk-provider.h>
13 #include <linux/clk.h>
14 #include <linux/slab.h>
15 #include <linux/io.h>
16 #include <linux/of.h>
17 #include <linux/module.h>
18 #include <linux/err.h>
19 
20 #define AXI_CLKGEN_REG_UPDATE_ENABLE	0x04
21 #define AXI_CLKGEN_REG_CLK_OUT1		0x08
22 #define AXI_CLKGEN_REG_CLK_OUT2		0x0c
23 #define AXI_CLKGEN_REG_CLK_DIV		0x10
24 #define AXI_CLKGEN_REG_CLK_FB1		0x14
25 #define AXI_CLKGEN_REG_CLK_FB2		0x18
26 #define AXI_CLKGEN_REG_LOCK1		0x1c
27 #define AXI_CLKGEN_REG_LOCK2		0x20
28 #define AXI_CLKGEN_REG_LOCK3		0x24
29 #define AXI_CLKGEN_REG_FILTER1		0x28
30 #define AXI_CLKGEN_REG_FILTER2		0x2c
31 
32 struct axi_clkgen {
33 	void __iomem *base;
34 	struct clk_hw clk_hw;
35 };
36 
37 static uint32_t axi_clkgen_lookup_filter(unsigned int m)
38 {
39 	switch (m) {
40 	case 0:
41 		return 0x01001990;
42 	case 1:
43 		return 0x01001190;
44 	case 2:
45 		return 0x01009890;
46 	case 3:
47 		return 0x01001890;
48 	case 4:
49 		return 0x01008890;
50 	case 5 ... 8:
51 		return 0x01009090;
52 	case 9 ... 11:
53 		return 0x01000890;
54 	case 12:
55 		return 0x08009090;
56 	case 13 ... 22:
57 		return 0x01001090;
58 	case 23 ... 36:
59 		return 0x01008090;
60 	case 37 ... 46:
61 		return 0x08001090;
62 	default:
63 		return 0x08008090;
64 	}
65 }
66 
67 static const uint32_t axi_clkgen_lock_table[] = {
68 	0x060603e8, 0x060603e8, 0x080803e8, 0x0b0b03e8,
69 	0x0e0e03e8, 0x111103e8, 0x131303e8, 0x161603e8,
70 	0x191903e8, 0x1c1c03e8, 0x1f1f0384, 0x1f1f0339,
71 	0x1f1f02ee, 0x1f1f02bc, 0x1f1f028a, 0x1f1f0271,
72 	0x1f1f023f, 0x1f1f0226, 0x1f1f020d, 0x1f1f01f4,
73 	0x1f1f01db, 0x1f1f01c2, 0x1f1f01a9, 0x1f1f0190,
74 	0x1f1f0190, 0x1f1f0177, 0x1f1f015e, 0x1f1f015e,
75 	0x1f1f0145, 0x1f1f0145, 0x1f1f012c, 0x1f1f012c,
76 	0x1f1f012c, 0x1f1f0113, 0x1f1f0113, 0x1f1f0113,
77 };
78 
79 static uint32_t axi_clkgen_lookup_lock(unsigned int m)
80 {
81 	if (m < ARRAY_SIZE(axi_clkgen_lock_table))
82 		return axi_clkgen_lock_table[m];
83 	return 0x1f1f00fa;
84 }
85 
86 static const unsigned int fpfd_min = 10000;
87 static const unsigned int fpfd_max = 300000;
88 static const unsigned int fvco_min = 600000;
89 static const unsigned int fvco_max = 1200000;
90 
91 static void axi_clkgen_calc_params(unsigned long fin, unsigned long fout,
92 	unsigned int *best_d, unsigned int *best_m, unsigned int *best_dout)
93 {
94 	unsigned long d, d_min, d_max, _d_min, _d_max;
95 	unsigned long m, m_min, m_max;
96 	unsigned long f, dout, best_f, fvco;
97 
98 	fin /= 1000;
99 	fout /= 1000;
100 
101 	best_f = ULONG_MAX;
102 	*best_d = 0;
103 	*best_m = 0;
104 	*best_dout = 0;
105 
106 	d_min = max_t(unsigned long, DIV_ROUND_UP(fin, fpfd_max), 1);
107 	d_max = min_t(unsigned long, fin / fpfd_min, 80);
108 
109 	m_min = max_t(unsigned long, DIV_ROUND_UP(fvco_min, fin) * d_min, 1);
110 	m_max = min_t(unsigned long, fvco_max * d_max / fin, 64);
111 
112 	for (m = m_min; m <= m_max; m++) {
113 		_d_min = max(d_min, DIV_ROUND_UP(fin * m, fvco_max));
114 		_d_max = min(d_max, fin * m / fvco_min);
115 
116 		for (d = _d_min; d <= _d_max; d++) {
117 			fvco = fin * m / d;
118 
119 			dout = DIV_ROUND_CLOSEST(fvco, fout);
120 			dout = clamp_t(unsigned long, dout, 1, 128);
121 			f = fvco / dout;
122 			if (abs(f - fout) < abs(best_f - fout)) {
123 				best_f = f;
124 				*best_d = d;
125 				*best_m = m;
126 				*best_dout = dout;
127 				if (best_f == fout)
128 					return;
129 			}
130 		}
131 	}
132 }
133 
134 static void axi_clkgen_calc_clk_params(unsigned int divider, unsigned int *low,
135 	unsigned int *high, unsigned int *edge, unsigned int *nocount)
136 {
137 	if (divider == 1)
138 		*nocount = 1;
139 	else
140 		*nocount = 0;
141 
142 	*high = divider / 2;
143 	*edge = divider % 2;
144 	*low = divider - *high;
145 }
146 
147 static void axi_clkgen_write(struct axi_clkgen *axi_clkgen,
148 	unsigned int reg, unsigned int val)
149 {
150 	writel(val, axi_clkgen->base + reg);
151 }
152 
153 static void axi_clkgen_read(struct axi_clkgen *axi_clkgen,
154 	unsigned int reg, unsigned int *val)
155 {
156 	*val = readl(axi_clkgen->base + reg);
157 }
158 
159 static struct axi_clkgen *clk_hw_to_axi_clkgen(struct clk_hw *clk_hw)
160 {
161 	return container_of(clk_hw, struct axi_clkgen, clk_hw);
162 }
163 
164 static int axi_clkgen_set_rate(struct clk_hw *clk_hw,
165 	unsigned long rate, unsigned long parent_rate)
166 {
167 	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
168 	unsigned int d, m, dout;
169 	unsigned int nocount;
170 	unsigned int high;
171 	unsigned int edge;
172 	unsigned int low;
173 	uint32_t filter;
174 	uint32_t lock;
175 
176 	if (parent_rate == 0 || rate == 0)
177 		return -EINVAL;
178 
179 	axi_clkgen_calc_params(parent_rate, rate, &d, &m, &dout);
180 
181 	if (d == 0 || dout == 0 || m == 0)
182 		return -EINVAL;
183 
184 	filter = axi_clkgen_lookup_filter(m - 1);
185 	lock = axi_clkgen_lookup_lock(m - 1);
186 
187 	axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_UPDATE_ENABLE, 0);
188 
189 	axi_clkgen_calc_clk_params(dout, &low, &high, &edge, &nocount);
190 	axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_CLK_OUT1,
191 		(high << 6) | low);
192 	axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_CLK_OUT2,
193 		(edge << 7) | (nocount << 6));
194 
195 	axi_clkgen_calc_clk_params(d, &low, &high, &edge, &nocount);
196 	axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_CLK_DIV,
197 		(edge << 13) | (nocount << 12) | (high << 6) | low);
198 
199 	axi_clkgen_calc_clk_params(m, &low, &high, &edge, &nocount);
200 	axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_CLK_FB1,
201 		(high << 6) | low);
202 	axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_CLK_FB2,
203 		(edge << 7) | (nocount << 6));
204 
205 	axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_LOCK1, lock & 0x3ff);
206 	axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_LOCK2,
207 		(((lock >> 16) & 0x1f) << 10) | 0x1);
208 	axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_LOCK3,
209 		(((lock >> 24) & 0x1f) << 10) | 0x3e9);
210 	axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_FILTER1, filter >> 16);
211 	axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_FILTER2, filter);
212 
213 	axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_UPDATE_ENABLE, 1);
214 
215 	return 0;
216 }
217 
218 static long axi_clkgen_round_rate(struct clk_hw *hw, unsigned long rate,
219 	unsigned long *parent_rate)
220 {
221 	unsigned int d, m, dout;
222 
223 	axi_clkgen_calc_params(*parent_rate, rate, &d, &m, &dout);
224 
225 	if (d == 0 || dout == 0 || m == 0)
226 		return -EINVAL;
227 
228 	return *parent_rate / d * m / dout;
229 }
230 
231 static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw,
232 	unsigned long parent_rate)
233 {
234 	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
235 	unsigned int d, m, dout;
236 	unsigned int reg;
237 	unsigned long long tmp;
238 
239 	axi_clkgen_read(axi_clkgen, AXI_CLKGEN_REG_CLK_OUT1, &reg);
240 	dout = (reg & 0x3f) + ((reg >> 6) & 0x3f);
241 	axi_clkgen_read(axi_clkgen, AXI_CLKGEN_REG_CLK_DIV, &reg);
242 	d = (reg & 0x3f) + ((reg >> 6) & 0x3f);
243 	axi_clkgen_read(axi_clkgen, AXI_CLKGEN_REG_CLK_FB1, &reg);
244 	m = (reg & 0x3f) + ((reg >> 6) & 0x3f);
245 
246 	if (d == 0 || dout == 0)
247 		return 0;
248 
249 	tmp = (unsigned long long)(parent_rate / d) * m;
250 	do_div(tmp, dout);
251 
252 	if (tmp > ULONG_MAX)
253 		return ULONG_MAX;
254 
255 	return tmp;
256 }
257 
258 static const struct clk_ops axi_clkgen_ops = {
259 	.recalc_rate = axi_clkgen_recalc_rate,
260 	.round_rate = axi_clkgen_round_rate,
261 	.set_rate = axi_clkgen_set_rate,
262 };
263 
264 static int axi_clkgen_probe(struct platform_device *pdev)
265 {
266 	struct axi_clkgen *axi_clkgen;
267 	struct clk_init_data init;
268 	const char *parent_name;
269 	const char *clk_name;
270 	struct resource *mem;
271 	struct clk *clk;
272 
273 	axi_clkgen = devm_kzalloc(&pdev->dev, sizeof(*axi_clkgen), GFP_KERNEL);
274 	if (!axi_clkgen)
275 		return -ENOMEM;
276 
277 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
278 	axi_clkgen->base = devm_ioremap_resource(&pdev->dev, mem);
279 	if (IS_ERR(axi_clkgen->base))
280 		return PTR_ERR(axi_clkgen->base);
281 
282 	parent_name = of_clk_get_parent_name(pdev->dev.of_node, 0);
283 	if (!parent_name)
284 		return -EINVAL;
285 
286 	clk_name = pdev->dev.of_node->name;
287 	of_property_read_string(pdev->dev.of_node, "clock-output-names",
288 		&clk_name);
289 
290 	init.name = clk_name;
291 	init.ops = &axi_clkgen_ops;
292 	init.flags = 0;
293 	init.parent_names = &parent_name;
294 	init.num_parents = 1;
295 
296 	axi_clkgen->clk_hw.init = &init;
297 	clk = devm_clk_register(&pdev->dev, &axi_clkgen->clk_hw);
298 	if (IS_ERR(clk))
299 		return PTR_ERR(clk);
300 
301 	return of_clk_add_provider(pdev->dev.of_node, of_clk_src_simple_get,
302 				    clk);
303 }
304 
305 static int axi_clkgen_remove(struct platform_device *pdev)
306 {
307 	of_clk_del_provider(pdev->dev.of_node);
308 
309 	return 0;
310 }
311 
312 static const struct of_device_id axi_clkgen_ids[] = {
313 	{ .compatible = "adi,axi-clkgen-1.00.a" },
314 	{ },
315 };
316 MODULE_DEVICE_TABLE(of, axi_clkgen_ids);
317 
318 static struct platform_driver axi_clkgen_driver = {
319 	.driver = {
320 		.name = "adi-axi-clkgen",
321 		.owner = THIS_MODULE,
322 		.of_match_table = axi_clkgen_ids,
323 	},
324 	.probe = axi_clkgen_probe,
325 	.remove = axi_clkgen_remove,
326 };
327 module_platform_driver(axi_clkgen_driver);
328 
329 MODULE_LICENSE("GPL v2");
330 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
331 MODULE_DESCRIPTION("Driver for the Analog Devices' AXI clkgen pcore clock generator");
332