1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * AXI clkgen driver 4 * 5 * Copyright 2012-2013 Analog Devices Inc. 6 * Author: Lars-Peter Clausen <lars@metafoo.de> 7 */ 8 9 #include <linux/platform_device.h> 10 #include <linux/clk-provider.h> 11 #include <linux/slab.h> 12 #include <linux/io.h> 13 #include <linux/of.h> 14 #include <linux/module.h> 15 #include <linux/err.h> 16 17 #define AXI_CLKGEN_V2_REG_RESET 0x40 18 #define AXI_CLKGEN_V2_REG_CLKSEL 0x44 19 #define AXI_CLKGEN_V2_REG_DRP_CNTRL 0x70 20 #define AXI_CLKGEN_V2_REG_DRP_STATUS 0x74 21 22 #define AXI_CLKGEN_V2_RESET_MMCM_ENABLE BIT(1) 23 #define AXI_CLKGEN_V2_RESET_ENABLE BIT(0) 24 25 #define AXI_CLKGEN_V2_DRP_CNTRL_SEL BIT(29) 26 #define AXI_CLKGEN_V2_DRP_CNTRL_READ BIT(28) 27 28 #define AXI_CLKGEN_V2_DRP_STATUS_BUSY BIT(16) 29 30 #define MMCM_REG_CLKOUT5_2 0x07 31 #define MMCM_REG_CLKOUT0_1 0x08 32 #define MMCM_REG_CLKOUT0_2 0x09 33 #define MMCM_REG_CLKOUT6_2 0x13 34 #define MMCM_REG_CLK_FB1 0x14 35 #define MMCM_REG_CLK_FB2 0x15 36 #define MMCM_REG_CLK_DIV 0x16 37 #define MMCM_REG_LOCK1 0x18 38 #define MMCM_REG_LOCK2 0x19 39 #define MMCM_REG_LOCK3 0x1a 40 #define MMCM_REG_POWER 0x28 41 #define MMCM_REG_FILTER1 0x4e 42 #define MMCM_REG_FILTER2 0x4f 43 44 #define MMCM_CLKOUT_NOCOUNT BIT(6) 45 46 #define MMCM_CLK_DIV_DIVIDE BIT(11) 47 #define MMCM_CLK_DIV_NOCOUNT BIT(12) 48 49 struct axi_clkgen_limits { 50 unsigned int fpfd_min; 51 unsigned int fpfd_max; 52 unsigned int fvco_min; 53 unsigned int fvco_max; 54 }; 55 56 struct axi_clkgen { 57 void __iomem *base; 58 struct clk_hw clk_hw; 59 struct axi_clkgen_limits limits; 60 }; 61 62 static uint32_t axi_clkgen_lookup_filter(unsigned int m) 63 { 64 switch (m) { 65 case 0: 66 return 0x01001990; 67 case 1: 68 return 0x01001190; 69 case 2: 70 return 0x01009890; 71 case 3: 72 return 0x01001890; 73 case 4: 74 return 0x01008890; 75 case 5 ... 8: 76 return 0x01009090; 77 case 9 ... 11: 78 return 0x01000890; 79 case 12: 80 return 0x08009090; 81 case 13 ... 22: 82 return 0x01001090; 83 case 23 ... 36: 84 return 0x01008090; 85 case 37 ... 46: 86 return 0x08001090; 87 default: 88 return 0x08008090; 89 } 90 } 91 92 static const uint32_t axi_clkgen_lock_table[] = { 93 0x060603e8, 0x060603e8, 0x080803e8, 0x0b0b03e8, 94 0x0e0e03e8, 0x111103e8, 0x131303e8, 0x161603e8, 95 0x191903e8, 0x1c1c03e8, 0x1f1f0384, 0x1f1f0339, 96 0x1f1f02ee, 0x1f1f02bc, 0x1f1f028a, 0x1f1f0271, 97 0x1f1f023f, 0x1f1f0226, 0x1f1f020d, 0x1f1f01f4, 98 0x1f1f01db, 0x1f1f01c2, 0x1f1f01a9, 0x1f1f0190, 99 0x1f1f0190, 0x1f1f0177, 0x1f1f015e, 0x1f1f015e, 100 0x1f1f0145, 0x1f1f0145, 0x1f1f012c, 0x1f1f012c, 101 0x1f1f012c, 0x1f1f0113, 0x1f1f0113, 0x1f1f0113, 102 }; 103 104 static uint32_t axi_clkgen_lookup_lock(unsigned int m) 105 { 106 if (m < ARRAY_SIZE(axi_clkgen_lock_table)) 107 return axi_clkgen_lock_table[m]; 108 return 0x1f1f00fa; 109 } 110 111 static const struct axi_clkgen_limits axi_clkgen_zynq_default_limits = { 112 .fpfd_min = 10000, 113 .fpfd_max = 300000, 114 .fvco_min = 600000, 115 .fvco_max = 1200000, 116 }; 117 118 static void axi_clkgen_calc_params(const struct axi_clkgen_limits *limits, 119 unsigned long fin, unsigned long fout, 120 unsigned int *best_d, unsigned int *best_m, unsigned int *best_dout) 121 { 122 unsigned long d, d_min, d_max, _d_min, _d_max; 123 unsigned long m, m_min, m_max; 124 unsigned long f, dout, best_f, fvco; 125 unsigned long fract_shift = 0; 126 unsigned long fvco_min_fract, fvco_max_fract; 127 128 fin /= 1000; 129 fout /= 1000; 130 131 best_f = ULONG_MAX; 132 *best_d = 0; 133 *best_m = 0; 134 *best_dout = 0; 135 136 d_min = max_t(unsigned long, DIV_ROUND_UP(fin, limits->fpfd_max), 1); 137 d_max = min_t(unsigned long, fin / limits->fpfd_min, 80); 138 139 again: 140 fvco_min_fract = limits->fvco_min << fract_shift; 141 fvco_max_fract = limits->fvco_max << fract_shift; 142 143 m_min = max_t(unsigned long, DIV_ROUND_UP(fvco_min_fract, fin) * d_min, 1); 144 m_max = min_t(unsigned long, fvco_max_fract * d_max / fin, 64 << fract_shift); 145 146 for (m = m_min; m <= m_max; m++) { 147 _d_min = max(d_min, DIV_ROUND_UP(fin * m, fvco_max_fract)); 148 _d_max = min(d_max, fin * m / fvco_min_fract); 149 150 for (d = _d_min; d <= _d_max; d++) { 151 fvco = fin * m / d; 152 153 dout = DIV_ROUND_CLOSEST(fvco, fout); 154 dout = clamp_t(unsigned long, dout, 1, 128 << fract_shift); 155 f = fvco / dout; 156 if (abs(f - fout) < abs(best_f - fout)) { 157 best_f = f; 158 *best_d = d; 159 *best_m = m << (3 - fract_shift); 160 *best_dout = dout << (3 - fract_shift); 161 if (best_f == fout) 162 return; 163 } 164 } 165 } 166 167 /* Lets see if we find a better setting in fractional mode */ 168 if (fract_shift == 0) { 169 fract_shift = 3; 170 goto again; 171 } 172 } 173 174 struct axi_clkgen_div_params { 175 unsigned int low; 176 unsigned int high; 177 unsigned int edge; 178 unsigned int nocount; 179 unsigned int frac_en; 180 unsigned int frac; 181 unsigned int frac_wf_f; 182 unsigned int frac_wf_r; 183 unsigned int frac_phase; 184 }; 185 186 static void axi_clkgen_calc_clk_params(unsigned int divider, 187 unsigned int frac_divider, struct axi_clkgen_div_params *params) 188 { 189 190 memset(params, 0x0, sizeof(*params)); 191 192 if (divider == 1) { 193 params->nocount = 1; 194 return; 195 } 196 197 if (frac_divider == 0) { 198 params->high = divider / 2; 199 params->edge = divider % 2; 200 params->low = divider - params->high; 201 } else { 202 params->frac_en = 1; 203 params->frac = frac_divider; 204 205 params->high = divider / 2; 206 params->edge = divider % 2; 207 params->low = params->high; 208 209 if (params->edge == 0) { 210 params->high--; 211 params->frac_wf_r = 1; 212 } 213 214 if (params->edge == 0 || frac_divider == 1) 215 params->low--; 216 if (((params->edge == 0) ^ (frac_divider == 1)) || 217 (divider == 2 && frac_divider == 1)) 218 params->frac_wf_f = 1; 219 220 params->frac_phase = params->edge * 4 + frac_divider / 2; 221 } 222 } 223 224 static void axi_clkgen_write(struct axi_clkgen *axi_clkgen, 225 unsigned int reg, unsigned int val) 226 { 227 writel(val, axi_clkgen->base + reg); 228 } 229 230 static void axi_clkgen_read(struct axi_clkgen *axi_clkgen, 231 unsigned int reg, unsigned int *val) 232 { 233 *val = readl(axi_clkgen->base + reg); 234 } 235 236 static int axi_clkgen_wait_non_busy(struct axi_clkgen *axi_clkgen) 237 { 238 unsigned int timeout = 10000; 239 unsigned int val; 240 241 do { 242 axi_clkgen_read(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_STATUS, &val); 243 } while ((val & AXI_CLKGEN_V2_DRP_STATUS_BUSY) && --timeout); 244 245 if (val & AXI_CLKGEN_V2_DRP_STATUS_BUSY) 246 return -EIO; 247 248 return val & 0xffff; 249 } 250 251 static int axi_clkgen_mmcm_read(struct axi_clkgen *axi_clkgen, 252 unsigned int reg, unsigned int *val) 253 { 254 unsigned int reg_val; 255 int ret; 256 257 ret = axi_clkgen_wait_non_busy(axi_clkgen); 258 if (ret < 0) 259 return ret; 260 261 reg_val = AXI_CLKGEN_V2_DRP_CNTRL_SEL | AXI_CLKGEN_V2_DRP_CNTRL_READ; 262 reg_val |= (reg << 16); 263 264 axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val); 265 266 ret = axi_clkgen_wait_non_busy(axi_clkgen); 267 if (ret < 0) 268 return ret; 269 270 *val = ret; 271 272 return 0; 273 } 274 275 static int axi_clkgen_mmcm_write(struct axi_clkgen *axi_clkgen, 276 unsigned int reg, unsigned int val, unsigned int mask) 277 { 278 unsigned int reg_val = 0; 279 int ret; 280 281 ret = axi_clkgen_wait_non_busy(axi_clkgen); 282 if (ret < 0) 283 return ret; 284 285 if (mask != 0xffff) { 286 axi_clkgen_mmcm_read(axi_clkgen, reg, ®_val); 287 reg_val &= ~mask; 288 } 289 290 reg_val |= AXI_CLKGEN_V2_DRP_CNTRL_SEL | (reg << 16) | (val & mask); 291 292 axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val); 293 294 return 0; 295 } 296 297 static void axi_clkgen_mmcm_enable(struct axi_clkgen *axi_clkgen, 298 bool enable) 299 { 300 unsigned int val = AXI_CLKGEN_V2_RESET_ENABLE; 301 302 if (enable) 303 val |= AXI_CLKGEN_V2_RESET_MMCM_ENABLE; 304 305 axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_RESET, val); 306 } 307 308 static struct axi_clkgen *clk_hw_to_axi_clkgen(struct clk_hw *clk_hw) 309 { 310 return container_of(clk_hw, struct axi_clkgen, clk_hw); 311 } 312 313 static void axi_clkgen_set_div(struct axi_clkgen *axi_clkgen, 314 unsigned int reg1, unsigned int reg2, unsigned int reg3, 315 struct axi_clkgen_div_params *params) 316 { 317 axi_clkgen_mmcm_write(axi_clkgen, reg1, 318 (params->high << 6) | params->low, 0xefff); 319 axi_clkgen_mmcm_write(axi_clkgen, reg2, 320 (params->frac << 12) | (params->frac_en << 11) | 321 (params->frac_wf_r << 10) | (params->edge << 7) | 322 (params->nocount << 6), 0x7fff); 323 if (reg3 != 0) { 324 axi_clkgen_mmcm_write(axi_clkgen, reg3, 325 (params->frac_phase << 11) | (params->frac_wf_f << 10), 0x3c00); 326 } 327 } 328 329 static int axi_clkgen_set_rate(struct clk_hw *clk_hw, 330 unsigned long rate, unsigned long parent_rate) 331 { 332 struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw); 333 const struct axi_clkgen_limits *limits = &axi_clkgen->limits; 334 unsigned int d, m, dout; 335 struct axi_clkgen_div_params params; 336 uint32_t power = 0; 337 uint32_t filter; 338 uint32_t lock; 339 340 if (parent_rate == 0 || rate == 0) 341 return -EINVAL; 342 343 axi_clkgen_calc_params(limits, parent_rate, rate, &d, &m, &dout); 344 345 if (d == 0 || dout == 0 || m == 0) 346 return -EINVAL; 347 348 if ((dout & 0x7) != 0 || (m & 0x7) != 0) 349 power |= 0x9800; 350 351 axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_POWER, power, 0x9800); 352 353 filter = axi_clkgen_lookup_filter(m - 1); 354 lock = axi_clkgen_lookup_lock(m - 1); 355 356 axi_clkgen_calc_clk_params(dout >> 3, dout & 0x7, ¶ms); 357 axi_clkgen_set_div(axi_clkgen, MMCM_REG_CLKOUT0_1, MMCM_REG_CLKOUT0_2, 358 MMCM_REG_CLKOUT5_2, ¶ms); 359 360 axi_clkgen_calc_clk_params(d, 0, ¶ms); 361 axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLK_DIV, 362 (params.edge << 13) | (params.nocount << 12) | 363 (params.high << 6) | params.low, 0x3fff); 364 365 axi_clkgen_calc_clk_params(m >> 3, m & 0x7, ¶ms); 366 axi_clkgen_set_div(axi_clkgen, MMCM_REG_CLK_FB1, MMCM_REG_CLK_FB2, 367 MMCM_REG_CLKOUT6_2, ¶ms); 368 369 axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK1, lock & 0x3ff, 0x3ff); 370 axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK2, 371 (((lock >> 16) & 0x1f) << 10) | 0x1, 0x7fff); 372 axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK3, 373 (((lock >> 24) & 0x1f) << 10) | 0x3e9, 0x7fff); 374 axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER1, filter >> 16, 0x9900); 375 axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER2, filter, 0x9900); 376 377 return 0; 378 } 379 380 static long axi_clkgen_round_rate(struct clk_hw *hw, unsigned long rate, 381 unsigned long *parent_rate) 382 { 383 struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(hw); 384 const struct axi_clkgen_limits *limits = &axi_clkgen->limits; 385 unsigned int d, m, dout; 386 unsigned long long tmp; 387 388 axi_clkgen_calc_params(limits, *parent_rate, rate, &d, &m, &dout); 389 390 if (d == 0 || dout == 0 || m == 0) 391 return -EINVAL; 392 393 tmp = (unsigned long long)*parent_rate * m; 394 tmp = DIV_ROUND_CLOSEST_ULL(tmp, dout * d); 395 396 return min_t(unsigned long long, tmp, LONG_MAX); 397 } 398 399 static unsigned int axi_clkgen_get_div(struct axi_clkgen *axi_clkgen, 400 unsigned int reg1, unsigned int reg2) 401 { 402 unsigned int val1, val2; 403 unsigned int div; 404 405 axi_clkgen_mmcm_read(axi_clkgen, reg2, &val2); 406 if (val2 & MMCM_CLKOUT_NOCOUNT) 407 return 8; 408 409 axi_clkgen_mmcm_read(axi_clkgen, reg1, &val1); 410 411 div = (val1 & 0x3f) + ((val1 >> 6) & 0x3f); 412 div <<= 3; 413 414 if (val2 & MMCM_CLK_DIV_DIVIDE) { 415 if ((val2 & BIT(7)) && (val2 & 0x7000) != 0x1000) 416 div += 8; 417 else 418 div += 16; 419 420 div += (val2 >> 12) & 0x7; 421 } 422 423 return div; 424 } 425 426 static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw, 427 unsigned long parent_rate) 428 { 429 struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw); 430 unsigned int d, m, dout; 431 unsigned long long tmp; 432 unsigned int val; 433 434 dout = axi_clkgen_get_div(axi_clkgen, MMCM_REG_CLKOUT0_1, 435 MMCM_REG_CLKOUT0_2); 436 m = axi_clkgen_get_div(axi_clkgen, MMCM_REG_CLK_FB1, 437 MMCM_REG_CLK_FB2); 438 439 axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_DIV, &val); 440 if (val & MMCM_CLK_DIV_NOCOUNT) 441 d = 1; 442 else 443 d = (val & 0x3f) + ((val >> 6) & 0x3f); 444 445 if (d == 0 || dout == 0) 446 return 0; 447 448 tmp = (unsigned long long)parent_rate * m; 449 tmp = DIV_ROUND_CLOSEST_ULL(tmp, dout * d); 450 451 return min_t(unsigned long long, tmp, ULONG_MAX); 452 } 453 454 static int axi_clkgen_enable(struct clk_hw *clk_hw) 455 { 456 struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw); 457 458 axi_clkgen_mmcm_enable(axi_clkgen, true); 459 460 return 0; 461 } 462 463 static void axi_clkgen_disable(struct clk_hw *clk_hw) 464 { 465 struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw); 466 467 axi_clkgen_mmcm_enable(axi_clkgen, false); 468 } 469 470 static int axi_clkgen_set_parent(struct clk_hw *clk_hw, u8 index) 471 { 472 struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw); 473 474 axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_CLKSEL, index); 475 476 return 0; 477 } 478 479 static u8 axi_clkgen_get_parent(struct clk_hw *clk_hw) 480 { 481 struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw); 482 unsigned int parent; 483 484 axi_clkgen_read(axi_clkgen, AXI_CLKGEN_V2_REG_CLKSEL, &parent); 485 486 return parent; 487 } 488 489 static const struct clk_ops axi_clkgen_ops = { 490 .recalc_rate = axi_clkgen_recalc_rate, 491 .round_rate = axi_clkgen_round_rate, 492 .set_rate = axi_clkgen_set_rate, 493 .enable = axi_clkgen_enable, 494 .disable = axi_clkgen_disable, 495 .set_parent = axi_clkgen_set_parent, 496 .get_parent = axi_clkgen_get_parent, 497 }; 498 499 static int axi_clkgen_probe(struct platform_device *pdev) 500 { 501 const struct axi_clkgen_limits *dflt_limits; 502 struct axi_clkgen *axi_clkgen; 503 struct clk_init_data init; 504 const char *parent_names[2]; 505 const char *clk_name; 506 struct resource *mem; 507 unsigned int i; 508 int ret; 509 510 dflt_limits = device_get_match_data(&pdev->dev); 511 if (!dflt_limits) 512 return -ENODEV; 513 514 axi_clkgen = devm_kzalloc(&pdev->dev, sizeof(*axi_clkgen), GFP_KERNEL); 515 if (!axi_clkgen) 516 return -ENOMEM; 517 518 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 519 axi_clkgen->base = devm_ioremap_resource(&pdev->dev, mem); 520 if (IS_ERR(axi_clkgen->base)) 521 return PTR_ERR(axi_clkgen->base); 522 523 init.num_parents = of_clk_get_parent_count(pdev->dev.of_node); 524 if (init.num_parents < 1 || init.num_parents > 2) 525 return -EINVAL; 526 527 for (i = 0; i < init.num_parents; i++) { 528 parent_names[i] = of_clk_get_parent_name(pdev->dev.of_node, i); 529 if (!parent_names[i]) 530 return -EINVAL; 531 } 532 533 memcpy(&axi_clkgen->limits, dflt_limits, sizeof(axi_clkgen->limits)); 534 535 clk_name = pdev->dev.of_node->name; 536 of_property_read_string(pdev->dev.of_node, "clock-output-names", 537 &clk_name); 538 539 init.name = clk_name; 540 init.ops = &axi_clkgen_ops; 541 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; 542 init.parent_names = parent_names; 543 544 axi_clkgen_mmcm_enable(axi_clkgen, false); 545 546 axi_clkgen->clk_hw.init = &init; 547 ret = devm_clk_hw_register(&pdev->dev, &axi_clkgen->clk_hw); 548 if (ret) 549 return ret; 550 551 return of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_simple_get, 552 &axi_clkgen->clk_hw); 553 } 554 555 static int axi_clkgen_remove(struct platform_device *pdev) 556 { 557 of_clk_del_provider(pdev->dev.of_node); 558 559 return 0; 560 } 561 562 static const struct of_device_id axi_clkgen_ids[] = { 563 { 564 .compatible = "adi,axi-clkgen-2.00.a", 565 .data = &axi_clkgen_zynq_default_limits, 566 }, 567 { } 568 }; 569 MODULE_DEVICE_TABLE(of, axi_clkgen_ids); 570 571 static struct platform_driver axi_clkgen_driver = { 572 .driver = { 573 .name = "adi-axi-clkgen", 574 .of_match_table = axi_clkgen_ids, 575 }, 576 .probe = axi_clkgen_probe, 577 .remove = axi_clkgen_remove, 578 }; 579 module_platform_driver(axi_clkgen_driver); 580 581 MODULE_LICENSE("GPL v2"); 582 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); 583 MODULE_DESCRIPTION("Driver for the Analog Devices' AXI clkgen pcore clock generator"); 584