1 // SPDX-License-Identifier: GPL-2.0+ 2 3 #define pr_fmt(fmt) "clk-aspeed: " fmt 4 5 #include <linux/clk-provider.h> 6 #include <linux/mfd/syscon.h> 7 #include <linux/of_address.h> 8 #include <linux/of_device.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 #include <linux/reset-controller.h> 12 #include <linux/slab.h> 13 #include <linux/spinlock.h> 14 15 #include <dt-bindings/clock/aspeed-clock.h> 16 17 #define ASPEED_NUM_CLKS 36 18 19 #define ASPEED_RESET2_OFFSET 32 20 21 #define ASPEED_RESET_CTRL 0x04 22 #define ASPEED_CLK_SELECTION 0x08 23 #define ASPEED_CLK_STOP_CTRL 0x0c 24 #define ASPEED_MPLL_PARAM 0x20 25 #define ASPEED_HPLL_PARAM 0x24 26 #define AST2500_HPLL_BYPASS_EN BIT(20) 27 #define AST2400_HPLL_PROGRAMMED BIT(18) 28 #define AST2400_HPLL_BYPASS_EN BIT(17) 29 #define ASPEED_MISC_CTRL 0x2c 30 #define UART_DIV13_EN BIT(12) 31 #define ASPEED_STRAP 0x70 32 #define CLKIN_25MHZ_EN BIT(23) 33 #define AST2400_CLK_SOURCE_SEL BIT(18) 34 #define ASPEED_CLK_SELECTION_2 0xd8 35 #define ASPEED_RESET_CTRL2 0xd4 36 37 /* Globally visible clocks */ 38 static DEFINE_SPINLOCK(aspeed_clk_lock); 39 40 /* Keeps track of all clocks */ 41 static struct clk_hw_onecell_data *aspeed_clk_data; 42 43 static void __iomem *scu_base; 44 45 /** 46 * struct aspeed_gate_data - Aspeed gated clocks 47 * @clock_idx: bit used to gate this clock in the clock register 48 * @reset_idx: bit used to reset this IP in the reset register. -1 if no 49 * reset is required when enabling the clock 50 * @name: the clock name 51 * @parent_name: the name of the parent clock 52 * @flags: standard clock framework flags 53 */ 54 struct aspeed_gate_data { 55 u8 clock_idx; 56 s8 reset_idx; 57 const char *name; 58 const char *parent_name; 59 unsigned long flags; 60 }; 61 62 /** 63 * struct aspeed_clk_gate - Aspeed specific clk_gate structure 64 * @hw: handle between common and hardware-specific interfaces 65 * @reg: register controlling gate 66 * @clock_idx: bit used to gate this clock in the clock register 67 * @reset_idx: bit used to reset this IP in the reset register. -1 if no 68 * reset is required when enabling the clock 69 * @flags: hardware-specific flags 70 * @lock: register lock 71 * 72 * Some of the clocks in the Aspeed SoC must be put in reset before enabling. 73 * This modified version of clk_gate allows an optional reset bit to be 74 * specified. 75 */ 76 struct aspeed_clk_gate { 77 struct clk_hw hw; 78 struct regmap *map; 79 u8 clock_idx; 80 s8 reset_idx; 81 u8 flags; 82 spinlock_t *lock; 83 }; 84 85 #define to_aspeed_clk_gate(_hw) container_of(_hw, struct aspeed_clk_gate, hw) 86 87 /* TODO: ask Aspeed about the actual parent data */ 88 static const struct aspeed_gate_data aspeed_gates[] = { 89 /* clk rst name parent flags */ 90 [ASPEED_CLK_GATE_ECLK] = { 0, -1, "eclk-gate", "eclk", 0 }, /* Video Engine */ 91 [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */ 92 [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */ 93 [ASPEED_CLK_GATE_VCLK] = { 3, 6, "vclk-gate", NULL, 0 }, /* Video Capture */ 94 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */ 95 [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */ 96 [ASPEED_CLK_GATE_REFCLK] = { 6, -1, "refclk-gate", "clkin", CLK_IS_CRITICAL }, 97 [ASPEED_CLK_GATE_USBPORT2CLK] = { 7, 3, "usb-port2-gate", NULL, 0 }, /* USB2.0 Host port 2 */ 98 [ASPEED_CLK_GATE_LCLK] = { 8, 5, "lclk-gate", NULL, 0 }, /* LPC */ 99 [ASPEED_CLK_GATE_USBUHCICLK] = { 9, 15, "usb-uhci-gate", NULL, 0 }, /* USB1.1 (requires port 2 enabled) */ 100 [ASPEED_CLK_GATE_D1CLK] = { 10, 13, "d1clk-gate", NULL, 0 }, /* GFX CRT */ 101 [ASPEED_CLK_GATE_YCLK] = { 13, 4, "yclk-gate", NULL, 0 }, /* HAC */ 102 [ASPEED_CLK_GATE_USBPORT1CLK] = { 14, 14, "usb-port1-gate", NULL, 0 }, /* USB2 hub/USB2 host port 1/USB1.1 dev */ 103 [ASPEED_CLK_GATE_UART1CLK] = { 15, -1, "uart1clk-gate", "uart", 0 }, /* UART1 */ 104 [ASPEED_CLK_GATE_UART2CLK] = { 16, -1, "uart2clk-gate", "uart", 0 }, /* UART2 */ 105 [ASPEED_CLK_GATE_UART5CLK] = { 17, -1, "uart5clk-gate", "uart", 0 }, /* UART5 */ 106 [ASPEED_CLK_GATE_ESPICLK] = { 19, -1, "espiclk-gate", NULL, 0 }, /* eSPI */ 107 [ASPEED_CLK_GATE_MAC1CLK] = { 20, 11, "mac1clk-gate", "mac", 0 }, /* MAC1 */ 108 [ASPEED_CLK_GATE_MAC2CLK] = { 21, 12, "mac2clk-gate", "mac", 0 }, /* MAC2 */ 109 [ASPEED_CLK_GATE_RSACLK] = { 24, -1, "rsaclk-gate", NULL, 0 }, /* RSA */ 110 [ASPEED_CLK_GATE_UART3CLK] = { 25, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */ 111 [ASPEED_CLK_GATE_UART4CLK] = { 26, -1, "uart4clk-gate", "uart", 0 }, /* UART4 */ 112 [ASPEED_CLK_GATE_SDCLK] = { 27, 16, "sdclk-gate", NULL, 0 }, /* SDIO/SD */ 113 [ASPEED_CLK_GATE_LHCCLK] = { 28, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */ 114 }; 115 116 static const struct clk_div_table ast2500_mac_div_table[] = { 117 { 0x0, 4 }, /* Yep, really. Aspeed confirmed this is correct */ 118 { 0x1, 4 }, 119 { 0x2, 6 }, 120 { 0x3, 8 }, 121 { 0x4, 10 }, 122 { 0x5, 12 }, 123 { 0x6, 14 }, 124 { 0x7, 16 }, 125 { 0 } 126 }; 127 128 static const struct clk_div_table ast2400_div_table[] = { 129 { 0x0, 2 }, 130 { 0x1, 4 }, 131 { 0x2, 6 }, 132 { 0x3, 8 }, 133 { 0x4, 10 }, 134 { 0x5, 12 }, 135 { 0x6, 14 }, 136 { 0x7, 16 }, 137 { 0 } 138 }; 139 140 static const struct clk_div_table ast2500_div_table[] = { 141 { 0x0, 4 }, 142 { 0x1, 8 }, 143 { 0x2, 12 }, 144 { 0x3, 16 }, 145 { 0x4, 20 }, 146 { 0x5, 24 }, 147 { 0x6, 28 }, 148 { 0x7, 32 }, 149 { 0 } 150 }; 151 152 static struct clk_hw *aspeed_ast2400_calc_pll(const char *name, u32 val) 153 { 154 unsigned int mult, div; 155 156 if (val & AST2400_HPLL_BYPASS_EN) { 157 /* Pass through mode */ 158 mult = div = 1; 159 } else { 160 /* F = 24Mhz * (2-OD) * [(N + 2) / (D + 1)] */ 161 u32 n = (val >> 5) & 0x3f; 162 u32 od = (val >> 4) & 0x1; 163 u32 d = val & 0xf; 164 165 mult = (2 - od) * (n + 2); 166 div = d + 1; 167 } 168 return clk_hw_register_fixed_factor(NULL, name, "clkin", 0, 169 mult, div); 170 }; 171 172 static struct clk_hw *aspeed_ast2500_calc_pll(const char *name, u32 val) 173 { 174 unsigned int mult, div; 175 176 if (val & AST2500_HPLL_BYPASS_EN) { 177 /* Pass through mode */ 178 mult = div = 1; 179 } else { 180 /* F = clkin * [(M+1) / (N+1)] / (P + 1) */ 181 u32 p = (val >> 13) & 0x3f; 182 u32 m = (val >> 5) & 0xff; 183 u32 n = val & 0x1f; 184 185 mult = (m + 1) / (n + 1); 186 div = p + 1; 187 } 188 189 return clk_hw_register_fixed_factor(NULL, name, "clkin", 0, 190 mult, div); 191 } 192 193 struct aspeed_clk_soc_data { 194 const struct clk_div_table *div_table; 195 const struct clk_div_table *mac_div_table; 196 struct clk_hw *(*calc_pll)(const char *name, u32 val); 197 }; 198 199 static const struct aspeed_clk_soc_data ast2500_data = { 200 .div_table = ast2500_div_table, 201 .mac_div_table = ast2500_mac_div_table, 202 .calc_pll = aspeed_ast2500_calc_pll, 203 }; 204 205 static const struct aspeed_clk_soc_data ast2400_data = { 206 .div_table = ast2400_div_table, 207 .mac_div_table = ast2400_div_table, 208 .calc_pll = aspeed_ast2400_calc_pll, 209 }; 210 211 static int aspeed_clk_is_enabled(struct clk_hw *hw) 212 { 213 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); 214 u32 clk = BIT(gate->clock_idx); 215 u32 rst = BIT(gate->reset_idx); 216 u32 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk; 217 u32 reg; 218 219 /* 220 * If the IP is in reset, treat the clock as not enabled, 221 * this happens with some clocks such as the USB one when 222 * coming from cold reset. Without this, aspeed_clk_enable() 223 * will fail to lift the reset. 224 */ 225 if (gate->reset_idx >= 0) { 226 regmap_read(gate->map, ASPEED_RESET_CTRL, ®); 227 if (reg & rst) 228 return 0; 229 } 230 231 regmap_read(gate->map, ASPEED_CLK_STOP_CTRL, ®); 232 233 return ((reg & clk) == enval) ? 1 : 0; 234 } 235 236 static int aspeed_clk_enable(struct clk_hw *hw) 237 { 238 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); 239 unsigned long flags; 240 u32 clk = BIT(gate->clock_idx); 241 u32 rst = BIT(gate->reset_idx); 242 u32 enval; 243 244 spin_lock_irqsave(gate->lock, flags); 245 246 if (aspeed_clk_is_enabled(hw)) { 247 spin_unlock_irqrestore(gate->lock, flags); 248 return 0; 249 } 250 251 if (gate->reset_idx >= 0) { 252 /* Put IP in reset */ 253 regmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, rst); 254 255 /* Delay 100us */ 256 udelay(100); 257 } 258 259 /* Enable clock */ 260 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk; 261 regmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, enval); 262 263 if (gate->reset_idx >= 0) { 264 /* A delay of 10ms is specified by the ASPEED docs */ 265 mdelay(10); 266 267 /* Take IP out of reset */ 268 regmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, 0); 269 } 270 271 spin_unlock_irqrestore(gate->lock, flags); 272 273 return 0; 274 } 275 276 static void aspeed_clk_disable(struct clk_hw *hw) 277 { 278 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); 279 unsigned long flags; 280 u32 clk = BIT(gate->clock_idx); 281 u32 enval; 282 283 spin_lock_irqsave(gate->lock, flags); 284 285 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? clk : 0; 286 regmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, enval); 287 288 spin_unlock_irqrestore(gate->lock, flags); 289 } 290 291 static const struct clk_ops aspeed_clk_gate_ops = { 292 .enable = aspeed_clk_enable, 293 .disable = aspeed_clk_disable, 294 .is_enabled = aspeed_clk_is_enabled, 295 }; 296 297 /** 298 * struct aspeed_reset - Aspeed reset controller 299 * @map: regmap to access the containing system controller 300 * @rcdev: reset controller device 301 */ 302 struct aspeed_reset { 303 struct regmap *map; 304 struct reset_controller_dev rcdev; 305 }; 306 307 #define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev) 308 309 static const u8 aspeed_resets[] = { 310 /* SCU04 resets */ 311 [ASPEED_RESET_XDMA] = 25, 312 [ASPEED_RESET_MCTP] = 24, 313 [ASPEED_RESET_ADC] = 23, 314 [ASPEED_RESET_JTAG_MASTER] = 22, 315 [ASPEED_RESET_MIC] = 18, 316 [ASPEED_RESET_PWM] = 9, 317 [ASPEED_RESET_PECI] = 10, 318 [ASPEED_RESET_I2C] = 2, 319 [ASPEED_RESET_AHB] = 1, 320 321 /* 322 * SCUD4 resets start at an offset to separate them from 323 * the SCU04 resets. 324 */ 325 [ASPEED_RESET_CRT1] = ASPEED_RESET2_OFFSET + 5, 326 }; 327 328 static int aspeed_reset_deassert(struct reset_controller_dev *rcdev, 329 unsigned long id) 330 { 331 struct aspeed_reset *ar = to_aspeed_reset(rcdev); 332 u32 reg = ASPEED_RESET_CTRL; 333 u32 bit = aspeed_resets[id]; 334 335 if (bit >= ASPEED_RESET2_OFFSET) { 336 bit -= ASPEED_RESET2_OFFSET; 337 reg = ASPEED_RESET_CTRL2; 338 } 339 340 return regmap_update_bits(ar->map, reg, BIT(bit), 0); 341 } 342 343 static int aspeed_reset_assert(struct reset_controller_dev *rcdev, 344 unsigned long id) 345 { 346 struct aspeed_reset *ar = to_aspeed_reset(rcdev); 347 u32 reg = ASPEED_RESET_CTRL; 348 u32 bit = aspeed_resets[id]; 349 350 if (bit >= ASPEED_RESET2_OFFSET) { 351 bit -= ASPEED_RESET2_OFFSET; 352 reg = ASPEED_RESET_CTRL2; 353 } 354 355 return regmap_update_bits(ar->map, reg, BIT(bit), BIT(bit)); 356 } 357 358 static int aspeed_reset_status(struct reset_controller_dev *rcdev, 359 unsigned long id) 360 { 361 struct aspeed_reset *ar = to_aspeed_reset(rcdev); 362 u32 reg = ASPEED_RESET_CTRL; 363 u32 bit = aspeed_resets[id]; 364 int ret, val; 365 366 if (bit >= ASPEED_RESET2_OFFSET) { 367 bit -= ASPEED_RESET2_OFFSET; 368 reg = ASPEED_RESET_CTRL2; 369 } 370 371 ret = regmap_read(ar->map, reg, &val); 372 if (ret) 373 return ret; 374 375 return !!(val & BIT(bit)); 376 } 377 378 static const struct reset_control_ops aspeed_reset_ops = { 379 .assert = aspeed_reset_assert, 380 .deassert = aspeed_reset_deassert, 381 .status = aspeed_reset_status, 382 }; 383 384 static struct clk_hw *aspeed_clk_hw_register_gate(struct device *dev, 385 const char *name, const char *parent_name, unsigned long flags, 386 struct regmap *map, u8 clock_idx, u8 reset_idx, 387 u8 clk_gate_flags, spinlock_t *lock) 388 { 389 struct aspeed_clk_gate *gate; 390 struct clk_init_data init; 391 struct clk_hw *hw; 392 int ret; 393 394 gate = kzalloc(sizeof(*gate), GFP_KERNEL); 395 if (!gate) 396 return ERR_PTR(-ENOMEM); 397 398 init.name = name; 399 init.ops = &aspeed_clk_gate_ops; 400 init.flags = flags; 401 init.parent_names = parent_name ? &parent_name : NULL; 402 init.num_parents = parent_name ? 1 : 0; 403 404 gate->map = map; 405 gate->clock_idx = clock_idx; 406 gate->reset_idx = reset_idx; 407 gate->flags = clk_gate_flags; 408 gate->lock = lock; 409 gate->hw.init = &init; 410 411 hw = &gate->hw; 412 ret = clk_hw_register(dev, hw); 413 if (ret) { 414 kfree(gate); 415 hw = ERR_PTR(ret); 416 } 417 418 return hw; 419 } 420 421 static int aspeed_clk_probe(struct platform_device *pdev) 422 { 423 const struct aspeed_clk_soc_data *soc_data; 424 struct device *dev = &pdev->dev; 425 struct aspeed_reset *ar; 426 struct regmap *map; 427 struct clk_hw *hw; 428 u32 val, rate; 429 int i, ret; 430 431 map = syscon_node_to_regmap(dev->of_node); 432 if (IS_ERR(map)) { 433 dev_err(dev, "no syscon regmap\n"); 434 return PTR_ERR(map); 435 } 436 437 ar = devm_kzalloc(dev, sizeof(*ar), GFP_KERNEL); 438 if (!ar) 439 return -ENOMEM; 440 441 ar->map = map; 442 ar->rcdev.owner = THIS_MODULE; 443 ar->rcdev.nr_resets = ARRAY_SIZE(aspeed_resets); 444 ar->rcdev.ops = &aspeed_reset_ops; 445 ar->rcdev.of_node = dev->of_node; 446 447 ret = devm_reset_controller_register(dev, &ar->rcdev); 448 if (ret) { 449 dev_err(dev, "could not register reset controller\n"); 450 return ret; 451 } 452 453 /* SoC generations share common layouts but have different divisors */ 454 soc_data = of_device_get_match_data(dev); 455 if (!soc_data) { 456 dev_err(dev, "no match data for platform\n"); 457 return -EINVAL; 458 } 459 460 /* UART clock div13 setting */ 461 regmap_read(map, ASPEED_MISC_CTRL, &val); 462 if (val & UART_DIV13_EN) 463 rate = 24000000 / 13; 464 else 465 rate = 24000000; 466 /* TODO: Find the parent data for the uart clock */ 467 hw = clk_hw_register_fixed_rate(dev, "uart", NULL, 0, rate); 468 if (IS_ERR(hw)) 469 return PTR_ERR(hw); 470 aspeed_clk_data->hws[ASPEED_CLK_UART] = hw; 471 472 /* 473 * Memory controller (M-PLL) PLL. This clock is configured by the 474 * bootloader, and is exposed to Linux as a read-only clock rate. 475 */ 476 regmap_read(map, ASPEED_MPLL_PARAM, &val); 477 hw = soc_data->calc_pll("mpll", val); 478 if (IS_ERR(hw)) 479 return PTR_ERR(hw); 480 aspeed_clk_data->hws[ASPEED_CLK_MPLL] = hw; 481 482 /* SD/SDIO clock divider (TODO: There's a gate too) */ 483 hw = clk_hw_register_divider_table(dev, "sdio", "hpll", 0, 484 scu_base + ASPEED_CLK_SELECTION, 12, 3, 0, 485 soc_data->div_table, 486 &aspeed_clk_lock); 487 if (IS_ERR(hw)) 488 return PTR_ERR(hw); 489 aspeed_clk_data->hws[ASPEED_CLK_SDIO] = hw; 490 491 /* MAC AHB bus clock divider */ 492 hw = clk_hw_register_divider_table(dev, "mac", "hpll", 0, 493 scu_base + ASPEED_CLK_SELECTION, 16, 3, 0, 494 soc_data->mac_div_table, 495 &aspeed_clk_lock); 496 if (IS_ERR(hw)) 497 return PTR_ERR(hw); 498 aspeed_clk_data->hws[ASPEED_CLK_MAC] = hw; 499 500 /* LPC Host (LHCLK) clock divider */ 501 hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0, 502 scu_base + ASPEED_CLK_SELECTION, 20, 3, 0, 503 soc_data->div_table, 504 &aspeed_clk_lock); 505 if (IS_ERR(hw)) 506 return PTR_ERR(hw); 507 aspeed_clk_data->hws[ASPEED_CLK_LHCLK] = hw; 508 509 /* P-Bus (BCLK) clock divider */ 510 hw = clk_hw_register_divider_table(dev, "bclk", "hpll", 0, 511 scu_base + ASPEED_CLK_SELECTION_2, 0, 2, 0, 512 soc_data->div_table, 513 &aspeed_clk_lock); 514 if (IS_ERR(hw)) 515 return PTR_ERR(hw); 516 aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw; 517 518 /* Fixed 24MHz clock */ 519 hw = clk_hw_register_fixed_rate(NULL, "fixed-24m", "clkin", 520 0, 24000000); 521 if (IS_ERR(hw)) 522 return PTR_ERR(hw); 523 aspeed_clk_data->hws[ASPEED_CLK_24M] = hw; 524 525 /* 526 * TODO: There are a number of clocks that not included in this driver 527 * as more information is required: 528 * D2-PLL 529 * D-PLL 530 * YCLK 531 * RGMII 532 * RMII 533 * UART[1..5] clock source mux 534 * Video Engine (ECLK) mux and clock divider 535 */ 536 537 for (i = 0; i < ARRAY_SIZE(aspeed_gates); i++) { 538 const struct aspeed_gate_data *gd = &aspeed_gates[i]; 539 u32 gate_flags; 540 541 /* Special case: the USB port 1 clock (bit 14) is always 542 * working the opposite way from the other ones. 543 */ 544 gate_flags = (gd->clock_idx == 14) ? 0 : CLK_GATE_SET_TO_DISABLE; 545 hw = aspeed_clk_hw_register_gate(dev, 546 gd->name, 547 gd->parent_name, 548 gd->flags, 549 map, 550 gd->clock_idx, 551 gd->reset_idx, 552 gate_flags, 553 &aspeed_clk_lock); 554 if (IS_ERR(hw)) 555 return PTR_ERR(hw); 556 aspeed_clk_data->hws[i] = hw; 557 } 558 559 return 0; 560 }; 561 562 static const struct of_device_id aspeed_clk_dt_ids[] = { 563 { .compatible = "aspeed,ast2400-scu", .data = &ast2400_data }, 564 { .compatible = "aspeed,ast2500-scu", .data = &ast2500_data }, 565 { } 566 }; 567 568 static struct platform_driver aspeed_clk_driver = { 569 .probe = aspeed_clk_probe, 570 .driver = { 571 .name = "aspeed-clk", 572 .of_match_table = aspeed_clk_dt_ids, 573 .suppress_bind_attrs = true, 574 }, 575 }; 576 builtin_platform_driver(aspeed_clk_driver); 577 578 static void __init aspeed_ast2400_cc(struct regmap *map) 579 { 580 struct clk_hw *hw; 581 u32 val, div, clkin, hpll; 582 const u16 hpll_rates[][4] = { 583 {384, 360, 336, 408}, 584 {400, 375, 350, 425}, 585 }; 586 int rate; 587 588 /* 589 * CLKIN is the crystal oscillator, 24, 48 or 25MHz selected by 590 * strapping 591 */ 592 regmap_read(map, ASPEED_STRAP, &val); 593 rate = (val >> 8) & 3; 594 if (val & CLKIN_25MHZ_EN) { 595 clkin = 25000000; 596 hpll = hpll_rates[1][rate]; 597 } else if (val & AST2400_CLK_SOURCE_SEL) { 598 clkin = 48000000; 599 hpll = hpll_rates[0][rate]; 600 } else { 601 clkin = 24000000; 602 hpll = hpll_rates[0][rate]; 603 } 604 hw = clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, clkin); 605 pr_debug("clkin @%u MHz\n", clkin / 1000000); 606 607 /* 608 * High-speed PLL clock derived from the crystal. This the CPU clock, 609 * and we assume that it is enabled. It can be configured through the 610 * HPLL_PARAM register, or set to a specified frequency by strapping. 611 */ 612 regmap_read(map, ASPEED_HPLL_PARAM, &val); 613 if (val & AST2400_HPLL_PROGRAMMED) 614 hw = aspeed_ast2400_calc_pll("hpll", val); 615 else 616 hw = clk_hw_register_fixed_rate(NULL, "hpll", "clkin", 0, 617 hpll * 1000000); 618 619 aspeed_clk_data->hws[ASPEED_CLK_HPLL] = hw; 620 621 /* 622 * Strap bits 11:10 define the CPU/AHB clock frequency ratio (aka HCLK) 623 * 00: Select CPU:AHB = 1:1 624 * 01: Select CPU:AHB = 2:1 625 * 10: Select CPU:AHB = 4:1 626 * 11: Select CPU:AHB = 3:1 627 */ 628 regmap_read(map, ASPEED_STRAP, &val); 629 val = (val >> 10) & 0x3; 630 div = val + 1; 631 if (div == 3) 632 div = 4; 633 else if (div == 4) 634 div = 3; 635 hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, div); 636 aspeed_clk_data->hws[ASPEED_CLK_AHB] = hw; 637 638 /* APB clock clock selection register SCU08 (aka PCLK) */ 639 hw = clk_hw_register_divider_table(NULL, "apb", "hpll", 0, 640 scu_base + ASPEED_CLK_SELECTION, 23, 3, 0, 641 ast2400_div_table, 642 &aspeed_clk_lock); 643 aspeed_clk_data->hws[ASPEED_CLK_APB] = hw; 644 } 645 646 static void __init aspeed_ast2500_cc(struct regmap *map) 647 { 648 struct clk_hw *hw; 649 u32 val, freq, div; 650 651 /* CLKIN is the crystal oscillator, 24 or 25MHz selected by strapping */ 652 regmap_read(map, ASPEED_STRAP, &val); 653 if (val & CLKIN_25MHZ_EN) 654 freq = 25000000; 655 else 656 freq = 24000000; 657 hw = clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, freq); 658 pr_debug("clkin @%u MHz\n", freq / 1000000); 659 660 /* 661 * High-speed PLL clock derived from the crystal. This the CPU clock, 662 * and we assume that it is enabled 663 */ 664 regmap_read(map, ASPEED_HPLL_PARAM, &val); 665 aspeed_clk_data->hws[ASPEED_CLK_HPLL] = aspeed_ast2500_calc_pll("hpll", val); 666 667 /* Strap bits 11:9 define the AXI/AHB clock frequency ratio (aka HCLK)*/ 668 regmap_read(map, ASPEED_STRAP, &val); 669 val = (val >> 9) & 0x7; 670 WARN(val == 0, "strapping is zero: cannot determine ahb clock"); 671 div = 2 * (val + 1); 672 hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, div); 673 aspeed_clk_data->hws[ASPEED_CLK_AHB] = hw; 674 675 /* APB clock clock selection register SCU08 (aka PCLK) */ 676 regmap_read(map, ASPEED_CLK_SELECTION, &val); 677 val = (val >> 23) & 0x7; 678 div = 4 * (val + 1); 679 hw = clk_hw_register_fixed_factor(NULL, "apb", "hpll", 0, 1, div); 680 aspeed_clk_data->hws[ASPEED_CLK_APB] = hw; 681 }; 682 683 static void __init aspeed_cc_init(struct device_node *np) 684 { 685 struct regmap *map; 686 u32 val; 687 int ret; 688 int i; 689 690 scu_base = of_iomap(np, 0); 691 if (!scu_base) 692 return; 693 694 aspeed_clk_data = kzalloc(struct_size(aspeed_clk_data, hws, 695 ASPEED_NUM_CLKS), 696 GFP_KERNEL); 697 if (!aspeed_clk_data) 698 return; 699 700 /* 701 * This way all clocks fetched before the platform device probes, 702 * except those we assign here for early use, will be deferred. 703 */ 704 for (i = 0; i < ASPEED_NUM_CLKS; i++) 705 aspeed_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); 706 707 map = syscon_node_to_regmap(np); 708 if (IS_ERR(map)) { 709 pr_err("no syscon regmap\n"); 710 return; 711 } 712 /* 713 * We check that the regmap works on this very first access, 714 * but as this is an MMIO-backed regmap, subsequent regmap 715 * access is not going to fail and we skip error checks from 716 * this point. 717 */ 718 ret = regmap_read(map, ASPEED_STRAP, &val); 719 if (ret) { 720 pr_err("failed to read strapping register\n"); 721 return; 722 } 723 724 if (of_device_is_compatible(np, "aspeed,ast2400-scu")) 725 aspeed_ast2400_cc(map); 726 else if (of_device_is_compatible(np, "aspeed,ast2500-scu")) 727 aspeed_ast2500_cc(map); 728 else 729 pr_err("unknown platform, failed to add clocks\n"); 730 731 aspeed_clk_data->num = ASPEED_NUM_CLKS; 732 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_clk_data); 733 if (ret) 734 pr_err("failed to add DT provider: %d\n", ret); 735 }; 736 CLK_OF_DECLARE_DRIVER(aspeed_cc_g5, "aspeed,ast2500-scu", aspeed_cc_init); 737 CLK_OF_DECLARE_DRIVER(aspeed_cc_g4, "aspeed,ast2400-scu", aspeed_cc_init); 738