1 // SPDX-License-Identifier: GPL-2.0+ 2 // Copyright IBM Corp 3 4 #define pr_fmt(fmt) "clk-aspeed: " fmt 5 6 #include <linux/mfd/syscon.h> 7 #include <linux/of_address.h> 8 #include <linux/of_device.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 #include <linux/slab.h> 12 13 #include <dt-bindings/clock/aspeed-clock.h> 14 15 #include "clk-aspeed.h" 16 17 #define ASPEED_NUM_CLKS 36 18 19 #define ASPEED_RESET2_OFFSET 32 20 21 #define ASPEED_RESET_CTRL 0x04 22 #define ASPEED_CLK_SELECTION 0x08 23 #define ASPEED_CLK_STOP_CTRL 0x0c 24 #define ASPEED_MPLL_PARAM 0x20 25 #define ASPEED_HPLL_PARAM 0x24 26 #define AST2500_HPLL_BYPASS_EN BIT(20) 27 #define AST2400_HPLL_PROGRAMMED BIT(18) 28 #define AST2400_HPLL_BYPASS_EN BIT(17) 29 #define ASPEED_MISC_CTRL 0x2c 30 #define UART_DIV13_EN BIT(12) 31 #define ASPEED_STRAP 0x70 32 #define CLKIN_25MHZ_EN BIT(23) 33 #define AST2400_CLK_SOURCE_SEL BIT(18) 34 #define ASPEED_CLK_SELECTION_2 0xd8 35 #define ASPEED_RESET_CTRL2 0xd4 36 37 /* Globally visible clocks */ 38 static DEFINE_SPINLOCK(aspeed_clk_lock); 39 40 /* Keeps track of all clocks */ 41 static struct clk_hw_onecell_data *aspeed_clk_data; 42 43 static void __iomem *scu_base; 44 45 /* TODO: ask Aspeed about the actual parent data */ 46 static const struct aspeed_gate_data aspeed_gates[] = { 47 /* clk rst name parent flags */ 48 [ASPEED_CLK_GATE_ECLK] = { 0, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */ 49 [ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */ 50 [ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */ 51 [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */ 52 [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */ 53 [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */ 54 [ASPEED_CLK_GATE_REFCLK] = { 6, -1, "refclk-gate", "clkin", CLK_IS_CRITICAL }, 55 [ASPEED_CLK_GATE_USBPORT2CLK] = { 7, 3, "usb-port2-gate", NULL, 0 }, /* USB2.0 Host port 2 */ 56 [ASPEED_CLK_GATE_LCLK] = { 8, 5, "lclk-gate", NULL, 0 }, /* LPC */ 57 [ASPEED_CLK_GATE_USBUHCICLK] = { 9, 15, "usb-uhci-gate", NULL, 0 }, /* USB1.1 (requires port 2 enabled) */ 58 [ASPEED_CLK_GATE_D1CLK] = { 10, 13, "d1clk-gate", NULL, 0 }, /* GFX CRT */ 59 [ASPEED_CLK_GATE_YCLK] = { 13, 4, "yclk-gate", NULL, 0 }, /* HAC */ 60 [ASPEED_CLK_GATE_USBPORT1CLK] = { 14, 14, "usb-port1-gate", NULL, 0 }, /* USB2 hub/USB2 host port 1/USB1.1 dev */ 61 [ASPEED_CLK_GATE_UART1CLK] = { 15, -1, "uart1clk-gate", "uart", 0 }, /* UART1 */ 62 [ASPEED_CLK_GATE_UART2CLK] = { 16, -1, "uart2clk-gate", "uart", 0 }, /* UART2 */ 63 [ASPEED_CLK_GATE_UART5CLK] = { 17, -1, "uart5clk-gate", "uart", 0 }, /* UART5 */ 64 [ASPEED_CLK_GATE_ESPICLK] = { 19, -1, "espiclk-gate", NULL, 0 }, /* eSPI */ 65 [ASPEED_CLK_GATE_MAC1CLK] = { 20, 11, "mac1clk-gate", "mac", 0 }, /* MAC1 */ 66 [ASPEED_CLK_GATE_MAC2CLK] = { 21, 12, "mac2clk-gate", "mac", 0 }, /* MAC2 */ 67 [ASPEED_CLK_GATE_RSACLK] = { 24, -1, "rsaclk-gate", NULL, 0 }, /* RSA */ 68 [ASPEED_CLK_GATE_UART3CLK] = { 25, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */ 69 [ASPEED_CLK_GATE_UART4CLK] = { 26, -1, "uart4clk-gate", "uart", 0 }, /* UART4 */ 70 [ASPEED_CLK_GATE_SDCLK] = { 27, 16, "sdclk-gate", NULL, 0 }, /* SDIO/SD */ 71 [ASPEED_CLK_GATE_LHCCLK] = { 28, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */ 72 }; 73 74 static const char * const eclk_parent_names[] = { 75 "mpll", 76 "hpll", 77 "dpll", 78 }; 79 80 static const struct clk_div_table ast2500_eclk_div_table[] = { 81 { 0x0, 2 }, 82 { 0x1, 2 }, 83 { 0x2, 3 }, 84 { 0x3, 4 }, 85 { 0x4, 5 }, 86 { 0x5, 6 }, 87 { 0x6, 7 }, 88 { 0x7, 8 }, 89 { 0 } 90 }; 91 92 static const struct clk_div_table ast2500_mac_div_table[] = { 93 { 0x0, 4 }, /* Yep, really. Aspeed confirmed this is correct */ 94 { 0x1, 4 }, 95 { 0x2, 6 }, 96 { 0x3, 8 }, 97 { 0x4, 10 }, 98 { 0x5, 12 }, 99 { 0x6, 14 }, 100 { 0x7, 16 }, 101 { 0 } 102 }; 103 104 static const struct clk_div_table ast2400_div_table[] = { 105 { 0x0, 2 }, 106 { 0x1, 4 }, 107 { 0x2, 6 }, 108 { 0x3, 8 }, 109 { 0x4, 10 }, 110 { 0x5, 12 }, 111 { 0x6, 14 }, 112 { 0x7, 16 }, 113 { 0 } 114 }; 115 116 static const struct clk_div_table ast2500_div_table[] = { 117 { 0x0, 4 }, 118 { 0x1, 8 }, 119 { 0x2, 12 }, 120 { 0x3, 16 }, 121 { 0x4, 20 }, 122 { 0x5, 24 }, 123 { 0x6, 28 }, 124 { 0x7, 32 }, 125 { 0 } 126 }; 127 128 static struct clk_hw *aspeed_ast2400_calc_pll(const char *name, u32 val) 129 { 130 unsigned int mult, div; 131 132 if (val & AST2400_HPLL_BYPASS_EN) { 133 /* Pass through mode */ 134 mult = div = 1; 135 } else { 136 /* F = 24Mhz * (2-OD) * [(N + 2) / (D + 1)] */ 137 u32 n = (val >> 5) & 0x3f; 138 u32 od = (val >> 4) & 0x1; 139 u32 d = val & 0xf; 140 141 mult = (2 - od) * (n + 2); 142 div = d + 1; 143 } 144 return clk_hw_register_fixed_factor(NULL, name, "clkin", 0, 145 mult, div); 146 }; 147 148 static struct clk_hw *aspeed_ast2500_calc_pll(const char *name, u32 val) 149 { 150 unsigned int mult, div; 151 152 if (val & AST2500_HPLL_BYPASS_EN) { 153 /* Pass through mode */ 154 mult = div = 1; 155 } else { 156 /* F = clkin * [(M+1) / (N+1)] / (P + 1) */ 157 u32 p = (val >> 13) & 0x3f; 158 u32 m = (val >> 5) & 0xff; 159 u32 n = val & 0x1f; 160 161 mult = (m + 1) / (n + 1); 162 div = p + 1; 163 } 164 165 return clk_hw_register_fixed_factor(NULL, name, "clkin", 0, 166 mult, div); 167 } 168 169 static const struct aspeed_clk_soc_data ast2500_data = { 170 .div_table = ast2500_div_table, 171 .eclk_div_table = ast2500_eclk_div_table, 172 .mac_div_table = ast2500_mac_div_table, 173 .calc_pll = aspeed_ast2500_calc_pll, 174 }; 175 176 static const struct aspeed_clk_soc_data ast2400_data = { 177 .div_table = ast2400_div_table, 178 .eclk_div_table = ast2400_div_table, 179 .mac_div_table = ast2400_div_table, 180 .calc_pll = aspeed_ast2400_calc_pll, 181 }; 182 183 static int aspeed_clk_is_enabled(struct clk_hw *hw) 184 { 185 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); 186 u32 clk = BIT(gate->clock_idx); 187 u32 rst = BIT(gate->reset_idx); 188 u32 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk; 189 u32 reg; 190 191 /* 192 * If the IP is in reset, treat the clock as not enabled, 193 * this happens with some clocks such as the USB one when 194 * coming from cold reset. Without this, aspeed_clk_enable() 195 * will fail to lift the reset. 196 */ 197 if (gate->reset_idx >= 0) { 198 regmap_read(gate->map, ASPEED_RESET_CTRL, ®); 199 if (reg & rst) 200 return 0; 201 } 202 203 regmap_read(gate->map, ASPEED_CLK_STOP_CTRL, ®); 204 205 return ((reg & clk) == enval) ? 1 : 0; 206 } 207 208 static int aspeed_clk_enable(struct clk_hw *hw) 209 { 210 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); 211 unsigned long flags; 212 u32 clk = BIT(gate->clock_idx); 213 u32 rst = BIT(gate->reset_idx); 214 u32 enval; 215 216 spin_lock_irqsave(gate->lock, flags); 217 218 if (aspeed_clk_is_enabled(hw)) { 219 spin_unlock_irqrestore(gate->lock, flags); 220 return 0; 221 } 222 223 if (gate->reset_idx >= 0) { 224 /* Put IP in reset */ 225 regmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, rst); 226 227 /* Delay 100us */ 228 udelay(100); 229 } 230 231 /* Enable clock */ 232 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk; 233 regmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, enval); 234 235 if (gate->reset_idx >= 0) { 236 /* A delay of 10ms is specified by the ASPEED docs */ 237 mdelay(10); 238 239 /* Take IP out of reset */ 240 regmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, 0); 241 } 242 243 spin_unlock_irqrestore(gate->lock, flags); 244 245 return 0; 246 } 247 248 static void aspeed_clk_disable(struct clk_hw *hw) 249 { 250 struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw); 251 unsigned long flags; 252 u32 clk = BIT(gate->clock_idx); 253 u32 enval; 254 255 spin_lock_irqsave(gate->lock, flags); 256 257 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? clk : 0; 258 regmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, enval); 259 260 spin_unlock_irqrestore(gate->lock, flags); 261 } 262 263 static const struct clk_ops aspeed_clk_gate_ops = { 264 .enable = aspeed_clk_enable, 265 .disable = aspeed_clk_disable, 266 .is_enabled = aspeed_clk_is_enabled, 267 }; 268 269 static const u8 aspeed_resets[] = { 270 /* SCU04 resets */ 271 [ASPEED_RESET_XDMA] = 25, 272 [ASPEED_RESET_MCTP] = 24, 273 [ASPEED_RESET_ADC] = 23, 274 [ASPEED_RESET_JTAG_MASTER] = 22, 275 [ASPEED_RESET_MIC] = 18, 276 [ASPEED_RESET_PWM] = 9, 277 [ASPEED_RESET_PECI] = 10, 278 [ASPEED_RESET_I2C] = 2, 279 [ASPEED_RESET_AHB] = 1, 280 281 /* 282 * SCUD4 resets start at an offset to separate them from 283 * the SCU04 resets. 284 */ 285 [ASPEED_RESET_CRT1] = ASPEED_RESET2_OFFSET + 5, 286 }; 287 288 static int aspeed_reset_deassert(struct reset_controller_dev *rcdev, 289 unsigned long id) 290 { 291 struct aspeed_reset *ar = to_aspeed_reset(rcdev); 292 u32 reg = ASPEED_RESET_CTRL; 293 u32 bit = aspeed_resets[id]; 294 295 if (bit >= ASPEED_RESET2_OFFSET) { 296 bit -= ASPEED_RESET2_OFFSET; 297 reg = ASPEED_RESET_CTRL2; 298 } 299 300 return regmap_update_bits(ar->map, reg, BIT(bit), 0); 301 } 302 303 static int aspeed_reset_assert(struct reset_controller_dev *rcdev, 304 unsigned long id) 305 { 306 struct aspeed_reset *ar = to_aspeed_reset(rcdev); 307 u32 reg = ASPEED_RESET_CTRL; 308 u32 bit = aspeed_resets[id]; 309 310 if (bit >= ASPEED_RESET2_OFFSET) { 311 bit -= ASPEED_RESET2_OFFSET; 312 reg = ASPEED_RESET_CTRL2; 313 } 314 315 return regmap_update_bits(ar->map, reg, BIT(bit), BIT(bit)); 316 } 317 318 static int aspeed_reset_status(struct reset_controller_dev *rcdev, 319 unsigned long id) 320 { 321 struct aspeed_reset *ar = to_aspeed_reset(rcdev); 322 u32 reg = ASPEED_RESET_CTRL; 323 u32 bit = aspeed_resets[id]; 324 int ret, val; 325 326 if (bit >= ASPEED_RESET2_OFFSET) { 327 bit -= ASPEED_RESET2_OFFSET; 328 reg = ASPEED_RESET_CTRL2; 329 } 330 331 ret = regmap_read(ar->map, reg, &val); 332 if (ret) 333 return ret; 334 335 return !!(val & BIT(bit)); 336 } 337 338 static const struct reset_control_ops aspeed_reset_ops = { 339 .assert = aspeed_reset_assert, 340 .deassert = aspeed_reset_deassert, 341 .status = aspeed_reset_status, 342 }; 343 344 static struct clk_hw *aspeed_clk_hw_register_gate(struct device *dev, 345 const char *name, const char *parent_name, unsigned long flags, 346 struct regmap *map, u8 clock_idx, u8 reset_idx, 347 u8 clk_gate_flags, spinlock_t *lock) 348 { 349 struct aspeed_clk_gate *gate; 350 struct clk_init_data init; 351 struct clk_hw *hw; 352 int ret; 353 354 gate = kzalloc(sizeof(*gate), GFP_KERNEL); 355 if (!gate) 356 return ERR_PTR(-ENOMEM); 357 358 init.name = name; 359 init.ops = &aspeed_clk_gate_ops; 360 init.flags = flags; 361 init.parent_names = parent_name ? &parent_name : NULL; 362 init.num_parents = parent_name ? 1 : 0; 363 364 gate->map = map; 365 gate->clock_idx = clock_idx; 366 gate->reset_idx = reset_idx; 367 gate->flags = clk_gate_flags; 368 gate->lock = lock; 369 gate->hw.init = &init; 370 371 hw = &gate->hw; 372 ret = clk_hw_register(dev, hw); 373 if (ret) { 374 kfree(gate); 375 hw = ERR_PTR(ret); 376 } 377 378 return hw; 379 } 380 381 static int aspeed_clk_probe(struct platform_device *pdev) 382 { 383 const struct aspeed_clk_soc_data *soc_data; 384 struct device *dev = &pdev->dev; 385 struct aspeed_reset *ar; 386 struct regmap *map; 387 struct clk_hw *hw; 388 u32 val, rate; 389 int i, ret; 390 391 map = syscon_node_to_regmap(dev->of_node); 392 if (IS_ERR(map)) { 393 dev_err(dev, "no syscon regmap\n"); 394 return PTR_ERR(map); 395 } 396 397 ar = devm_kzalloc(dev, sizeof(*ar), GFP_KERNEL); 398 if (!ar) 399 return -ENOMEM; 400 401 ar->map = map; 402 ar->rcdev.owner = THIS_MODULE; 403 ar->rcdev.nr_resets = ARRAY_SIZE(aspeed_resets); 404 ar->rcdev.ops = &aspeed_reset_ops; 405 ar->rcdev.of_node = dev->of_node; 406 407 ret = devm_reset_controller_register(dev, &ar->rcdev); 408 if (ret) { 409 dev_err(dev, "could not register reset controller\n"); 410 return ret; 411 } 412 413 /* SoC generations share common layouts but have different divisors */ 414 soc_data = of_device_get_match_data(dev); 415 if (!soc_data) { 416 dev_err(dev, "no match data for platform\n"); 417 return -EINVAL; 418 } 419 420 /* UART clock div13 setting */ 421 regmap_read(map, ASPEED_MISC_CTRL, &val); 422 if (val & UART_DIV13_EN) 423 rate = 24000000 / 13; 424 else 425 rate = 24000000; 426 /* TODO: Find the parent data for the uart clock */ 427 hw = clk_hw_register_fixed_rate(dev, "uart", NULL, 0, rate); 428 if (IS_ERR(hw)) 429 return PTR_ERR(hw); 430 aspeed_clk_data->hws[ASPEED_CLK_UART] = hw; 431 432 /* 433 * Memory controller (M-PLL) PLL. This clock is configured by the 434 * bootloader, and is exposed to Linux as a read-only clock rate. 435 */ 436 regmap_read(map, ASPEED_MPLL_PARAM, &val); 437 hw = soc_data->calc_pll("mpll", val); 438 if (IS_ERR(hw)) 439 return PTR_ERR(hw); 440 aspeed_clk_data->hws[ASPEED_CLK_MPLL] = hw; 441 442 /* SD/SDIO clock divider and gate */ 443 hw = clk_hw_register_gate(dev, "sd_extclk_gate", "hpll", 0, 444 scu_base + ASPEED_CLK_SELECTION, 15, 0, 445 &aspeed_clk_lock); 446 if (IS_ERR(hw)) 447 return PTR_ERR(hw); 448 hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate", 449 0, scu_base + ASPEED_CLK_SELECTION, 12, 3, 0, 450 soc_data->div_table, 451 &aspeed_clk_lock); 452 if (IS_ERR(hw)) 453 return PTR_ERR(hw); 454 aspeed_clk_data->hws[ASPEED_CLK_SDIO] = hw; 455 456 /* MAC AHB bus clock divider */ 457 hw = clk_hw_register_divider_table(dev, "mac", "hpll", 0, 458 scu_base + ASPEED_CLK_SELECTION, 16, 3, 0, 459 soc_data->mac_div_table, 460 &aspeed_clk_lock); 461 if (IS_ERR(hw)) 462 return PTR_ERR(hw); 463 aspeed_clk_data->hws[ASPEED_CLK_MAC] = hw; 464 465 /* LPC Host (LHCLK) clock divider */ 466 hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0, 467 scu_base + ASPEED_CLK_SELECTION, 20, 3, 0, 468 soc_data->div_table, 469 &aspeed_clk_lock); 470 if (IS_ERR(hw)) 471 return PTR_ERR(hw); 472 aspeed_clk_data->hws[ASPEED_CLK_LHCLK] = hw; 473 474 /* P-Bus (BCLK) clock divider */ 475 hw = clk_hw_register_divider_table(dev, "bclk", "hpll", 0, 476 scu_base + ASPEED_CLK_SELECTION_2, 0, 2, 0, 477 soc_data->div_table, 478 &aspeed_clk_lock); 479 if (IS_ERR(hw)) 480 return PTR_ERR(hw); 481 aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw; 482 483 /* Fixed 24MHz clock */ 484 hw = clk_hw_register_fixed_rate(NULL, "fixed-24m", "clkin", 485 0, 24000000); 486 if (IS_ERR(hw)) 487 return PTR_ERR(hw); 488 aspeed_clk_data->hws[ASPEED_CLK_24M] = hw; 489 490 hw = clk_hw_register_mux(dev, "eclk-mux", eclk_parent_names, 491 ARRAY_SIZE(eclk_parent_names), 0, 492 scu_base + ASPEED_CLK_SELECTION, 2, 0x3, 0, 493 &aspeed_clk_lock); 494 if (IS_ERR(hw)) 495 return PTR_ERR(hw); 496 aspeed_clk_data->hws[ASPEED_CLK_ECLK_MUX] = hw; 497 498 hw = clk_hw_register_divider_table(dev, "eclk", "eclk-mux", 0, 499 scu_base + ASPEED_CLK_SELECTION, 28, 500 3, 0, soc_data->eclk_div_table, 501 &aspeed_clk_lock); 502 if (IS_ERR(hw)) 503 return PTR_ERR(hw); 504 aspeed_clk_data->hws[ASPEED_CLK_ECLK] = hw; 505 506 /* 507 * TODO: There are a number of clocks that not included in this driver 508 * as more information is required: 509 * D2-PLL 510 * D-PLL 511 * YCLK 512 * RGMII 513 * RMII 514 * UART[1..5] clock source mux 515 */ 516 517 for (i = 0; i < ARRAY_SIZE(aspeed_gates); i++) { 518 const struct aspeed_gate_data *gd = &aspeed_gates[i]; 519 u32 gate_flags; 520 521 /* Special case: the USB port 1 clock (bit 14) is always 522 * working the opposite way from the other ones. 523 */ 524 gate_flags = (gd->clock_idx == 14) ? 0 : CLK_GATE_SET_TO_DISABLE; 525 hw = aspeed_clk_hw_register_gate(dev, 526 gd->name, 527 gd->parent_name, 528 gd->flags, 529 map, 530 gd->clock_idx, 531 gd->reset_idx, 532 gate_flags, 533 &aspeed_clk_lock); 534 if (IS_ERR(hw)) 535 return PTR_ERR(hw); 536 aspeed_clk_data->hws[i] = hw; 537 } 538 539 return 0; 540 }; 541 542 static const struct of_device_id aspeed_clk_dt_ids[] = { 543 { .compatible = "aspeed,ast2400-scu", .data = &ast2400_data }, 544 { .compatible = "aspeed,ast2500-scu", .data = &ast2500_data }, 545 { } 546 }; 547 548 static struct platform_driver aspeed_clk_driver = { 549 .probe = aspeed_clk_probe, 550 .driver = { 551 .name = "aspeed-clk", 552 .of_match_table = aspeed_clk_dt_ids, 553 .suppress_bind_attrs = true, 554 }, 555 }; 556 builtin_platform_driver(aspeed_clk_driver); 557 558 static void __init aspeed_ast2400_cc(struct regmap *map) 559 { 560 struct clk_hw *hw; 561 u32 val, div, clkin, hpll; 562 const u16 hpll_rates[][4] = { 563 {384, 360, 336, 408}, 564 {400, 375, 350, 425}, 565 }; 566 int rate; 567 568 /* 569 * CLKIN is the crystal oscillator, 24, 48 or 25MHz selected by 570 * strapping 571 */ 572 regmap_read(map, ASPEED_STRAP, &val); 573 rate = (val >> 8) & 3; 574 if (val & CLKIN_25MHZ_EN) { 575 clkin = 25000000; 576 hpll = hpll_rates[1][rate]; 577 } else if (val & AST2400_CLK_SOURCE_SEL) { 578 clkin = 48000000; 579 hpll = hpll_rates[0][rate]; 580 } else { 581 clkin = 24000000; 582 hpll = hpll_rates[0][rate]; 583 } 584 hw = clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, clkin); 585 pr_debug("clkin @%u MHz\n", clkin / 1000000); 586 587 /* 588 * High-speed PLL clock derived from the crystal. This the CPU clock, 589 * and we assume that it is enabled. It can be configured through the 590 * HPLL_PARAM register, or set to a specified frequency by strapping. 591 */ 592 regmap_read(map, ASPEED_HPLL_PARAM, &val); 593 if (val & AST2400_HPLL_PROGRAMMED) 594 hw = aspeed_ast2400_calc_pll("hpll", val); 595 else 596 hw = clk_hw_register_fixed_rate(NULL, "hpll", "clkin", 0, 597 hpll * 1000000); 598 599 aspeed_clk_data->hws[ASPEED_CLK_HPLL] = hw; 600 601 /* 602 * Strap bits 11:10 define the CPU/AHB clock frequency ratio (aka HCLK) 603 * 00: Select CPU:AHB = 1:1 604 * 01: Select CPU:AHB = 2:1 605 * 10: Select CPU:AHB = 4:1 606 * 11: Select CPU:AHB = 3:1 607 */ 608 regmap_read(map, ASPEED_STRAP, &val); 609 val = (val >> 10) & 0x3; 610 div = val + 1; 611 if (div == 3) 612 div = 4; 613 else if (div == 4) 614 div = 3; 615 hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, div); 616 aspeed_clk_data->hws[ASPEED_CLK_AHB] = hw; 617 618 /* APB clock clock selection register SCU08 (aka PCLK) */ 619 hw = clk_hw_register_divider_table(NULL, "apb", "hpll", 0, 620 scu_base + ASPEED_CLK_SELECTION, 23, 3, 0, 621 ast2400_div_table, 622 &aspeed_clk_lock); 623 aspeed_clk_data->hws[ASPEED_CLK_APB] = hw; 624 } 625 626 static void __init aspeed_ast2500_cc(struct regmap *map) 627 { 628 struct clk_hw *hw; 629 u32 val, freq, div; 630 631 /* CLKIN is the crystal oscillator, 24 or 25MHz selected by strapping */ 632 regmap_read(map, ASPEED_STRAP, &val); 633 if (val & CLKIN_25MHZ_EN) 634 freq = 25000000; 635 else 636 freq = 24000000; 637 hw = clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, freq); 638 pr_debug("clkin @%u MHz\n", freq / 1000000); 639 640 /* 641 * High-speed PLL clock derived from the crystal. This the CPU clock, 642 * and we assume that it is enabled 643 */ 644 regmap_read(map, ASPEED_HPLL_PARAM, &val); 645 aspeed_clk_data->hws[ASPEED_CLK_HPLL] = aspeed_ast2500_calc_pll("hpll", val); 646 647 /* Strap bits 11:9 define the AXI/AHB clock frequency ratio (aka HCLK)*/ 648 regmap_read(map, ASPEED_STRAP, &val); 649 val = (val >> 9) & 0x7; 650 WARN(val == 0, "strapping is zero: cannot determine ahb clock"); 651 div = 2 * (val + 1); 652 hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, div); 653 aspeed_clk_data->hws[ASPEED_CLK_AHB] = hw; 654 655 /* APB clock clock selection register SCU08 (aka PCLK) */ 656 regmap_read(map, ASPEED_CLK_SELECTION, &val); 657 val = (val >> 23) & 0x7; 658 div = 4 * (val + 1); 659 hw = clk_hw_register_fixed_factor(NULL, "apb", "hpll", 0, 1, div); 660 aspeed_clk_data->hws[ASPEED_CLK_APB] = hw; 661 }; 662 663 static void __init aspeed_cc_init(struct device_node *np) 664 { 665 struct regmap *map; 666 u32 val; 667 int ret; 668 int i; 669 670 scu_base = of_iomap(np, 0); 671 if (!scu_base) 672 return; 673 674 aspeed_clk_data = kzalloc(struct_size(aspeed_clk_data, hws, 675 ASPEED_NUM_CLKS), 676 GFP_KERNEL); 677 if (!aspeed_clk_data) 678 return; 679 680 /* 681 * This way all clocks fetched before the platform device probes, 682 * except those we assign here for early use, will be deferred. 683 */ 684 for (i = 0; i < ASPEED_NUM_CLKS; i++) 685 aspeed_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); 686 687 map = syscon_node_to_regmap(np); 688 if (IS_ERR(map)) { 689 pr_err("no syscon regmap\n"); 690 return; 691 } 692 /* 693 * We check that the regmap works on this very first access, 694 * but as this is an MMIO-backed regmap, subsequent regmap 695 * access is not going to fail and we skip error checks from 696 * this point. 697 */ 698 ret = regmap_read(map, ASPEED_STRAP, &val); 699 if (ret) { 700 pr_err("failed to read strapping register\n"); 701 return; 702 } 703 704 if (of_device_is_compatible(np, "aspeed,ast2400-scu")) 705 aspeed_ast2400_cc(map); 706 else if (of_device_is_compatible(np, "aspeed,ast2500-scu")) 707 aspeed_ast2500_cc(map); 708 else 709 pr_err("unknown platform, failed to add clocks\n"); 710 711 aspeed_clk_data->num = ASPEED_NUM_CLKS; 712 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_clk_data); 713 if (ret) 714 pr_err("failed to add DT provider: %d\n", ret); 715 }; 716 CLK_OF_DECLARE_DRIVER(aspeed_cc_g5, "aspeed,ast2500-scu", aspeed_cc_init); 717 CLK_OF_DECLARE_DRIVER(aspeed_cc_g4, "aspeed,ast2400-scu", aspeed_cc_init); 718