1 /* 2 * Copyright (c) 2014 Oleksij Rempel <linux@rempel-privat.de>. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #include <linux/clk.h> 18 #include <linux/clkdev.h> 19 #include <linux/err.h> 20 #include <linux/io.h> 21 #include <linux/clk-provider.h> 22 #include <linux/spinlock.h> 23 #include <linux/of.h> 24 #include <linux/of_address.h> 25 #include <dt-bindings/clock/alphascale,asm9260.h> 26 27 #define HW_AHBCLKCTRL0 0x0020 28 #define HW_AHBCLKCTRL1 0x0030 29 #define HW_SYSPLLCTRL 0x0100 30 #define HW_MAINCLKSEL 0x0120 31 #define HW_MAINCLKUEN 0x0124 32 #define HW_UARTCLKSEL 0x0128 33 #define HW_UARTCLKUEN 0x012c 34 #define HW_I2S0CLKSEL 0x0130 35 #define HW_I2S0CLKUEN 0x0134 36 #define HW_I2S1CLKSEL 0x0138 37 #define HW_I2S1CLKUEN 0x013c 38 #define HW_WDTCLKSEL 0x0160 39 #define HW_WDTCLKUEN 0x0164 40 #define HW_CLKOUTCLKSEL 0x0170 41 #define HW_CLKOUTCLKUEN 0x0174 42 #define HW_CPUCLKDIV 0x017c 43 #define HW_SYSAHBCLKDIV 0x0180 44 #define HW_I2S0MCLKDIV 0x0190 45 #define HW_I2S0SCLKDIV 0x0194 46 #define HW_I2S1MCLKDIV 0x0188 47 #define HW_I2S1SCLKDIV 0x018c 48 #define HW_UART0CLKDIV 0x0198 49 #define HW_UART1CLKDIV 0x019c 50 #define HW_UART2CLKDIV 0x01a0 51 #define HW_UART3CLKDIV 0x01a4 52 #define HW_UART4CLKDIV 0x01a8 53 #define HW_UART5CLKDIV 0x01ac 54 #define HW_UART6CLKDIV 0x01b0 55 #define HW_UART7CLKDIV 0x01b4 56 #define HW_UART8CLKDIV 0x01b8 57 #define HW_UART9CLKDIV 0x01bc 58 #define HW_SPI0CLKDIV 0x01c0 59 #define HW_SPI1CLKDIV 0x01c4 60 #define HW_QUADSPICLKDIV 0x01c8 61 #define HW_SSP0CLKDIV 0x01d0 62 #define HW_NANDCLKDIV 0x01d4 63 #define HW_TRACECLKDIV 0x01e0 64 #define HW_CAMMCLKDIV 0x01e8 65 #define HW_WDTCLKDIV 0x01ec 66 #define HW_CLKOUTCLKDIV 0x01f4 67 #define HW_MACCLKDIV 0x01f8 68 #define HW_LCDCLKDIV 0x01fc 69 #define HW_ADCANACLKDIV 0x0200 70 71 static struct clk *clks[MAX_CLKS]; 72 static struct clk_onecell_data clk_data; 73 static DEFINE_SPINLOCK(asm9260_clk_lock); 74 75 struct asm9260_div_clk { 76 unsigned int idx; 77 const char *name; 78 const char *parent_name; 79 u32 reg; 80 }; 81 82 struct asm9260_gate_data { 83 unsigned int idx; 84 const char *name; 85 const char *parent_name; 86 u32 reg; 87 u8 bit_idx; 88 unsigned long flags; 89 }; 90 91 struct asm9260_mux_clock { 92 u8 mask; 93 u32 *table; 94 const char *name; 95 const char **parent_names; 96 u8 num_parents; 97 unsigned long offset; 98 unsigned long flags; 99 }; 100 101 static void __iomem *base; 102 103 static const struct asm9260_div_clk asm9260_div_clks[] __initconst = { 104 { CLKID_SYS_CPU, "cpu_div", "main_gate", HW_CPUCLKDIV }, 105 { CLKID_SYS_AHB, "ahb_div", "cpu_div", HW_SYSAHBCLKDIV }, 106 107 /* i2s has two deviders: one for only external mclk and internal 108 * devider for all clks. */ 109 { CLKID_SYS_I2S0M, "i2s0m_div", "i2s0_mclk", HW_I2S0MCLKDIV }, 110 { CLKID_SYS_I2S1M, "i2s1m_div", "i2s1_mclk", HW_I2S1MCLKDIV }, 111 { CLKID_SYS_I2S0S, "i2s0s_div", "i2s0_gate", HW_I2S0SCLKDIV }, 112 { CLKID_SYS_I2S1S, "i2s1s_div", "i2s0_gate", HW_I2S1SCLKDIV }, 113 114 { CLKID_SYS_UART0, "uart0_div", "uart_gate", HW_UART0CLKDIV }, 115 { CLKID_SYS_UART1, "uart1_div", "uart_gate", HW_UART1CLKDIV }, 116 { CLKID_SYS_UART2, "uart2_div", "uart_gate", HW_UART2CLKDIV }, 117 { CLKID_SYS_UART3, "uart3_div", "uart_gate", HW_UART3CLKDIV }, 118 { CLKID_SYS_UART4, "uart4_div", "uart_gate", HW_UART4CLKDIV }, 119 { CLKID_SYS_UART5, "uart5_div", "uart_gate", HW_UART5CLKDIV }, 120 { CLKID_SYS_UART6, "uart6_div", "uart_gate", HW_UART6CLKDIV }, 121 { CLKID_SYS_UART7, "uart7_div", "uart_gate", HW_UART7CLKDIV }, 122 { CLKID_SYS_UART8, "uart8_div", "uart_gate", HW_UART8CLKDIV }, 123 { CLKID_SYS_UART9, "uart9_div", "uart_gate", HW_UART9CLKDIV }, 124 125 { CLKID_SYS_SPI0, "spi0_div", "main_gate", HW_SPI0CLKDIV }, 126 { CLKID_SYS_SPI1, "spi1_div", "main_gate", HW_SPI1CLKDIV }, 127 { CLKID_SYS_QUADSPI, "quadspi_div", "main_gate", HW_QUADSPICLKDIV }, 128 { CLKID_SYS_SSP0, "ssp0_div", "main_gate", HW_SSP0CLKDIV }, 129 { CLKID_SYS_NAND, "nand_div", "main_gate", HW_NANDCLKDIV }, 130 { CLKID_SYS_TRACE, "trace_div", "main_gate", HW_TRACECLKDIV }, 131 { CLKID_SYS_CAMM, "camm_div", "main_gate", HW_CAMMCLKDIV }, 132 { CLKID_SYS_MAC, "mac_div", "main_gate", HW_MACCLKDIV }, 133 { CLKID_SYS_LCD, "lcd_div", "main_gate", HW_LCDCLKDIV }, 134 { CLKID_SYS_ADCANA, "adcana_div", "main_gate", HW_ADCANACLKDIV }, 135 136 { CLKID_SYS_WDT, "wdt_div", "wdt_gate", HW_WDTCLKDIV }, 137 { CLKID_SYS_CLKOUT, "clkout_div", "clkout_gate", HW_CLKOUTCLKDIV }, 138 }; 139 140 static const struct asm9260_gate_data asm9260_mux_gates[] __initconst = { 141 { 0, "main_gate", "main_mux", HW_MAINCLKUEN, 0 }, 142 { 0, "uart_gate", "uart_mux", HW_UARTCLKUEN, 0 }, 143 { 0, "i2s0_gate", "i2s0_mux", HW_I2S0CLKUEN, 0 }, 144 { 0, "i2s1_gate", "i2s1_mux", HW_I2S1CLKUEN, 0 }, 145 { 0, "wdt_gate", "wdt_mux", HW_WDTCLKUEN, 0 }, 146 { 0, "clkout_gate", "clkout_mux", HW_CLKOUTCLKUEN, 0 }, 147 }; 148 static const struct asm9260_gate_data asm9260_ahb_gates[] __initconst = { 149 /* ahb gates */ 150 { CLKID_AHB_ROM, "rom", "ahb_div", 151 HW_AHBCLKCTRL0, 1, CLK_IGNORE_UNUSED}, 152 { CLKID_AHB_RAM, "ram", "ahb_div", 153 HW_AHBCLKCTRL0, 2, CLK_IGNORE_UNUSED}, 154 { CLKID_AHB_GPIO, "gpio", "ahb_div", 155 HW_AHBCLKCTRL0, 4 }, 156 { CLKID_AHB_MAC, "mac", "ahb_div", 157 HW_AHBCLKCTRL0, 5 }, 158 { CLKID_AHB_EMI, "emi", "ahb_div", 159 HW_AHBCLKCTRL0, 6, CLK_IGNORE_UNUSED}, 160 { CLKID_AHB_USB0, "usb0", "ahb_div", 161 HW_AHBCLKCTRL0, 7 }, 162 { CLKID_AHB_USB1, "usb1", "ahb_div", 163 HW_AHBCLKCTRL0, 8 }, 164 { CLKID_AHB_DMA0, "dma0", "ahb_div", 165 HW_AHBCLKCTRL0, 9 }, 166 { CLKID_AHB_DMA1, "dma1", "ahb_div", 167 HW_AHBCLKCTRL0, 10 }, 168 { CLKID_AHB_UART0, "uart0", "ahb_div", 169 HW_AHBCLKCTRL0, 11 }, 170 { CLKID_AHB_UART1, "uart1", "ahb_div", 171 HW_AHBCLKCTRL0, 12 }, 172 { CLKID_AHB_UART2, "uart2", "ahb_div", 173 HW_AHBCLKCTRL0, 13 }, 174 { CLKID_AHB_UART3, "uart3", "ahb_div", 175 HW_AHBCLKCTRL0, 14 }, 176 { CLKID_AHB_UART4, "uart4", "ahb_div", 177 HW_AHBCLKCTRL0, 15 }, 178 { CLKID_AHB_UART5, "uart5", "ahb_div", 179 HW_AHBCLKCTRL0, 16 }, 180 { CLKID_AHB_UART6, "uart6", "ahb_div", 181 HW_AHBCLKCTRL0, 17 }, 182 { CLKID_AHB_UART7, "uart7", "ahb_div", 183 HW_AHBCLKCTRL0, 18 }, 184 { CLKID_AHB_UART8, "uart8", "ahb_div", 185 HW_AHBCLKCTRL0, 19 }, 186 { CLKID_AHB_UART9, "uart9", "ahb_div", 187 HW_AHBCLKCTRL0, 20 }, 188 { CLKID_AHB_I2S0, "i2s0", "ahb_div", 189 HW_AHBCLKCTRL0, 21 }, 190 { CLKID_AHB_I2C0, "i2c0", "ahb_div", 191 HW_AHBCLKCTRL0, 22 }, 192 { CLKID_AHB_I2C1, "i2c1", "ahb_div", 193 HW_AHBCLKCTRL0, 23 }, 194 { CLKID_AHB_SSP0, "ssp0", "ahb_div", 195 HW_AHBCLKCTRL0, 24 }, 196 { CLKID_AHB_IOCONFIG, "ioconf", "ahb_div", 197 HW_AHBCLKCTRL0, 25 }, 198 { CLKID_AHB_WDT, "wdt", "ahb_div", 199 HW_AHBCLKCTRL0, 26 }, 200 { CLKID_AHB_CAN0, "can0", "ahb_div", 201 HW_AHBCLKCTRL0, 27 }, 202 { CLKID_AHB_CAN1, "can1", "ahb_div", 203 HW_AHBCLKCTRL0, 28 }, 204 { CLKID_AHB_MPWM, "mpwm", "ahb_div", 205 HW_AHBCLKCTRL0, 29 }, 206 { CLKID_AHB_SPI0, "spi0", "ahb_div", 207 HW_AHBCLKCTRL0, 30 }, 208 { CLKID_AHB_SPI1, "spi1", "ahb_div", 209 HW_AHBCLKCTRL0, 31 }, 210 211 { CLKID_AHB_QEI, "qei", "ahb_div", 212 HW_AHBCLKCTRL1, 0 }, 213 { CLKID_AHB_QUADSPI0, "quadspi0", "ahb_div", 214 HW_AHBCLKCTRL1, 1 }, 215 { CLKID_AHB_CAMIF, "capmif", "ahb_div", 216 HW_AHBCLKCTRL1, 2 }, 217 { CLKID_AHB_LCDIF, "lcdif", "ahb_div", 218 HW_AHBCLKCTRL1, 3 }, 219 { CLKID_AHB_TIMER0, "timer0", "ahb_div", 220 HW_AHBCLKCTRL1, 4 }, 221 { CLKID_AHB_TIMER1, "timer1", "ahb_div", 222 HW_AHBCLKCTRL1, 5 }, 223 { CLKID_AHB_TIMER2, "timer2", "ahb_div", 224 HW_AHBCLKCTRL1, 6 }, 225 { CLKID_AHB_TIMER3, "timer3", "ahb_div", 226 HW_AHBCLKCTRL1, 7 }, 227 { CLKID_AHB_IRQ, "irq", "ahb_div", 228 HW_AHBCLKCTRL1, 8, CLK_IGNORE_UNUSED}, 229 { CLKID_AHB_RTC, "rtc", "ahb_div", 230 HW_AHBCLKCTRL1, 9 }, 231 { CLKID_AHB_NAND, "nand", "ahb_div", 232 HW_AHBCLKCTRL1, 10 }, 233 { CLKID_AHB_ADC0, "adc0", "ahb_div", 234 HW_AHBCLKCTRL1, 11 }, 235 { CLKID_AHB_LED, "led", "ahb_div", 236 HW_AHBCLKCTRL1, 12 }, 237 { CLKID_AHB_DAC0, "dac0", "ahb_div", 238 HW_AHBCLKCTRL1, 13 }, 239 { CLKID_AHB_LCD, "lcd", "ahb_div", 240 HW_AHBCLKCTRL1, 14 }, 241 { CLKID_AHB_I2S1, "i2s1", "ahb_div", 242 HW_AHBCLKCTRL1, 15 }, 243 { CLKID_AHB_MAC1, "mac1", "ahb_div", 244 HW_AHBCLKCTRL1, 16 }, 245 }; 246 247 static const char __initdata *main_mux_p[] = { NULL, NULL }; 248 static const char __initdata *i2s0_mux_p[] = { NULL, NULL, "i2s0m_div"}; 249 static const char __initdata *i2s1_mux_p[] = { NULL, NULL, "i2s1m_div"}; 250 static const char __initdata *clkout_mux_p[] = { NULL, NULL, "rtc"}; 251 static u32 three_mux_table[] = {0, 1, 3}; 252 253 static struct asm9260_mux_clock asm9260_mux_clks[] __initdata = { 254 { 1, three_mux_table, "main_mux", main_mux_p, 255 ARRAY_SIZE(main_mux_p), HW_MAINCLKSEL, }, 256 { 1, three_mux_table, "uart_mux", main_mux_p, 257 ARRAY_SIZE(main_mux_p), HW_UARTCLKSEL, }, 258 { 1, three_mux_table, "wdt_mux", main_mux_p, 259 ARRAY_SIZE(main_mux_p), HW_WDTCLKSEL, }, 260 { 3, three_mux_table, "i2s0_mux", i2s0_mux_p, 261 ARRAY_SIZE(i2s0_mux_p), HW_I2S0CLKSEL, }, 262 { 3, three_mux_table, "i2s1_mux", i2s1_mux_p, 263 ARRAY_SIZE(i2s1_mux_p), HW_I2S1CLKSEL, }, 264 { 3, three_mux_table, "clkout_mux", clkout_mux_p, 265 ARRAY_SIZE(clkout_mux_p), HW_CLKOUTCLKSEL, }, 266 }; 267 268 static void __init asm9260_acc_init(struct device_node *np) 269 { 270 struct clk *clk; 271 const char *ref_clk, *pll_clk = "pll"; 272 u32 rate; 273 int n; 274 u32 accuracy = 0; 275 276 base = of_io_request_and_map(np, 0, np->name); 277 if (IS_ERR(base)) 278 panic("%s: unable to map resource", np->name); 279 280 /* register pll */ 281 rate = (ioread32(base + HW_SYSPLLCTRL) & 0xffff) * 1000000; 282 283 ref_clk = of_clk_get_parent_name(np, 0); 284 accuracy = clk_get_accuracy(__clk_lookup(ref_clk)); 285 clk = clk_register_fixed_rate_with_accuracy(NULL, pll_clk, 286 ref_clk, 0, rate, accuracy); 287 288 if (IS_ERR(clk)) 289 panic("%s: can't register REFCLK. Check DT!", np->name); 290 291 for (n = 0; n < ARRAY_SIZE(asm9260_mux_clks); n++) { 292 const struct asm9260_mux_clock *mc = &asm9260_mux_clks[n]; 293 294 mc->parent_names[0] = ref_clk; 295 mc->parent_names[1] = pll_clk; 296 clk = clk_register_mux_table(NULL, mc->name, mc->parent_names, 297 mc->num_parents, mc->flags, base + mc->offset, 298 0, mc->mask, 0, mc->table, &asm9260_clk_lock); 299 } 300 301 /* clock mux gate cells */ 302 for (n = 0; n < ARRAY_SIZE(asm9260_mux_gates); n++) { 303 const struct asm9260_gate_data *gd = &asm9260_mux_gates[n]; 304 305 clk = clk_register_gate(NULL, gd->name, 306 gd->parent_name, gd->flags | CLK_SET_RATE_PARENT, 307 base + gd->reg, gd->bit_idx, 0, &asm9260_clk_lock); 308 } 309 310 /* clock div cells */ 311 for (n = 0; n < ARRAY_SIZE(asm9260_div_clks); n++) { 312 const struct asm9260_div_clk *dc = &asm9260_div_clks[n]; 313 314 clks[dc->idx] = clk_register_divider(NULL, dc->name, 315 dc->parent_name, CLK_SET_RATE_PARENT, 316 base + dc->reg, 0, 8, CLK_DIVIDER_ONE_BASED, 317 &asm9260_clk_lock); 318 } 319 320 /* clock ahb gate cells */ 321 for (n = 0; n < ARRAY_SIZE(asm9260_ahb_gates); n++) { 322 const struct asm9260_gate_data *gd = &asm9260_ahb_gates[n]; 323 324 clks[gd->idx] = clk_register_gate(NULL, gd->name, 325 gd->parent_name, gd->flags, base + gd->reg, 326 gd->bit_idx, 0, &asm9260_clk_lock); 327 } 328 329 /* check for errors on leaf clocks */ 330 for (n = 0; n < MAX_CLKS; n++) { 331 if (!IS_ERR(clks[n])) 332 continue; 333 334 pr_err("%s: Unable to register leaf clock %d\n", 335 np->full_name, n); 336 goto fail; 337 } 338 339 /* register clk-provider */ 340 clk_data.clks = clks; 341 clk_data.clk_num = MAX_CLKS; 342 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 343 return; 344 fail: 345 iounmap(base); 346 } 347 CLK_OF_DECLARE(asm9260_acc, "alphascale,asm9260-clock-controller", 348 asm9260_acc_init); 349