1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (C) 2015 Broadcom Corporation 3 4 #include <linux/kernel.h> 5 #include <linux/err.h> 6 #include <linux/clk-provider.h> 7 #include <linux/io.h> 8 #include <linux/of.h> 9 #include <linux/of_address.h> 10 11 #include <dt-bindings/clock/bcm-nsp.h> 12 #include "clk-iproc.h" 13 14 #define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, } 15 16 #define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \ 17 .pwr_shift = ps, .iso_shift = is } 18 19 #define RESET_VAL(o, rs, prs) { .offset = o, .reset_shift = rs, \ 20 .p_reset_shift = prs } 21 22 #define DF_VAL(o, kis, kiw, kps, kpw, kas, kaw) { .offset = o, .ki_shift = kis,\ 23 .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \ 24 .ka_width = kaw } 25 26 #define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \ 27 .hold_shift = hs, .bypass_shift = bs } 28 29 static void __init nsp_armpll_init(struct device_node *node) 30 { 31 iproc_armpll_setup(node); 32 } 33 CLK_OF_DECLARE(nsp_armpll, "brcm,nsp-armpll", nsp_armpll_init); 34 35 static const struct iproc_pll_ctrl genpll = { 36 .flags = IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_EMBED_PWRCTRL, 37 .aon = AON_VAL(0x0, 1, 12, 0), 38 .reset = RESET_VAL(0x0, 11, 10), 39 .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3), 40 .ndiv_int = REG_VAL(0x14, 20, 10), 41 .ndiv_frac = REG_VAL(0x14, 0, 20), 42 .pdiv = REG_VAL(0x18, 24, 3), 43 .status = REG_VAL(0x20, 12, 1), 44 }; 45 46 static const struct iproc_clk_ctrl genpll_clk[] = { 47 [BCM_NSP_GENPLL_PHY_CLK] = { 48 .channel = BCM_NSP_GENPLL_PHY_CLK, 49 .flags = IPROC_CLK_AON, 50 .enable = ENABLE_VAL(0x4, 12, 6, 18), 51 .mdiv = REG_VAL(0x18, 16, 8), 52 }, 53 [BCM_NSP_GENPLL_ENET_SW_CLK] = { 54 .channel = BCM_NSP_GENPLL_ENET_SW_CLK, 55 .flags = IPROC_CLK_AON, 56 .enable = ENABLE_VAL(0x4, 13, 7, 19), 57 .mdiv = REG_VAL(0x18, 8, 8), 58 }, 59 [BCM_NSP_GENPLL_USB_PHY_REF_CLK] = { 60 .channel = BCM_NSP_GENPLL_USB_PHY_REF_CLK, 61 .flags = IPROC_CLK_AON, 62 .enable = ENABLE_VAL(0x4, 14, 8, 20), 63 .mdiv = REG_VAL(0x18, 0, 8), 64 }, 65 [BCM_NSP_GENPLL_IPROCFAST_CLK] = { 66 .channel = BCM_NSP_GENPLL_IPROCFAST_CLK, 67 .flags = IPROC_CLK_AON, 68 .enable = ENABLE_VAL(0x4, 15, 9, 21), 69 .mdiv = REG_VAL(0x1c, 16, 8), 70 }, 71 [BCM_NSP_GENPLL_SATA1_CLK] = { 72 .channel = BCM_NSP_GENPLL_SATA1_CLK, 73 .flags = IPROC_CLK_AON, 74 .enable = ENABLE_VAL(0x4, 16, 10, 22), 75 .mdiv = REG_VAL(0x1c, 8, 8), 76 }, 77 [BCM_NSP_GENPLL_SATA2_CLK] = { 78 .channel = BCM_NSP_GENPLL_SATA2_CLK, 79 .flags = IPROC_CLK_AON, 80 .enable = ENABLE_VAL(0x4, 17, 11, 23), 81 .mdiv = REG_VAL(0x1c, 0, 8), 82 }, 83 }; 84 85 static void __init nsp_genpll_clk_init(struct device_node *node) 86 { 87 iproc_pll_clk_setup(node, &genpll, NULL, 0, genpll_clk, 88 ARRAY_SIZE(genpll_clk)); 89 } 90 CLK_OF_DECLARE(nsp_genpll_clk, "brcm,nsp-genpll", nsp_genpll_clk_init); 91 92 static const struct iproc_pll_ctrl lcpll0 = { 93 .flags = IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_EMBED_PWRCTRL, 94 .aon = AON_VAL(0x0, 1, 24, 0), 95 .reset = RESET_VAL(0x0, 23, 22), 96 .dig_filter = DF_VAL(0x0, 16, 3, 12, 4, 19, 4), 97 .ndiv_int = REG_VAL(0x4, 20, 8), 98 .ndiv_frac = REG_VAL(0x4, 0, 20), 99 .pdiv = REG_VAL(0x4, 28, 3), 100 .status = REG_VAL(0x10, 12, 1), 101 }; 102 103 static const struct iproc_clk_ctrl lcpll0_clk[] = { 104 [BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK] = { 105 .channel = BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK, 106 .flags = IPROC_CLK_AON, 107 .enable = ENABLE_VAL(0x0, 6, 3, 9), 108 .mdiv = REG_VAL(0x8, 24, 8), 109 }, 110 [BCM_NSP_LCPLL0_SDIO_CLK] = { 111 .channel = BCM_NSP_LCPLL0_SDIO_CLK, 112 .flags = IPROC_CLK_AON, 113 .enable = ENABLE_VAL(0x0, 7, 4, 10), 114 .mdiv = REG_VAL(0x8, 16, 8), 115 }, 116 [BCM_NSP_LCPLL0_DDR_PHY_CLK] = { 117 .channel = BCM_NSP_LCPLL0_DDR_PHY_CLK, 118 .flags = IPROC_CLK_AON, 119 .enable = ENABLE_VAL(0x0, 8, 5, 11), 120 .mdiv = REG_VAL(0x8, 8, 8), 121 }, 122 }; 123 124 static void __init nsp_lcpll0_clk_init(struct device_node *node) 125 { 126 iproc_pll_clk_setup(node, &lcpll0, NULL, 0, lcpll0_clk, 127 ARRAY_SIZE(lcpll0_clk)); 128 } 129 CLK_OF_DECLARE(nsp_lcpll0_clk, "brcm,nsp-lcpll0", nsp_lcpll0_clk_init); 130