11f27f152SAlex Elder /* 21f27f152SAlex Elder * Copyright (C) 2013 Broadcom Corporation 31f27f152SAlex Elder * Copyright 2013 Linaro Limited 41f27f152SAlex Elder * 51f27f152SAlex Elder * This program is free software; you can redistribute it and/or 61f27f152SAlex Elder * modify it under the terms of the GNU General Public License as 71f27f152SAlex Elder * published by the Free Software Foundation version 2. 81f27f152SAlex Elder * 91f27f152SAlex Elder * This program is distributed "as is" WITHOUT ANY WARRANTY of any 101f27f152SAlex Elder * kind, whether express or implied; without even the implied warranty 111f27f152SAlex Elder * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 121f27f152SAlex Elder * GNU General Public License for more details. 131f27f152SAlex Elder */ 141f27f152SAlex Elder 151f27f152SAlex Elder #ifndef _CLK_KONA_H 161f27f152SAlex Elder #define _CLK_KONA_H 171f27f152SAlex Elder 181f27f152SAlex Elder #include <linux/kernel.h> 191f27f152SAlex Elder #include <linux/list.h> 201f27f152SAlex Elder #include <linux/spinlock.h> 211f27f152SAlex Elder #include <linux/slab.h> 221f27f152SAlex Elder #include <linux/device.h> 231f27f152SAlex Elder #include <linux/of.h> 241f27f152SAlex Elder #include <linux/clk-provider.h> 251f27f152SAlex Elder 261f27f152SAlex Elder #define BILLION 1000000000 271f27f152SAlex Elder 281f27f152SAlex Elder /* The common clock framework uses u8 to represent a parent index */ 291f27f152SAlex Elder #define PARENT_COUNT_MAX ((u32)U8_MAX) 301f27f152SAlex Elder 311f27f152SAlex Elder #define BAD_CLK_INDEX U8_MAX /* Can't ever be valid */ 321f27f152SAlex Elder #define BAD_CLK_NAME ((const char *)-1) 331f27f152SAlex Elder 341f27f152SAlex Elder #define BAD_SCALED_DIV_VALUE U64_MAX 351f27f152SAlex Elder 361f27f152SAlex Elder /* 371f27f152SAlex Elder * Utility macros for object flag management. If possible, flags 381f27f152SAlex Elder * should be defined such that 0 is the desired default value. 391f27f152SAlex Elder */ 401f27f152SAlex Elder #define FLAG(type, flag) BCM_CLK_ ## type ## _FLAGS_ ## flag 411f27f152SAlex Elder #define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag)) 421f27f152SAlex Elder #define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag))) 431f27f152SAlex Elder #define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag)) 441f27f152SAlex Elder #define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag))) 451f27f152SAlex Elder 461f27f152SAlex Elder /* Clock field state tests */ 471f27f152SAlex Elder 481f27f152SAlex Elder #define gate_exists(gate) FLAG_TEST(gate, GATE, EXISTS) 491f27f152SAlex Elder #define gate_is_enabled(gate) FLAG_TEST(gate, GATE, ENABLED) 501f27f152SAlex Elder #define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW) 511f27f152SAlex Elder #define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW) 521f27f152SAlex Elder #define gate_is_sw_managed(gate) FLAG_TEST(gate, GATE, SW_MANAGED) 531f27f152SAlex Elder #define gate_is_no_disable(gate) FLAG_TEST(gate, GATE, NO_DISABLE) 541f27f152SAlex Elder 551f27f152SAlex Elder #define gate_flip_enabled(gate) FLAG_FLIP(gate, GATE, ENABLED) 561f27f152SAlex Elder 571f27f152SAlex Elder #define divider_exists(div) FLAG_TEST(div, DIV, EXISTS) 581f27f152SAlex Elder #define divider_is_fixed(div) FLAG_TEST(div, DIV, FIXED) 591f27f152SAlex Elder #define divider_has_fraction(div) (!divider_is_fixed(div) && \ 60e813d49dSAlex Elder (div)->u.s.frac_width > 0) 611f27f152SAlex Elder 621f27f152SAlex Elder #define selector_exists(sel) ((sel)->width != 0) 631f27f152SAlex Elder #define trigger_exists(trig) FLAG_TEST(trig, TRIG, EXISTS) 641f27f152SAlex Elder 651f27f152SAlex Elder /* Clock type, used to tell common block what it's part of */ 661f27f152SAlex Elder enum bcm_clk_type { 671f27f152SAlex Elder bcm_clk_none, /* undefined clock type */ 681f27f152SAlex Elder bcm_clk_bus, 691f27f152SAlex Elder bcm_clk_core, 701f27f152SAlex Elder bcm_clk_peri 711f27f152SAlex Elder }; 721f27f152SAlex Elder 731f27f152SAlex Elder /* 741f27f152SAlex Elder * Each CCU defines a mapped area of memory containing registers 751f27f152SAlex Elder * used to manage clocks implemented by the CCU. Access to memory 761f27f152SAlex Elder * within the CCU's space is serialized by a spinlock. Before any 771f27f152SAlex Elder * (other) address can be written, a special access "password" value 781f27f152SAlex Elder * must be written to its WR_ACCESS register (located at the base 791f27f152SAlex Elder * address of the range). We keep track of the name of each CCU as 801f27f152SAlex Elder * it is set up, and maintain them in a list. 811f27f152SAlex Elder */ 821f27f152SAlex Elder struct ccu_data { 831f27f152SAlex Elder void __iomem *base; /* base of mapped address space */ 841f27f152SAlex Elder spinlock_t lock; /* serialization lock */ 851f27f152SAlex Elder bool write_enabled; /* write access is currently enabled */ 861f27f152SAlex Elder struct list_head links; /* for ccu_list */ 871f27f152SAlex Elder struct device_node *node; 881f27f152SAlex Elder struct clk_onecell_data data; 891f27f152SAlex Elder const char *name; 901f27f152SAlex Elder u32 range; /* byte range of address space */ 911f27f152SAlex Elder }; 921f27f152SAlex Elder 931f27f152SAlex Elder /* 941f27f152SAlex Elder * Gating control and status is managed by a 32-bit gate register. 951f27f152SAlex Elder * 961f27f152SAlex Elder * There are several types of gating available: 971f27f152SAlex Elder * - (no gate) 981f27f152SAlex Elder * A clock with no gate is assumed to be always enabled. 991f27f152SAlex Elder * - hardware-only gating (auto-gating) 1001f27f152SAlex Elder * Enabling or disabling clocks with this type of gate is 1011f27f152SAlex Elder * managed automatically by the hardware. Such clocks can be 1021f27f152SAlex Elder * considered by the software to be enabled. The current status 1031f27f152SAlex Elder * of auto-gated clocks can be read from the gate status bit. 1041f27f152SAlex Elder * - software-only gating 1051f27f152SAlex Elder * Auto-gating is not available for this type of clock. 1061f27f152SAlex Elder * Instead, software manages whether it's enabled by setting or 1071f27f152SAlex Elder * clearing the enable bit. The current gate status of a gate 1081f27f152SAlex Elder * under software control can be read from the gate status bit. 1091f27f152SAlex Elder * To ensure a change to the gating status is complete, the 1101f27f152SAlex Elder * status bit can be polled to verify that the gate has entered 1111f27f152SAlex Elder * the desired state. 1121f27f152SAlex Elder * - selectable hardware or software gating 1131f27f152SAlex Elder * Gating for this type of clock can be configured to be either 1141f27f152SAlex Elder * under software or hardware control. Which type is in use is 1151f27f152SAlex Elder * determined by the hw_sw_sel bit of the gate register. 1161f27f152SAlex Elder */ 1171f27f152SAlex Elder struct bcm_clk_gate { 1181f27f152SAlex Elder u32 offset; /* gate register offset */ 1191f27f152SAlex Elder u32 status_bit; /* 0: gate is disabled; 0: gatge is enabled */ 1201f27f152SAlex Elder u32 en_bit; /* 0: disable; 1: enable */ 1211f27f152SAlex Elder u32 hw_sw_sel_bit; /* 0: hardware gating; 1: software gating */ 1221f27f152SAlex Elder u32 flags; /* BCM_CLK_GATE_FLAGS_* below */ 1231f27f152SAlex Elder }; 1241f27f152SAlex Elder 1251f27f152SAlex Elder /* 1261f27f152SAlex Elder * Gate flags: 1271f27f152SAlex Elder * HW means this gate can be auto-gated 1281f27f152SAlex Elder * SW means the state of this gate can be software controlled 1291f27f152SAlex Elder * NO_DISABLE means this gate is (only) enabled if under software control 1301f27f152SAlex Elder * SW_MANAGED means the status of this gate is under software control 1311f27f152SAlex Elder * ENABLED means this software-managed gate is *supposed* to be enabled 1321f27f152SAlex Elder */ 1331f27f152SAlex Elder #define BCM_CLK_GATE_FLAGS_EXISTS ((u32)1 << 0) /* Gate is valid */ 1341f27f152SAlex Elder #define BCM_CLK_GATE_FLAGS_HW ((u32)1 << 1) /* Can auto-gate */ 1351f27f152SAlex Elder #define BCM_CLK_GATE_FLAGS_SW ((u32)1 << 2) /* Software control */ 1361f27f152SAlex Elder #define BCM_CLK_GATE_FLAGS_NO_DISABLE ((u32)1 << 3) /* HW or enabled */ 1371f27f152SAlex Elder #define BCM_CLK_GATE_FLAGS_SW_MANAGED ((u32)1 << 4) /* SW now in control */ 1381f27f152SAlex Elder #define BCM_CLK_GATE_FLAGS_ENABLED ((u32)1 << 5) /* If SW_MANAGED */ 1391f27f152SAlex Elder 1401f27f152SAlex Elder /* 1411f27f152SAlex Elder * Gate initialization macros. 1421f27f152SAlex Elder * 1431f27f152SAlex Elder * Any gate initially under software control will be enabled. 1441f27f152SAlex Elder */ 1451f27f152SAlex Elder 1461f27f152SAlex Elder /* A hardware/software gate initially under software control */ 1471f27f152SAlex Elder #define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ 1481f27f152SAlex Elder { \ 1491f27f152SAlex Elder .offset = (_offset), \ 1501f27f152SAlex Elder .status_bit = (_status_bit), \ 1511f27f152SAlex Elder .en_bit = (_en_bit), \ 1521f27f152SAlex Elder .hw_sw_sel_bit = (_hw_sw_sel_bit), \ 1531f27f152SAlex Elder .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \ 1541f27f152SAlex Elder FLAG(GATE, SW_MANAGED)|FLAG(GATE, ENABLED)| \ 1551f27f152SAlex Elder FLAG(GATE, EXISTS), \ 1561f27f152SAlex Elder } 1571f27f152SAlex Elder 1581f27f152SAlex Elder /* A hardware/software gate initially under hardware control */ 1591f27f152SAlex Elder #define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ 1601f27f152SAlex Elder { \ 1611f27f152SAlex Elder .offset = (_offset), \ 1621f27f152SAlex Elder .status_bit = (_status_bit), \ 1631f27f152SAlex Elder .en_bit = (_en_bit), \ 1641f27f152SAlex Elder .hw_sw_sel_bit = (_hw_sw_sel_bit), \ 1651f27f152SAlex Elder .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \ 1661f27f152SAlex Elder FLAG(GATE, EXISTS), \ 1671f27f152SAlex Elder } 1681f27f152SAlex Elder 1691f27f152SAlex Elder /* A hardware-or-enabled gate (enabled if not under hardware control) */ 1701f27f152SAlex Elder #define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ 1711f27f152SAlex Elder { \ 1721f27f152SAlex Elder .offset = (_offset), \ 1731f27f152SAlex Elder .status_bit = (_status_bit), \ 1741f27f152SAlex Elder .en_bit = (_en_bit), \ 1751f27f152SAlex Elder .hw_sw_sel_bit = (_hw_sw_sel_bit), \ 1761f27f152SAlex Elder .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \ 1771f27f152SAlex Elder FLAG(GATE, NO_DISABLE)|FLAG(GATE, EXISTS), \ 1781f27f152SAlex Elder } 1791f27f152SAlex Elder 1801f27f152SAlex Elder /* A software-only gate */ 1811f27f152SAlex Elder #define SW_ONLY_GATE(_offset, _status_bit, _en_bit) \ 1821f27f152SAlex Elder { \ 1831f27f152SAlex Elder .offset = (_offset), \ 1841f27f152SAlex Elder .status_bit = (_status_bit), \ 1851f27f152SAlex Elder .en_bit = (_en_bit), \ 1861f27f152SAlex Elder .flags = FLAG(GATE, SW)|FLAG(GATE, SW_MANAGED)| \ 1871f27f152SAlex Elder FLAG(GATE, ENABLED)|FLAG(GATE, EXISTS), \ 1881f27f152SAlex Elder } 1891f27f152SAlex Elder 1901f27f152SAlex Elder /* A hardware-only gate */ 1911f27f152SAlex Elder #define HW_ONLY_GATE(_offset, _status_bit) \ 1921f27f152SAlex Elder { \ 1931f27f152SAlex Elder .offset = (_offset), \ 1941f27f152SAlex Elder .status_bit = (_status_bit), \ 1951f27f152SAlex Elder .flags = FLAG(GATE, HW)|FLAG(GATE, EXISTS), \ 1961f27f152SAlex Elder } 1971f27f152SAlex Elder 1981f27f152SAlex Elder /* 1991f27f152SAlex Elder * Each clock can have zero, one, or two dividers which change the 2001f27f152SAlex Elder * output rate of the clock. Each divider can be either fixed or 2011f27f152SAlex Elder * variable. If there are two dividers, they are the "pre-divider" 2021f27f152SAlex Elder * and the "regular" or "downstream" divider. If there is only one, 2031f27f152SAlex Elder * there is no pre-divider. 2041f27f152SAlex Elder * 2051f27f152SAlex Elder * A fixed divider is any non-zero (positive) value, and it 2061f27f152SAlex Elder * indicates how the input rate is affected by the divider. 2071f27f152SAlex Elder * 2081f27f152SAlex Elder * The value of a variable divider is maintained in a sub-field of a 2091f27f152SAlex Elder * 32-bit divider register. The position of the field in the 2101f27f152SAlex Elder * register is defined by its offset and width. The value recorded 2111f27f152SAlex Elder * in this field is always 1 less than the value it represents. 2121f27f152SAlex Elder * 2131f27f152SAlex Elder * In addition, a variable divider can indicate that some subset 2141f27f152SAlex Elder * of its bits represent a "fractional" part of the divider. Such 2151f27f152SAlex Elder * bits comprise the low-order portion of the divider field, and can 2161f27f152SAlex Elder * be viewed as representing the portion of the divider that lies to 2171f27f152SAlex Elder * the right of the decimal point. Most variable dividers have zero 2181f27f152SAlex Elder * fractional bits. Variable dividers with non-zero fraction width 2191f27f152SAlex Elder * still record a value 1 less than the value they represent; the 2201f27f152SAlex Elder * added 1 does *not* affect the low-order bit in this case, it 2211f27f152SAlex Elder * affects the bits above the fractional part only. (Often in this 2221f27f152SAlex Elder * code a divider field value is distinguished from the value it 2231f27f152SAlex Elder * represents by referring to the latter as a "divisor".) 2241f27f152SAlex Elder * 2251f27f152SAlex Elder * In order to avoid dealing with fractions, divider arithmetic is 2261f27f152SAlex Elder * performed using "scaled" values. A scaled value is one that's 2271f27f152SAlex Elder * been left-shifted by the fractional width of a divider. Dividing 2281f27f152SAlex Elder * a scaled value by a scaled divisor produces the desired quotient 2291f27f152SAlex Elder * without loss of precision and without any other special handling 2301f27f152SAlex Elder * for fractions. 2311f27f152SAlex Elder * 2321f27f152SAlex Elder * The recorded value of a variable divider can be modified. To 2331f27f152SAlex Elder * modify either divider (or both), a clock must be enabled (i.e., 2341f27f152SAlex Elder * using its gate). In addition, a trigger register (described 2351f27f152SAlex Elder * below) must be used to commit the change, and polled to verify 2361f27f152SAlex Elder * the change is complete. 2371f27f152SAlex Elder */ 2381f27f152SAlex Elder struct bcm_clk_div { 2391f27f152SAlex Elder union { 2401f27f152SAlex Elder struct { /* variable divider */ 2411f27f152SAlex Elder u32 offset; /* divider register offset */ 2421f27f152SAlex Elder u32 shift; /* field shift */ 2431f27f152SAlex Elder u32 width; /* field width */ 2441f27f152SAlex Elder u32 frac_width; /* field fraction width */ 2451f27f152SAlex Elder 2461f27f152SAlex Elder u64 scaled_div; /* scaled divider value */ 247e813d49dSAlex Elder } s; 2481f27f152SAlex Elder u32 fixed; /* non-zero fixed divider value */ 249e813d49dSAlex Elder } u; 2501f27f152SAlex Elder u32 flags; /* BCM_CLK_DIV_FLAGS_* below */ 2511f27f152SAlex Elder }; 2521f27f152SAlex Elder 2531f27f152SAlex Elder /* 2541f27f152SAlex Elder * Divider flags: 2551f27f152SAlex Elder * EXISTS means this divider exists 2561f27f152SAlex Elder * FIXED means it is a fixed-rate divider 2571f27f152SAlex Elder */ 2581f27f152SAlex Elder #define BCM_CLK_DIV_FLAGS_EXISTS ((u32)1 << 0) /* Divider is valid */ 2591f27f152SAlex Elder #define BCM_CLK_DIV_FLAGS_FIXED ((u32)1 << 1) /* Fixed-value */ 2601f27f152SAlex Elder 2611f27f152SAlex Elder /* Divider initialization macros */ 2621f27f152SAlex Elder 2631f27f152SAlex Elder /* A fixed (non-zero) divider */ 2641f27f152SAlex Elder #define FIXED_DIVIDER(_value) \ 2651f27f152SAlex Elder { \ 266e813d49dSAlex Elder .u.fixed = (_value), \ 2671f27f152SAlex Elder .flags = FLAG(DIV, EXISTS)|FLAG(DIV, FIXED), \ 2681f27f152SAlex Elder } 2691f27f152SAlex Elder 2701f27f152SAlex Elder /* A divider with an integral divisor */ 2711f27f152SAlex Elder #define DIVIDER(_offset, _shift, _width) \ 2721f27f152SAlex Elder { \ 273e813d49dSAlex Elder .u.s.offset = (_offset), \ 274e813d49dSAlex Elder .u.s.shift = (_shift), \ 275e813d49dSAlex Elder .u.s.width = (_width), \ 276e813d49dSAlex Elder .u.s.scaled_div = BAD_SCALED_DIV_VALUE, \ 2771f27f152SAlex Elder .flags = FLAG(DIV, EXISTS), \ 2781f27f152SAlex Elder } 2791f27f152SAlex Elder 2801f27f152SAlex Elder /* A divider whose divisor has an integer and fractional part */ 2811f27f152SAlex Elder #define FRAC_DIVIDER(_offset, _shift, _width, _frac_width) \ 2821f27f152SAlex Elder { \ 283e813d49dSAlex Elder .u.s.offset = (_offset), \ 284e813d49dSAlex Elder .u.s.shift = (_shift), \ 285e813d49dSAlex Elder .u.s.width = (_width), \ 286e813d49dSAlex Elder .u.s.frac_width = (_frac_width), \ 287e813d49dSAlex Elder .u.s.scaled_div = BAD_SCALED_DIV_VALUE, \ 2881f27f152SAlex Elder .flags = FLAG(DIV, EXISTS), \ 2891f27f152SAlex Elder } 2901f27f152SAlex Elder 2911f27f152SAlex Elder /* 2921f27f152SAlex Elder * Clocks may have multiple "parent" clocks. If there is more than 2931f27f152SAlex Elder * one, a selector must be specified to define which of the parent 2941f27f152SAlex Elder * clocks is currently in use. The selected clock is indicated in a 2951f27f152SAlex Elder * sub-field of a 32-bit selector register. The range of 2961f27f152SAlex Elder * representable selector values typically exceeds the number of 2971f27f152SAlex Elder * available parent clocks. Occasionally the reset value of a 2981f27f152SAlex Elder * selector field is explicitly set to a (specific) value that does 2991f27f152SAlex Elder * not correspond to a defined input clock. 3001f27f152SAlex Elder * 3011f27f152SAlex Elder * We register all known parent clocks with the common clock code 3021f27f152SAlex Elder * using a packed array (i.e., no empty slots) of (parent) clock 3031f27f152SAlex Elder * names, and refer to them later using indexes into that array. 3041f27f152SAlex Elder * We maintain an array of selector values indexed by common clock 3051f27f152SAlex Elder * index values in order to map between these common clock indexes 3061f27f152SAlex Elder * and the selector values used by the hardware. 3071f27f152SAlex Elder * 3081f27f152SAlex Elder * Like dividers, a selector can be modified, but to do so a clock 3091f27f152SAlex Elder * must be enabled, and a trigger must be used to commit the change. 3101f27f152SAlex Elder */ 3111f27f152SAlex Elder struct bcm_clk_sel { 3121f27f152SAlex Elder u32 offset; /* selector register offset */ 3131f27f152SAlex Elder u32 shift; /* field shift */ 3141f27f152SAlex Elder u32 width; /* field width */ 3151f27f152SAlex Elder 3161f27f152SAlex Elder u32 parent_count; /* number of entries in parent_sel[] */ 3171f27f152SAlex Elder u32 *parent_sel; /* array of parent selector values */ 3181f27f152SAlex Elder u8 clk_index; /* current selected index in parent_sel[] */ 3191f27f152SAlex Elder }; 3201f27f152SAlex Elder 3211f27f152SAlex Elder /* Selector initialization macro */ 3221f27f152SAlex Elder #define SELECTOR(_offset, _shift, _width) \ 3231f27f152SAlex Elder { \ 3241f27f152SAlex Elder .offset = (_offset), \ 3251f27f152SAlex Elder .shift = (_shift), \ 3261f27f152SAlex Elder .width = (_width), \ 3271f27f152SAlex Elder .clk_index = BAD_CLK_INDEX, \ 3281f27f152SAlex Elder } 3291f27f152SAlex Elder 3301f27f152SAlex Elder /* 3311f27f152SAlex Elder * Making changes to a variable divider or a selector for a clock 3321f27f152SAlex Elder * requires the use of a trigger. A trigger is defined by a single 3331f27f152SAlex Elder * bit within a register. To signal a change, a 1 is written into 3341f27f152SAlex Elder * that bit. To determine when the change has been completed, that 3351f27f152SAlex Elder * trigger bit is polled; the read value will be 1 while the change 3361f27f152SAlex Elder * is in progress, and 0 when it is complete. 3371f27f152SAlex Elder * 3381f27f152SAlex Elder * Occasionally a clock will have more than one trigger. In this 3391f27f152SAlex Elder * case, the "pre-trigger" will be used when changing a clock's 3401f27f152SAlex Elder * selector and/or its pre-divider. 3411f27f152SAlex Elder */ 3421f27f152SAlex Elder struct bcm_clk_trig { 3431f27f152SAlex Elder u32 offset; /* trigger register offset */ 3441f27f152SAlex Elder u32 bit; /* trigger bit */ 3451f27f152SAlex Elder u32 flags; /* BCM_CLK_TRIG_FLAGS_* below */ 3461f27f152SAlex Elder }; 3471f27f152SAlex Elder 3481f27f152SAlex Elder /* 3491f27f152SAlex Elder * Trigger flags: 3501f27f152SAlex Elder * EXISTS means this trigger exists 3511f27f152SAlex Elder */ 3521f27f152SAlex Elder #define BCM_CLK_TRIG_FLAGS_EXISTS ((u32)1 << 0) /* Trigger is valid */ 3531f27f152SAlex Elder 3541f27f152SAlex Elder /* Trigger initialization macro */ 3551f27f152SAlex Elder #define TRIGGER(_offset, _bit) \ 3561f27f152SAlex Elder { \ 3571f27f152SAlex Elder .offset = (_offset), \ 3581f27f152SAlex Elder .bit = (_bit), \ 3591f27f152SAlex Elder .flags = FLAG(TRIG, EXISTS), \ 3601f27f152SAlex Elder } 3611f27f152SAlex Elder 3621f27f152SAlex Elder struct peri_clk_data { 3631f27f152SAlex Elder struct bcm_clk_gate gate; 3641f27f152SAlex Elder struct bcm_clk_trig pre_trig; 3651f27f152SAlex Elder struct bcm_clk_div pre_div; 3661f27f152SAlex Elder struct bcm_clk_trig trig; 3671f27f152SAlex Elder struct bcm_clk_div div; 3681f27f152SAlex Elder struct bcm_clk_sel sel; 3691f27f152SAlex Elder const char *clocks[]; /* must be last; use CLOCKS() to declare */ 3701f27f152SAlex Elder }; 3711f27f152SAlex Elder #define CLOCKS(...) { __VA_ARGS__, NULL, } 3721f27f152SAlex Elder #define NO_CLOCKS { NULL, } /* Must use of no parent clocks */ 3731f27f152SAlex Elder 3741f27f152SAlex Elder struct kona_clk { 3751f27f152SAlex Elder struct clk_hw hw; 376e7563252SAlex Elder struct clk_init_data init_data; /* includes name of this clock */ 3771f27f152SAlex Elder struct ccu_data *ccu; /* ccu this clock is associated with */ 3781f27f152SAlex Elder enum bcm_clk_type type; 3791f27f152SAlex Elder union { 3801f27f152SAlex Elder void *data; 3811f27f152SAlex Elder struct peri_clk_data *peri; 382e813d49dSAlex Elder } u; 3831f27f152SAlex Elder }; 3841f27f152SAlex Elder #define to_kona_clk(_hw) \ 3851f27f152SAlex Elder container_of(_hw, struct kona_clk, hw) 3861f27f152SAlex Elder 3871f27f152SAlex Elder /* Exported globals */ 3881f27f152SAlex Elder 3891f27f152SAlex Elder extern struct clk_ops kona_peri_clk_ops; 3901f27f152SAlex Elder 3911f27f152SAlex Elder /* Help functions */ 3921f27f152SAlex Elder 3931f27f152SAlex Elder #define PERI_CLK_SETUP(clks, ccu, id, name) \ 3941f27f152SAlex Elder clks[id] = kona_clk_setup(ccu, #name, bcm_clk_peri, &name ## _data) 3951f27f152SAlex Elder 3961f27f152SAlex Elder /* Externally visible functions */ 3971f27f152SAlex Elder 3981f27f152SAlex Elder extern u64 do_div_round_closest(u64 dividend, unsigned long divisor); 3991f27f152SAlex Elder extern u64 scaled_div_max(struct bcm_clk_div *div); 4001f27f152SAlex Elder extern u64 scaled_div_build(struct bcm_clk_div *div, u32 div_value, 4011f27f152SAlex Elder u32 billionths); 4021f27f152SAlex Elder 4031f27f152SAlex Elder extern struct clk *kona_clk_setup(struct ccu_data *ccu, const char *name, 4041f27f152SAlex Elder enum bcm_clk_type type, void *data); 4051f27f152SAlex Elder extern void __init kona_dt_ccu_setup(struct device_node *node, 4061f27f152SAlex Elder int (*ccu_clks_setup)(struct ccu_data *)); 4071f27f152SAlex Elder extern bool __init kona_ccu_init(struct ccu_data *ccu); 4081f27f152SAlex Elder 4091f27f152SAlex Elder #endif /* _CLK_KONA_H */ 410