1 /* 2 * Copyright (C) 2014 Broadcom Corporation 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation version 2. 7 * 8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 9 * kind, whether express or implied; without even the implied warranty 10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/err.h> 16 #include <linux/clk-provider.h> 17 #include <linux/io.h> 18 #include <linux/of.h> 19 #include <linux/clkdev.h> 20 #include <linux/of_address.h> 21 #include <linux/delay.h> 22 23 #include "clk-iproc.h" 24 25 #define PLL_VCO_HIGH_SHIFT 19 26 #define PLL_VCO_LOW_SHIFT 30 27 28 /* 29 * PLL MACRO_SELECT modes 0 to 5 choose pre-calculated PLL output frequencies 30 * from a look-up table. Mode 7 allows user to manipulate PLL clock dividers 31 */ 32 #define PLL_USER_MODE 7 33 34 /* number of delay loops waiting for PLL to lock */ 35 #define LOCK_DELAY 100 36 37 /* number of VCO frequency bands */ 38 #define NUM_FREQ_BANDS 8 39 40 #define NUM_KP_BANDS 3 41 enum kp_band { 42 KP_BAND_MID = 0, 43 KP_BAND_HIGH, 44 KP_BAND_HIGH_HIGH 45 }; 46 47 static const unsigned int kp_table[NUM_KP_BANDS][NUM_FREQ_BANDS] = { 48 { 5, 6, 6, 7, 7, 8, 9, 10 }, 49 { 4, 4, 5, 5, 6, 7, 8, 9 }, 50 { 4, 5, 5, 6, 7, 8, 9, 10 }, 51 }; 52 53 static const unsigned long ref_freq_table[NUM_FREQ_BANDS][2] = { 54 { 10000000, 12500000 }, 55 { 12500000, 15000000 }, 56 { 15000000, 20000000 }, 57 { 20000000, 25000000 }, 58 { 25000000, 50000000 }, 59 { 50000000, 75000000 }, 60 { 75000000, 100000000 }, 61 { 100000000, 125000000 }, 62 }; 63 64 enum vco_freq_range { 65 VCO_LOW = 700000000U, 66 VCO_MID = 1200000000U, 67 VCO_HIGH = 2200000000U, 68 VCO_HIGH_HIGH = 3100000000U, 69 VCO_MAX = 4000000000U, 70 }; 71 72 struct iproc_pll; 73 74 struct iproc_clk { 75 struct clk_hw hw; 76 const char *name; 77 struct iproc_pll *pll; 78 unsigned long rate; 79 const struct iproc_clk_ctrl *ctrl; 80 }; 81 82 struct iproc_pll { 83 void __iomem *status_base; 84 void __iomem *control_base; 85 void __iomem *pwr_base; 86 void __iomem *asiu_base; 87 88 const struct iproc_pll_ctrl *ctrl; 89 const struct iproc_pll_vco_param *vco_param; 90 unsigned int num_vco_entries; 91 92 struct clk_onecell_data clk_data; 93 struct iproc_clk *clks; 94 }; 95 96 #define to_iproc_clk(hw) container_of(hw, struct iproc_clk, hw) 97 98 /* 99 * Based on the target frequency, find a match from the VCO frequency parameter 100 * table and return its index 101 */ 102 static int pll_get_rate_index(struct iproc_pll *pll, unsigned int target_rate) 103 { 104 int i; 105 106 for (i = 0; i < pll->num_vco_entries; i++) 107 if (target_rate == pll->vco_param[i].rate) 108 break; 109 110 if (i >= pll->num_vco_entries) 111 return -EINVAL; 112 113 return i; 114 } 115 116 static int get_kp(unsigned long ref_freq, enum kp_band kp_index) 117 { 118 int i; 119 120 if (ref_freq < ref_freq_table[0][0]) 121 return -EINVAL; 122 123 for (i = 0; i < NUM_FREQ_BANDS; i++) { 124 if (ref_freq >= ref_freq_table[i][0] && 125 ref_freq < ref_freq_table[i][1]) 126 return kp_table[kp_index][i]; 127 } 128 return -EINVAL; 129 } 130 131 static int pll_wait_for_lock(struct iproc_pll *pll) 132 { 133 int i; 134 const struct iproc_pll_ctrl *ctrl = pll->ctrl; 135 136 for (i = 0; i < LOCK_DELAY; i++) { 137 u32 val = readl(pll->status_base + ctrl->status.offset); 138 139 if (val & (1 << ctrl->status.shift)) 140 return 0; 141 udelay(10); 142 } 143 144 return -EIO; 145 } 146 147 static void iproc_pll_write(const struct iproc_pll *pll, void __iomem *base, 148 const u32 offset, u32 val) 149 { 150 const struct iproc_pll_ctrl *ctrl = pll->ctrl; 151 152 writel(val, base + offset); 153 154 if (unlikely(ctrl->flags & IPROC_CLK_NEEDS_READ_BACK && 155 (base == pll->status_base || base == pll->control_base))) 156 val = readl(base + offset); 157 } 158 159 static void __pll_disable(struct iproc_pll *pll) 160 { 161 const struct iproc_pll_ctrl *ctrl = pll->ctrl; 162 u32 val; 163 164 if (ctrl->flags & IPROC_CLK_PLL_ASIU) { 165 val = readl(pll->asiu_base + ctrl->asiu.offset); 166 val &= ~(1 << ctrl->asiu.en_shift); 167 iproc_pll_write(pll, pll->asiu_base, ctrl->asiu.offset, val); 168 } 169 170 if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) { 171 val = readl(pll->control_base + ctrl->aon.offset); 172 val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift; 173 iproc_pll_write(pll, pll->control_base, ctrl->aon.offset, val); 174 } 175 176 if (pll->pwr_base) { 177 /* latch input value so core power can be shut down */ 178 val = readl(pll->pwr_base + ctrl->aon.offset); 179 val |= 1 << ctrl->aon.iso_shift; 180 iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val); 181 182 /* power down the core */ 183 val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); 184 iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val); 185 } 186 } 187 188 static int __pll_enable(struct iproc_pll *pll) 189 { 190 const struct iproc_pll_ctrl *ctrl = pll->ctrl; 191 u32 val; 192 193 if (ctrl->flags & IPROC_CLK_EMBED_PWRCTRL) { 194 val = readl(pll->control_base + ctrl->aon.offset); 195 val &= ~(bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift); 196 iproc_pll_write(pll, pll->control_base, ctrl->aon.offset, val); 197 } 198 199 if (pll->pwr_base) { 200 /* power up the PLL and make sure it's not latched */ 201 val = readl(pll->pwr_base + ctrl->aon.offset); 202 val |= bit_mask(ctrl->aon.pwr_width) << ctrl->aon.pwr_shift; 203 val &= ~(1 << ctrl->aon.iso_shift); 204 iproc_pll_write(pll, pll->pwr_base, ctrl->aon.offset, val); 205 } 206 207 /* certain PLLs also need to be ungated from the ASIU top level */ 208 if (ctrl->flags & IPROC_CLK_PLL_ASIU) { 209 val = readl(pll->asiu_base + ctrl->asiu.offset); 210 val |= (1 << ctrl->asiu.en_shift); 211 iproc_pll_write(pll, pll->asiu_base, ctrl->asiu.offset, val); 212 } 213 214 return 0; 215 } 216 217 static void __pll_put_in_reset(struct iproc_pll *pll) 218 { 219 u32 val; 220 const struct iproc_pll_ctrl *ctrl = pll->ctrl; 221 const struct iproc_pll_reset_ctrl *reset = &ctrl->reset; 222 223 val = readl(pll->control_base + reset->offset); 224 if (ctrl->flags & IPROC_CLK_PLL_RESET_ACTIVE_LOW) 225 val |= BIT(reset->reset_shift) | BIT(reset->p_reset_shift); 226 else 227 val &= ~(BIT(reset->reset_shift) | BIT(reset->p_reset_shift)); 228 iproc_pll_write(pll, pll->control_base, reset->offset, val); 229 } 230 231 static void __pll_bring_out_reset(struct iproc_pll *pll, unsigned int kp, 232 unsigned int ka, unsigned int ki) 233 { 234 u32 val; 235 const struct iproc_pll_ctrl *ctrl = pll->ctrl; 236 const struct iproc_pll_reset_ctrl *reset = &ctrl->reset; 237 const struct iproc_pll_dig_filter_ctrl *dig_filter = &ctrl->dig_filter; 238 239 val = readl(pll->control_base + dig_filter->offset); 240 val &= ~(bit_mask(dig_filter->ki_width) << dig_filter->ki_shift | 241 bit_mask(dig_filter->kp_width) << dig_filter->kp_shift | 242 bit_mask(dig_filter->ka_width) << dig_filter->ka_shift); 243 val |= ki << dig_filter->ki_shift | kp << dig_filter->kp_shift | 244 ka << dig_filter->ka_shift; 245 iproc_pll_write(pll, pll->control_base, dig_filter->offset, val); 246 247 val = readl(pll->control_base + reset->offset); 248 if (ctrl->flags & IPROC_CLK_PLL_RESET_ACTIVE_LOW) 249 val &= ~(BIT(reset->reset_shift) | BIT(reset->p_reset_shift)); 250 else 251 val |= BIT(reset->reset_shift) | BIT(reset->p_reset_shift); 252 iproc_pll_write(pll, pll->control_base, reset->offset, val); 253 } 254 255 static int pll_set_rate(struct iproc_clk *clk, unsigned int rate_index, 256 unsigned long parent_rate) 257 { 258 struct iproc_pll *pll = clk->pll; 259 const struct iproc_pll_vco_param *vco = &pll->vco_param[rate_index]; 260 const struct iproc_pll_ctrl *ctrl = pll->ctrl; 261 int ka = 0, ki, kp, ret; 262 unsigned long rate = vco->rate; 263 u32 val; 264 enum kp_band kp_index; 265 unsigned long ref_freq; 266 267 /* 268 * reference frequency = parent frequency / PDIV 269 * If PDIV = 0, then it becomes a multiplier (x2) 270 */ 271 if (vco->pdiv == 0) 272 ref_freq = parent_rate * 2; 273 else 274 ref_freq = parent_rate / vco->pdiv; 275 276 /* determine Ki and Kp index based on target VCO frequency */ 277 if (rate >= VCO_LOW && rate < VCO_HIGH) { 278 ki = 4; 279 kp_index = KP_BAND_MID; 280 } else if (rate >= VCO_HIGH && rate && rate < VCO_HIGH_HIGH) { 281 ki = 3; 282 kp_index = KP_BAND_HIGH; 283 } else if (rate >= VCO_HIGH_HIGH && rate < VCO_MAX) { 284 ki = 3; 285 kp_index = KP_BAND_HIGH_HIGH; 286 } else { 287 pr_err("%s: pll: %s has invalid rate: %lu\n", __func__, 288 clk->name, rate); 289 return -EINVAL; 290 } 291 292 kp = get_kp(ref_freq, kp_index); 293 if (kp < 0) { 294 pr_err("%s: pll: %s has invalid kp\n", __func__, clk->name); 295 return kp; 296 } 297 298 ret = __pll_enable(pll); 299 if (ret) { 300 pr_err("%s: pll: %s fails to enable\n", __func__, clk->name); 301 return ret; 302 } 303 304 /* put PLL in reset */ 305 __pll_put_in_reset(pll); 306 307 /* set PLL in user mode before modifying PLL controls */ 308 if (ctrl->flags & IPROC_CLK_PLL_USER_MODE_ON) { 309 val = readl(pll->control_base + ctrl->macro_mode.offset); 310 val &= ~(bit_mask(ctrl->macro_mode.width) << 311 ctrl->macro_mode.shift); 312 val |= PLL_USER_MODE << ctrl->macro_mode.shift; 313 iproc_pll_write(pll, pll->control_base, 314 ctrl->macro_mode.offset, val); 315 } 316 317 iproc_pll_write(pll, pll->control_base, ctrl->vco_ctrl.u_offset, 0); 318 319 val = readl(pll->control_base + ctrl->vco_ctrl.l_offset); 320 321 if (rate >= VCO_LOW && rate < VCO_MID) 322 val |= (1 << PLL_VCO_LOW_SHIFT); 323 324 if (rate < VCO_HIGH) 325 val &= ~(1 << PLL_VCO_HIGH_SHIFT); 326 else 327 val |= (1 << PLL_VCO_HIGH_SHIFT); 328 329 iproc_pll_write(pll, pll->control_base, ctrl->vco_ctrl.l_offset, val); 330 331 /* program integer part of NDIV */ 332 val = readl(pll->control_base + ctrl->ndiv_int.offset); 333 val &= ~(bit_mask(ctrl->ndiv_int.width) << ctrl->ndiv_int.shift); 334 val |= vco->ndiv_int << ctrl->ndiv_int.shift; 335 iproc_pll_write(pll, pll->control_base, ctrl->ndiv_int.offset, val); 336 337 /* program fractional part of NDIV */ 338 if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) { 339 val = readl(pll->control_base + ctrl->ndiv_frac.offset); 340 val &= ~(bit_mask(ctrl->ndiv_frac.width) << 341 ctrl->ndiv_frac.shift); 342 val |= vco->ndiv_frac << ctrl->ndiv_frac.shift; 343 iproc_pll_write(pll, pll->control_base, ctrl->ndiv_frac.offset, 344 val); 345 } 346 347 /* program PDIV */ 348 val = readl(pll->control_base + ctrl->pdiv.offset); 349 val &= ~(bit_mask(ctrl->pdiv.width) << ctrl->pdiv.shift); 350 val |= vco->pdiv << ctrl->pdiv.shift; 351 iproc_pll_write(pll, pll->control_base, ctrl->pdiv.offset, val); 352 353 __pll_bring_out_reset(pll, kp, ka, ki); 354 355 ret = pll_wait_for_lock(pll); 356 if (ret < 0) { 357 pr_err("%s: pll: %s failed to lock\n", __func__, clk->name); 358 return ret; 359 } 360 361 return 0; 362 } 363 364 static int iproc_pll_enable(struct clk_hw *hw) 365 { 366 struct iproc_clk *clk = to_iproc_clk(hw); 367 struct iproc_pll *pll = clk->pll; 368 369 return __pll_enable(pll); 370 } 371 372 static void iproc_pll_disable(struct clk_hw *hw) 373 { 374 struct iproc_clk *clk = to_iproc_clk(hw); 375 struct iproc_pll *pll = clk->pll; 376 const struct iproc_pll_ctrl *ctrl = pll->ctrl; 377 378 if (ctrl->flags & IPROC_CLK_AON) 379 return; 380 381 __pll_disable(pll); 382 } 383 384 static unsigned long iproc_pll_recalc_rate(struct clk_hw *hw, 385 unsigned long parent_rate) 386 { 387 struct iproc_clk *clk = to_iproc_clk(hw); 388 struct iproc_pll *pll = clk->pll; 389 const struct iproc_pll_ctrl *ctrl = pll->ctrl; 390 u32 val; 391 u64 ndiv, ndiv_int, ndiv_frac; 392 unsigned int pdiv; 393 394 if (parent_rate == 0) 395 return 0; 396 397 /* PLL needs to be locked */ 398 val = readl(pll->status_base + ctrl->status.offset); 399 if ((val & (1 << ctrl->status.shift)) == 0) { 400 clk->rate = 0; 401 return 0; 402 } 403 404 /* 405 * PLL output frequency = 406 * 407 * ((ndiv_int + ndiv_frac / 2^20) * (parent clock rate / pdiv) 408 */ 409 val = readl(pll->control_base + ctrl->ndiv_int.offset); 410 ndiv_int = (val >> ctrl->ndiv_int.shift) & 411 bit_mask(ctrl->ndiv_int.width); 412 ndiv = ndiv_int << 20; 413 414 if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) { 415 val = readl(pll->control_base + ctrl->ndiv_frac.offset); 416 ndiv_frac = (val >> ctrl->ndiv_frac.shift) & 417 bit_mask(ctrl->ndiv_frac.width); 418 ndiv += ndiv_frac; 419 } 420 421 val = readl(pll->control_base + ctrl->pdiv.offset); 422 pdiv = (val >> ctrl->pdiv.shift) & bit_mask(ctrl->pdiv.width); 423 424 clk->rate = (ndiv * parent_rate) >> 20; 425 426 if (pdiv == 0) 427 clk->rate *= 2; 428 else 429 clk->rate /= pdiv; 430 431 return clk->rate; 432 } 433 434 static long iproc_pll_round_rate(struct clk_hw *hw, unsigned long rate, 435 unsigned long *parent_rate) 436 { 437 unsigned i; 438 struct iproc_clk *clk = to_iproc_clk(hw); 439 struct iproc_pll *pll = clk->pll; 440 441 if (rate == 0 || *parent_rate == 0 || !pll->vco_param) 442 return -EINVAL; 443 444 for (i = 0; i < pll->num_vco_entries; i++) { 445 if (rate <= pll->vco_param[i].rate) 446 break; 447 } 448 449 if (i == pll->num_vco_entries) 450 i--; 451 452 return pll->vco_param[i].rate; 453 } 454 455 static int iproc_pll_set_rate(struct clk_hw *hw, unsigned long rate, 456 unsigned long parent_rate) 457 { 458 struct iproc_clk *clk = to_iproc_clk(hw); 459 struct iproc_pll *pll = clk->pll; 460 int rate_index, ret; 461 462 rate_index = pll_get_rate_index(pll, rate); 463 if (rate_index < 0) 464 return rate_index; 465 466 ret = pll_set_rate(clk, rate_index, parent_rate); 467 return ret; 468 } 469 470 static const struct clk_ops iproc_pll_ops = { 471 .enable = iproc_pll_enable, 472 .disable = iproc_pll_disable, 473 .recalc_rate = iproc_pll_recalc_rate, 474 .round_rate = iproc_pll_round_rate, 475 .set_rate = iproc_pll_set_rate, 476 }; 477 478 static int iproc_clk_enable(struct clk_hw *hw) 479 { 480 struct iproc_clk *clk = to_iproc_clk(hw); 481 const struct iproc_clk_ctrl *ctrl = clk->ctrl; 482 struct iproc_pll *pll = clk->pll; 483 u32 val; 484 485 /* channel enable is active low */ 486 val = readl(pll->control_base + ctrl->enable.offset); 487 val &= ~(1 << ctrl->enable.enable_shift); 488 iproc_pll_write(pll, pll->control_base, ctrl->enable.offset, val); 489 490 /* also make sure channel is not held */ 491 val = readl(pll->control_base + ctrl->enable.offset); 492 val &= ~(1 << ctrl->enable.hold_shift); 493 iproc_pll_write(pll, pll->control_base, ctrl->enable.offset, val); 494 495 return 0; 496 } 497 498 static void iproc_clk_disable(struct clk_hw *hw) 499 { 500 struct iproc_clk *clk = to_iproc_clk(hw); 501 const struct iproc_clk_ctrl *ctrl = clk->ctrl; 502 struct iproc_pll *pll = clk->pll; 503 u32 val; 504 505 if (ctrl->flags & IPROC_CLK_AON) 506 return; 507 508 val = readl(pll->control_base + ctrl->enable.offset); 509 val |= 1 << ctrl->enable.enable_shift; 510 iproc_pll_write(pll, pll->control_base, ctrl->enable.offset, val); 511 } 512 513 static unsigned long iproc_clk_recalc_rate(struct clk_hw *hw, 514 unsigned long parent_rate) 515 { 516 struct iproc_clk *clk = to_iproc_clk(hw); 517 const struct iproc_clk_ctrl *ctrl = clk->ctrl; 518 struct iproc_pll *pll = clk->pll; 519 u32 val; 520 unsigned int mdiv; 521 522 if (parent_rate == 0) 523 return 0; 524 525 val = readl(pll->control_base + ctrl->mdiv.offset); 526 mdiv = (val >> ctrl->mdiv.shift) & bit_mask(ctrl->mdiv.width); 527 if (mdiv == 0) 528 mdiv = 256; 529 530 if (ctrl->flags & IPROC_CLK_MCLK_DIV_BY_2) 531 clk->rate = parent_rate / (mdiv * 2); 532 else 533 clk->rate = parent_rate / mdiv; 534 535 return clk->rate; 536 } 537 538 static long iproc_clk_round_rate(struct clk_hw *hw, unsigned long rate, 539 unsigned long *parent_rate) 540 { 541 unsigned int div; 542 543 if (rate == 0 || *parent_rate == 0) 544 return -EINVAL; 545 546 if (rate == *parent_rate) 547 return *parent_rate; 548 549 div = DIV_ROUND_UP(*parent_rate, rate); 550 if (div < 2) 551 return *parent_rate; 552 553 if (div > 256) 554 div = 256; 555 556 return *parent_rate / div; 557 } 558 559 static int iproc_clk_set_rate(struct clk_hw *hw, unsigned long rate, 560 unsigned long parent_rate) 561 { 562 struct iproc_clk *clk = to_iproc_clk(hw); 563 const struct iproc_clk_ctrl *ctrl = clk->ctrl; 564 struct iproc_pll *pll = clk->pll; 565 u32 val; 566 unsigned int div; 567 568 if (rate == 0 || parent_rate == 0) 569 return -EINVAL; 570 571 if (ctrl->flags & IPROC_CLK_MCLK_DIV_BY_2) 572 div = DIV_ROUND_UP(parent_rate, rate * 2); 573 else 574 div = DIV_ROUND_UP(parent_rate, rate); 575 if (div > 256) 576 return -EINVAL; 577 578 val = readl(pll->control_base + ctrl->mdiv.offset); 579 if (div == 256) { 580 val &= ~(bit_mask(ctrl->mdiv.width) << ctrl->mdiv.shift); 581 } else { 582 val &= ~(bit_mask(ctrl->mdiv.width) << ctrl->mdiv.shift); 583 val |= div << ctrl->mdiv.shift; 584 } 585 iproc_pll_write(pll, pll->control_base, ctrl->mdiv.offset, val); 586 if (ctrl->flags & IPROC_CLK_MCLK_DIV_BY_2) 587 clk->rate = parent_rate / (div * 2); 588 else 589 clk->rate = parent_rate / div; 590 591 return 0; 592 } 593 594 static const struct clk_ops iproc_clk_ops = { 595 .enable = iproc_clk_enable, 596 .disable = iproc_clk_disable, 597 .recalc_rate = iproc_clk_recalc_rate, 598 .round_rate = iproc_clk_round_rate, 599 .set_rate = iproc_clk_set_rate, 600 }; 601 602 /** 603 * Some PLLs require the PLL SW override bit to be set before changes can be 604 * applied to the PLL 605 */ 606 static void iproc_pll_sw_cfg(struct iproc_pll *pll) 607 { 608 const struct iproc_pll_ctrl *ctrl = pll->ctrl; 609 610 if (ctrl->flags & IPROC_CLK_PLL_NEEDS_SW_CFG) { 611 u32 val; 612 613 val = readl(pll->control_base + ctrl->sw_ctrl.offset); 614 val |= BIT(ctrl->sw_ctrl.shift); 615 iproc_pll_write(pll, pll->control_base, ctrl->sw_ctrl.offset, 616 val); 617 } 618 } 619 620 void __init iproc_pll_clk_setup(struct device_node *node, 621 const struct iproc_pll_ctrl *pll_ctrl, 622 const struct iproc_pll_vco_param *vco, 623 unsigned int num_vco_entries, 624 const struct iproc_clk_ctrl *clk_ctrl, 625 unsigned int num_clks) 626 { 627 int i, ret; 628 struct clk *clk; 629 struct iproc_pll *pll; 630 struct iproc_clk *iclk; 631 struct clk_init_data init; 632 const char *parent_name; 633 634 if (WARN_ON(!pll_ctrl) || WARN_ON(!clk_ctrl)) 635 return; 636 637 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 638 if (WARN_ON(!pll)) 639 return; 640 641 pll->clk_data.clk_num = num_clks; 642 pll->clk_data.clks = kcalloc(num_clks, sizeof(*pll->clk_data.clks), 643 GFP_KERNEL); 644 if (WARN_ON(!pll->clk_data.clks)) 645 goto err_clk_data; 646 647 pll->clks = kcalloc(num_clks, sizeof(*pll->clks), GFP_KERNEL); 648 if (WARN_ON(!pll->clks)) 649 goto err_clks; 650 651 pll->control_base = of_iomap(node, 0); 652 if (WARN_ON(!pll->control_base)) 653 goto err_pll_iomap; 654 655 /* Some SoCs do not require the pwr_base, thus failing is not fatal */ 656 pll->pwr_base = of_iomap(node, 1); 657 658 /* some PLLs require gating control at the top ASIU level */ 659 if (pll_ctrl->flags & IPROC_CLK_PLL_ASIU) { 660 pll->asiu_base = of_iomap(node, 2); 661 if (WARN_ON(!pll->asiu_base)) 662 goto err_asiu_iomap; 663 } 664 665 if (pll_ctrl->flags & IPROC_CLK_PLL_SPLIT_STAT_CTRL) { 666 /* Some SoCs have a split status/control. If this does not 667 * exist, assume they are unified. 668 */ 669 pll->status_base = of_iomap(node, 2); 670 if (!pll->status_base) 671 goto err_status_iomap; 672 } else 673 pll->status_base = pll->control_base; 674 675 /* initialize and register the PLL itself */ 676 pll->ctrl = pll_ctrl; 677 678 iclk = &pll->clks[0]; 679 iclk->pll = pll; 680 iclk->name = node->name; 681 682 init.name = node->name; 683 init.ops = &iproc_pll_ops; 684 init.flags = 0; 685 parent_name = of_clk_get_parent_name(node, 0); 686 init.parent_names = (parent_name ? &parent_name : NULL); 687 init.num_parents = (parent_name ? 1 : 0); 688 iclk->hw.init = &init; 689 690 if (vco) { 691 pll->num_vco_entries = num_vco_entries; 692 pll->vco_param = vco; 693 } 694 695 iproc_pll_sw_cfg(pll); 696 697 clk = clk_register(NULL, &iclk->hw); 698 if (WARN_ON(IS_ERR(clk))) 699 goto err_pll_register; 700 701 pll->clk_data.clks[0] = clk; 702 703 /* now initialize and register all leaf clocks */ 704 for (i = 1; i < num_clks; i++) { 705 const char *clk_name; 706 707 memset(&init, 0, sizeof(init)); 708 parent_name = node->name; 709 710 ret = of_property_read_string_index(node, "clock-output-names", 711 i, &clk_name); 712 if (WARN_ON(ret)) 713 goto err_clk_register; 714 715 iclk = &pll->clks[i]; 716 iclk->name = clk_name; 717 iclk->pll = pll; 718 iclk->ctrl = &clk_ctrl[i]; 719 720 init.name = clk_name; 721 init.ops = &iproc_clk_ops; 722 init.flags = 0; 723 init.parent_names = (parent_name ? &parent_name : NULL); 724 init.num_parents = (parent_name ? 1 : 0); 725 iclk->hw.init = &init; 726 727 clk = clk_register(NULL, &iclk->hw); 728 if (WARN_ON(IS_ERR(clk))) 729 goto err_clk_register; 730 731 pll->clk_data.clks[i] = clk; 732 } 733 734 ret = of_clk_add_provider(node, of_clk_src_onecell_get, &pll->clk_data); 735 if (WARN_ON(ret)) 736 goto err_clk_register; 737 738 return; 739 740 err_clk_register: 741 for (i = 0; i < num_clks; i++) 742 clk_unregister(pll->clk_data.clks[i]); 743 744 err_pll_register: 745 if (pll->status_base != pll->control_base) 746 iounmap(pll->status_base); 747 748 err_status_iomap: 749 if (pll->asiu_base) 750 iounmap(pll->asiu_base); 751 752 err_asiu_iomap: 753 if (pll->pwr_base) 754 iounmap(pll->pwr_base); 755 756 iounmap(pll->control_base); 757 758 err_pll_iomap: 759 kfree(pll->clks); 760 761 err_clks: 762 kfree(pll->clk_data.clks); 763 764 err_clk_data: 765 kfree(pll); 766 } 767