161ca7b0cSRay Jui /* 261ca7b0cSRay Jui * Copyright (C) 2014 Broadcom Corporation 361ca7b0cSRay Jui * 461ca7b0cSRay Jui * This program is free software; you can redistribute it and/or 561ca7b0cSRay Jui * modify it under the terms of the GNU General Public License as 661ca7b0cSRay Jui * published by the Free Software Foundation version 2. 761ca7b0cSRay Jui * 861ca7b0cSRay Jui * This program is distributed "as is" WITHOUT ANY WARRANTY of any 961ca7b0cSRay Jui * kind, whether express or implied; without even the implied warranty 1061ca7b0cSRay Jui * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1161ca7b0cSRay Jui * GNU General Public License for more details. 1261ca7b0cSRay Jui */ 1361ca7b0cSRay Jui 1461ca7b0cSRay Jui #include <linux/kernel.h> 1561ca7b0cSRay Jui #include <linux/err.h> 1661ca7b0cSRay Jui #include <linux/clk-provider.h> 1761ca7b0cSRay Jui #include <linux/io.h> 1861ca7b0cSRay Jui #include <linux/of.h> 1961ca7b0cSRay Jui #include <linux/clkdev.h> 2061ca7b0cSRay Jui #include <linux/of_address.h> 2161ca7b0cSRay Jui #include <linux/delay.h> 2261ca7b0cSRay Jui 2361ca7b0cSRay Jui #include <dt-bindings/clock/bcm-cygnus.h> 2461ca7b0cSRay Jui #include "clk-iproc.h" 2561ca7b0cSRay Jui 262dfc8a27SJon Mason #define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, } 2761ca7b0cSRay Jui 282dfc8a27SJon Mason #define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \ 2961ca7b0cSRay Jui .pwr_shift = ps, .iso_shift = is } 3061ca7b0cSRay Jui 312dfc8a27SJon Mason #define SW_CTRL_VAL(o, s) { .offset = o, .shift = s, } 3261ca7b0cSRay Jui 332dfc8a27SJon Mason #define ASIU_DIV_VAL(o, es, hs, hw, ls, lw) \ 3461ca7b0cSRay Jui { .offset = o, .en_shift = es, .high_shift = hs, \ 3561ca7b0cSRay Jui .high_width = hw, .low_shift = ls, .low_width = lw } 3661ca7b0cSRay Jui 37f713c6bfSJon Mason #define RESET_VAL(o, rs, prs) { .offset = o, .reset_shift = rs, \ 38f713c6bfSJon Mason .p_reset_shift = prs } 39f713c6bfSJon Mason 40f713c6bfSJon Mason #define DF_VAL(o, kis, kiw, kps, kpw, kas, kaw) { .offset = o, .ki_shift = kis,\ 4161ca7b0cSRay Jui .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \ 4261ca7b0cSRay Jui .ka_width = kaw } 4361ca7b0cSRay Jui 442dfc8a27SJon Mason #define VCO_CTRL_VAL(uo, lo) { .u_offset = uo, .l_offset = lo } 4561ca7b0cSRay Jui 462dfc8a27SJon Mason #define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \ 4761ca7b0cSRay Jui .hold_shift = hs, .bypass_shift = bs } 4861ca7b0cSRay Jui 492dfc8a27SJon Mason #define ASIU_GATE_VAL(o, es) { .offset = o, .en_shift = es } 5061ca7b0cSRay Jui 5161ca7b0cSRay Jui static void __init cygnus_armpll_init(struct device_node *node) 5261ca7b0cSRay Jui { 5361ca7b0cSRay Jui iproc_armpll_setup(node); 5461ca7b0cSRay Jui } 5561ca7b0cSRay Jui CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll", cygnus_armpll_init); 5661ca7b0cSRay Jui 5761ca7b0cSRay Jui static const struct iproc_pll_ctrl genpll = { 5861ca7b0cSRay Jui .flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC | 5961ca7b0cSRay Jui IPROC_CLK_PLL_NEEDS_SW_CFG, 602dfc8a27SJon Mason .aon = AON_VAL(0x0, 2, 1, 0), 61f713c6bfSJon Mason .reset = RESET_VAL(0x0, 11, 10), 62f713c6bfSJon Mason .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3), 632dfc8a27SJon Mason .sw_ctrl = SW_CTRL_VAL(0x10, 31), 642dfc8a27SJon Mason .ndiv_int = REG_VAL(0x10, 20, 10), 652dfc8a27SJon Mason .ndiv_frac = REG_VAL(0x10, 0, 20), 662dfc8a27SJon Mason .pdiv = REG_VAL(0x14, 0, 4), 672dfc8a27SJon Mason .vco_ctrl = VCO_CTRL_VAL(0x18, 0x1c), 682dfc8a27SJon Mason .status = REG_VAL(0x28, 12, 1), 6961ca7b0cSRay Jui }; 7061ca7b0cSRay Jui 7161ca7b0cSRay Jui static const struct iproc_clk_ctrl genpll_clk[] = { 7261ca7b0cSRay Jui [BCM_CYGNUS_GENPLL_AXI21_CLK] = { 7361ca7b0cSRay Jui .channel = BCM_CYGNUS_GENPLL_AXI21_CLK, 7461ca7b0cSRay Jui .flags = IPROC_CLK_AON, 752dfc8a27SJon Mason .enable = ENABLE_VAL(0x4, 6, 0, 12), 762dfc8a27SJon Mason .mdiv = REG_VAL(0x20, 0, 8), 7761ca7b0cSRay Jui }, 7861ca7b0cSRay Jui [BCM_CYGNUS_GENPLL_250MHZ_CLK] = { 7961ca7b0cSRay Jui .channel = BCM_CYGNUS_GENPLL_250MHZ_CLK, 8061ca7b0cSRay Jui .flags = IPROC_CLK_AON, 812dfc8a27SJon Mason .enable = ENABLE_VAL(0x4, 7, 1, 13), 822dfc8a27SJon Mason .mdiv = REG_VAL(0x20, 10, 8), 8361ca7b0cSRay Jui }, 8461ca7b0cSRay Jui [BCM_CYGNUS_GENPLL_IHOST_SYS_CLK] = { 8561ca7b0cSRay Jui .channel = BCM_CYGNUS_GENPLL_IHOST_SYS_CLK, 8661ca7b0cSRay Jui .flags = IPROC_CLK_AON, 872dfc8a27SJon Mason .enable = ENABLE_VAL(0x4, 8, 2, 14), 882dfc8a27SJon Mason .mdiv = REG_VAL(0x20, 20, 8), 8961ca7b0cSRay Jui }, 9061ca7b0cSRay Jui [BCM_CYGNUS_GENPLL_ENET_SW_CLK] = { 9161ca7b0cSRay Jui .channel = BCM_CYGNUS_GENPLL_ENET_SW_CLK, 9261ca7b0cSRay Jui .flags = IPROC_CLK_AON, 932dfc8a27SJon Mason .enable = ENABLE_VAL(0x4, 9, 3, 15), 942dfc8a27SJon Mason .mdiv = REG_VAL(0x24, 0, 8), 9561ca7b0cSRay Jui }, 9661ca7b0cSRay Jui [BCM_CYGNUS_GENPLL_AUDIO_125_CLK] = { 9761ca7b0cSRay Jui .channel = BCM_CYGNUS_GENPLL_AUDIO_125_CLK, 9861ca7b0cSRay Jui .flags = IPROC_CLK_AON, 992dfc8a27SJon Mason .enable = ENABLE_VAL(0x4, 10, 4, 16), 1002dfc8a27SJon Mason .mdiv = REG_VAL(0x24, 10, 8), 10161ca7b0cSRay Jui }, 10261ca7b0cSRay Jui [BCM_CYGNUS_GENPLL_CAN_CLK] = { 10361ca7b0cSRay Jui .channel = BCM_CYGNUS_GENPLL_CAN_CLK, 10461ca7b0cSRay Jui .flags = IPROC_CLK_AON, 1052dfc8a27SJon Mason .enable = ENABLE_VAL(0x4, 11, 5, 17), 1062dfc8a27SJon Mason .mdiv = REG_VAL(0x24, 20, 8), 10761ca7b0cSRay Jui }, 10861ca7b0cSRay Jui }; 10961ca7b0cSRay Jui 11061ca7b0cSRay Jui static void __init cygnus_genpll_clk_init(struct device_node *node) 11161ca7b0cSRay Jui { 11261ca7b0cSRay Jui iproc_pll_clk_setup(node, &genpll, NULL, 0, genpll_clk, 11361ca7b0cSRay Jui ARRAY_SIZE(genpll_clk)); 11461ca7b0cSRay Jui } 11561ca7b0cSRay Jui CLK_OF_DECLARE(cygnus_genpll, "brcm,cygnus-genpll", cygnus_genpll_clk_init); 11661ca7b0cSRay Jui 11761ca7b0cSRay Jui static const struct iproc_pll_ctrl lcpll0 = { 11861ca7b0cSRay Jui .flags = IPROC_CLK_AON | IPROC_CLK_PLL_NEEDS_SW_CFG, 1192dfc8a27SJon Mason .aon = AON_VAL(0x0, 2, 5, 4), 120f713c6bfSJon Mason .reset = RESET_VAL(0x0, 31, 30), 121f713c6bfSJon Mason .dig_filter = DF_VAL(0x0, 27, 3, 23, 4, 19, 4), 1222dfc8a27SJon Mason .sw_ctrl = SW_CTRL_VAL(0x4, 31), 1232dfc8a27SJon Mason .ndiv_int = REG_VAL(0x4, 16, 10), 1242dfc8a27SJon Mason .pdiv = REG_VAL(0x4, 26, 4), 1252dfc8a27SJon Mason .vco_ctrl = VCO_CTRL_VAL(0x10, 0x14), 1262dfc8a27SJon Mason .status = REG_VAL(0x18, 12, 1), 12761ca7b0cSRay Jui }; 12861ca7b0cSRay Jui 12961ca7b0cSRay Jui static const struct iproc_clk_ctrl lcpll0_clk[] = { 13061ca7b0cSRay Jui [BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK] = { 13161ca7b0cSRay Jui .channel = BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK, 13261ca7b0cSRay Jui .flags = IPROC_CLK_AON, 1332dfc8a27SJon Mason .enable = ENABLE_VAL(0x0, 7, 1, 13), 1342dfc8a27SJon Mason .mdiv = REG_VAL(0x8, 0, 8), 13561ca7b0cSRay Jui }, 13661ca7b0cSRay Jui [BCM_CYGNUS_LCPLL0_DDR_PHY_CLK] = { 13761ca7b0cSRay Jui .channel = BCM_CYGNUS_LCPLL0_DDR_PHY_CLK, 13861ca7b0cSRay Jui .flags = IPROC_CLK_AON, 1392dfc8a27SJon Mason .enable = ENABLE_VAL(0x0, 8, 2, 14), 1402dfc8a27SJon Mason .mdiv = REG_VAL(0x8, 10, 8), 14161ca7b0cSRay Jui }, 14261ca7b0cSRay Jui [BCM_CYGNUS_LCPLL0_SDIO_CLK] = { 14361ca7b0cSRay Jui .channel = BCM_CYGNUS_LCPLL0_SDIO_CLK, 14461ca7b0cSRay Jui .flags = IPROC_CLK_AON, 1452dfc8a27SJon Mason .enable = ENABLE_VAL(0x0, 9, 3, 15), 1462dfc8a27SJon Mason .mdiv = REG_VAL(0x8, 20, 8), 14761ca7b0cSRay Jui }, 14861ca7b0cSRay Jui [BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK] = { 14961ca7b0cSRay Jui .channel = BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK, 15061ca7b0cSRay Jui .flags = IPROC_CLK_AON, 1512dfc8a27SJon Mason .enable = ENABLE_VAL(0x0, 10, 4, 16), 1522dfc8a27SJon Mason .mdiv = REG_VAL(0xc, 0, 8), 15361ca7b0cSRay Jui }, 15461ca7b0cSRay Jui [BCM_CYGNUS_LCPLL0_SMART_CARD_CLK] = { 15561ca7b0cSRay Jui .channel = BCM_CYGNUS_LCPLL0_SMART_CARD_CLK, 15661ca7b0cSRay Jui .flags = IPROC_CLK_AON, 1572dfc8a27SJon Mason .enable = ENABLE_VAL(0x0, 11, 5, 17), 1582dfc8a27SJon Mason .mdiv = REG_VAL(0xc, 10, 8), 15961ca7b0cSRay Jui }, 16061ca7b0cSRay Jui [BCM_CYGNUS_LCPLL0_CH5_UNUSED] = { 16161ca7b0cSRay Jui .channel = BCM_CYGNUS_LCPLL0_CH5_UNUSED, 16261ca7b0cSRay Jui .flags = IPROC_CLK_AON, 1632dfc8a27SJon Mason .enable = ENABLE_VAL(0x0, 12, 6, 18), 1642dfc8a27SJon Mason .mdiv = REG_VAL(0xc, 20, 8), 16561ca7b0cSRay Jui }, 16661ca7b0cSRay Jui }; 16761ca7b0cSRay Jui 16861ca7b0cSRay Jui static void __init cygnus_lcpll0_clk_init(struct device_node *node) 16961ca7b0cSRay Jui { 17061ca7b0cSRay Jui iproc_pll_clk_setup(node, &lcpll0, NULL, 0, lcpll0_clk, 17161ca7b0cSRay Jui ARRAY_SIZE(lcpll0_clk)); 17261ca7b0cSRay Jui } 17361ca7b0cSRay Jui CLK_OF_DECLARE(cygnus_lcpll0, "brcm,cygnus-lcpll0", cygnus_lcpll0_clk_init); 17461ca7b0cSRay Jui 17561ca7b0cSRay Jui /* 17661ca7b0cSRay Jui * MIPI PLL VCO frequency parameter table 17761ca7b0cSRay Jui */ 17861ca7b0cSRay Jui static const struct iproc_pll_vco_param mipipll_vco_params[] = { 17961ca7b0cSRay Jui /* rate (Hz) ndiv_int ndiv_frac pdiv */ 18061ca7b0cSRay Jui { 750000000UL, 30, 0, 1 }, 18161ca7b0cSRay Jui { 1000000000UL, 40, 0, 1 }, 18261ca7b0cSRay Jui { 1350000000ul, 54, 0, 1 }, 18361ca7b0cSRay Jui { 2000000000UL, 80, 0, 1 }, 18461ca7b0cSRay Jui { 2100000000UL, 84, 0, 1 }, 18561ca7b0cSRay Jui { 2250000000UL, 90, 0, 1 }, 18661ca7b0cSRay Jui { 2500000000UL, 100, 0, 1 }, 18761ca7b0cSRay Jui { 2700000000UL, 54, 0, 0 }, 18861ca7b0cSRay Jui { 2975000000UL, 119, 0, 1 }, 18961ca7b0cSRay Jui { 3100000000UL, 124, 0, 1 }, 19061ca7b0cSRay Jui { 3150000000UL, 126, 0, 1 }, 19161ca7b0cSRay Jui }; 19261ca7b0cSRay Jui 19361ca7b0cSRay Jui static const struct iproc_pll_ctrl mipipll = { 19461ca7b0cSRay Jui .flags = IPROC_CLK_PLL_ASIU | IPROC_CLK_PLL_HAS_NDIV_FRAC | 19561ca7b0cSRay Jui IPROC_CLK_NEEDS_READ_BACK, 1962dfc8a27SJon Mason .aon = AON_VAL(0x0, 4, 17, 16), 1972dfc8a27SJon Mason .asiu = ASIU_GATE_VAL(0x0, 3), 198f713c6bfSJon Mason .reset = RESET_VAL(0x0, 11, 10), 199f713c6bfSJon Mason .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 4), 2002dfc8a27SJon Mason .ndiv_int = REG_VAL(0x10, 20, 10), 2012dfc8a27SJon Mason .ndiv_frac = REG_VAL(0x10, 0, 20), 2022dfc8a27SJon Mason .pdiv = REG_VAL(0x14, 0, 4), 2032dfc8a27SJon Mason .vco_ctrl = VCO_CTRL_VAL(0x18, 0x1c), 2042dfc8a27SJon Mason .status = REG_VAL(0x28, 12, 1), 20561ca7b0cSRay Jui }; 20661ca7b0cSRay Jui 20761ca7b0cSRay Jui static const struct iproc_clk_ctrl mipipll_clk[] = { 20861ca7b0cSRay Jui [BCM_CYGNUS_MIPIPLL_CH0_UNUSED] = { 20961ca7b0cSRay Jui .channel = BCM_CYGNUS_MIPIPLL_CH0_UNUSED, 21061ca7b0cSRay Jui .flags = IPROC_CLK_NEEDS_READ_BACK, 2112dfc8a27SJon Mason .enable = ENABLE_VAL(0x4, 12, 6, 18), 2122dfc8a27SJon Mason .mdiv = REG_VAL(0x20, 0, 8), 21361ca7b0cSRay Jui }, 21461ca7b0cSRay Jui [BCM_CYGNUS_MIPIPLL_CH1_LCD] = { 21561ca7b0cSRay Jui .channel = BCM_CYGNUS_MIPIPLL_CH1_LCD, 21661ca7b0cSRay Jui .flags = IPROC_CLK_NEEDS_READ_BACK, 2172dfc8a27SJon Mason .enable = ENABLE_VAL(0x4, 13, 7, 19), 2182dfc8a27SJon Mason .mdiv = REG_VAL(0x20, 10, 8), 21961ca7b0cSRay Jui }, 22061ca7b0cSRay Jui [BCM_CYGNUS_MIPIPLL_CH2_V3D] = { 22161ca7b0cSRay Jui .channel = BCM_CYGNUS_MIPIPLL_CH2_V3D, 22261ca7b0cSRay Jui .flags = IPROC_CLK_NEEDS_READ_BACK, 2232dfc8a27SJon Mason .enable = ENABLE_VAL(0x4, 14, 8, 20), 2242dfc8a27SJon Mason .mdiv = REG_VAL(0x20, 20, 8), 22561ca7b0cSRay Jui }, 22661ca7b0cSRay Jui [BCM_CYGNUS_MIPIPLL_CH3_UNUSED] = { 22761ca7b0cSRay Jui .channel = BCM_CYGNUS_MIPIPLL_CH3_UNUSED, 22861ca7b0cSRay Jui .flags = IPROC_CLK_NEEDS_READ_BACK, 2292dfc8a27SJon Mason .enable = ENABLE_VAL(0x4, 15, 9, 21), 2302dfc8a27SJon Mason .mdiv = REG_VAL(0x24, 0, 8), 23161ca7b0cSRay Jui }, 23261ca7b0cSRay Jui [BCM_CYGNUS_MIPIPLL_CH4_UNUSED] = { 23361ca7b0cSRay Jui .channel = BCM_CYGNUS_MIPIPLL_CH4_UNUSED, 23461ca7b0cSRay Jui .flags = IPROC_CLK_NEEDS_READ_BACK, 2352dfc8a27SJon Mason .enable = ENABLE_VAL(0x4, 16, 10, 22), 2362dfc8a27SJon Mason .mdiv = REG_VAL(0x24, 10, 8), 23761ca7b0cSRay Jui }, 23861ca7b0cSRay Jui [BCM_CYGNUS_MIPIPLL_CH5_UNUSED] = { 23961ca7b0cSRay Jui .channel = BCM_CYGNUS_MIPIPLL_CH5_UNUSED, 24061ca7b0cSRay Jui .flags = IPROC_CLK_NEEDS_READ_BACK, 2412dfc8a27SJon Mason .enable = ENABLE_VAL(0x4, 17, 11, 23), 2422dfc8a27SJon Mason .mdiv = REG_VAL(0x24, 20, 8), 24361ca7b0cSRay Jui }, 24461ca7b0cSRay Jui }; 24561ca7b0cSRay Jui 24661ca7b0cSRay Jui static void __init cygnus_mipipll_clk_init(struct device_node *node) 24761ca7b0cSRay Jui { 24861ca7b0cSRay Jui iproc_pll_clk_setup(node, &mipipll, mipipll_vco_params, 24961ca7b0cSRay Jui ARRAY_SIZE(mipipll_vco_params), mipipll_clk, 25061ca7b0cSRay Jui ARRAY_SIZE(mipipll_clk)); 25161ca7b0cSRay Jui } 25261ca7b0cSRay Jui CLK_OF_DECLARE(cygnus_mipipll, "brcm,cygnus-mipipll", cygnus_mipipll_clk_init); 25361ca7b0cSRay Jui 25461ca7b0cSRay Jui static const struct iproc_asiu_div asiu_div[] = { 2552dfc8a27SJon Mason [BCM_CYGNUS_ASIU_KEYPAD_CLK] = ASIU_DIV_VAL(0x0, 31, 16, 10, 0, 10), 2562dfc8a27SJon Mason [BCM_CYGNUS_ASIU_ADC_CLK] = ASIU_DIV_VAL(0x4, 31, 16, 10, 0, 10), 2572dfc8a27SJon Mason [BCM_CYGNUS_ASIU_PWM_CLK] = ASIU_DIV_VAL(0x8, 31, 16, 10, 0, 10), 25861ca7b0cSRay Jui }; 25961ca7b0cSRay Jui 26061ca7b0cSRay Jui static const struct iproc_asiu_gate asiu_gate[] = { 2612dfc8a27SJon Mason [BCM_CYGNUS_ASIU_KEYPAD_CLK] = ASIU_GATE_VAL(0x0, 7), 2622dfc8a27SJon Mason [BCM_CYGNUS_ASIU_ADC_CLK] = ASIU_GATE_VAL(0x0, 9), 2632dfc8a27SJon Mason [BCM_CYGNUS_ASIU_PWM_CLK] = ASIU_GATE_VAL(IPROC_CLK_INVALID_OFFSET, 0), 26461ca7b0cSRay Jui }; 26561ca7b0cSRay Jui 26661ca7b0cSRay Jui static void __init cygnus_asiu_init(struct device_node *node) 26761ca7b0cSRay Jui { 26861ca7b0cSRay Jui iproc_asiu_setup(node, asiu_div, asiu_gate, ARRAY_SIZE(asiu_div)); 26961ca7b0cSRay Jui } 27061ca7b0cSRay Jui CLK_OF_DECLARE(cygnus_asiu_clk, "brcm,cygnus-asiu-clk", cygnus_asiu_init); 271bcd8be13SSimran Rai 272bcd8be13SSimran Rai /* 273bcd8be13SSimran Rai * AUDIO PLL VCO frequency parameter table 274bcd8be13SSimran Rai * 275bcd8be13SSimran Rai * PLL output frequency = ((ndiv_int + ndiv_frac / 2^20) * 276bcd8be13SSimran Rai * (parent clock rate / pdiv) 277bcd8be13SSimran Rai * 278bcd8be13SSimran Rai * On Cygnus, parent is the 25MHz oscillator 279bcd8be13SSimran Rai */ 280bcd8be13SSimran Rai static const struct iproc_pll_vco_param audiopll_vco_params[] = { 281bcd8be13SSimran Rai /* rate (Hz) ndiv_int ndiv_frac pdiv */ 282bcd8be13SSimran Rai { 1354750204UL, 54, 199238, 1 }, 283bcd8be13SSimran Rai { 1769470191UL, 70, 816639, 1 }, 284bcd8be13SSimran Rai }; 285bcd8be13SSimran Rai 286bcd8be13SSimran Rai static const struct iproc_pll_ctrl audiopll = { 287bcd8be13SSimran Rai .flags = IPROC_CLK_PLL_NEEDS_SW_CFG | IPROC_CLK_PLL_HAS_NDIV_FRAC | 288bcd8be13SSimran Rai IPROC_CLK_PLL_USER_MODE_ON | IPROC_CLK_PLL_RESET_ACTIVE_LOW, 289bcd8be13SSimran Rai .reset = RESET_VAL(0x5c, 0, 1), 290bcd8be13SSimran Rai .dig_filter = DF_VAL(0x48, 0, 3, 6, 4, 3, 3), 291bcd8be13SSimran Rai .sw_ctrl = SW_CTRL_VAL(0x4, 0), 292bcd8be13SSimran Rai .ndiv_int = REG_VAL(0x8, 0, 10), 293bcd8be13SSimran Rai .ndiv_frac = REG_VAL(0x8, 10, 20), 294bcd8be13SSimran Rai .pdiv = REG_VAL(0x44, 0, 4), 295bcd8be13SSimran Rai .vco_ctrl = VCO_CTRL_VAL(0x0c, 0x10), 296bcd8be13SSimran Rai .status = REG_VAL(0x54, 0, 1), 297bcd8be13SSimran Rai .macro_mode = REG_VAL(0x0, 0, 3), 298bcd8be13SSimran Rai }; 299bcd8be13SSimran Rai 300bcd8be13SSimran Rai static const struct iproc_clk_ctrl audiopll_clk[] = { 301bcd8be13SSimran Rai [BCM_CYGNUS_AUDIOPLL_CH0] = { 302bcd8be13SSimran Rai .channel = BCM_CYGNUS_AUDIOPLL_CH0, 303bcd8be13SSimran Rai .flags = IPROC_CLK_AON | 304bcd8be13SSimran Rai IPROC_CLK_MCLK_DIV_BY_2, 305bcd8be13SSimran Rai .enable = ENABLE_VAL(0x14, 8, 10, 9), 306bcd8be13SSimran Rai .mdiv = REG_VAL(0x14, 0, 8), 307bcd8be13SSimran Rai }, 308bcd8be13SSimran Rai [BCM_CYGNUS_AUDIOPLL_CH1] = { 309bcd8be13SSimran Rai .channel = BCM_CYGNUS_AUDIOPLL_CH1, 310bcd8be13SSimran Rai .flags = IPROC_CLK_AON, 311bcd8be13SSimran Rai .enable = ENABLE_VAL(0x18, 8, 10, 9), 312bcd8be13SSimran Rai .mdiv = REG_VAL(0x18, 0, 8), 313bcd8be13SSimran Rai }, 314bcd8be13SSimran Rai [BCM_CYGNUS_AUDIOPLL_CH2] = { 315bcd8be13SSimran Rai .channel = BCM_CYGNUS_AUDIOPLL_CH2, 316bcd8be13SSimran Rai .flags = IPROC_CLK_AON, 317bcd8be13SSimran Rai .enable = ENABLE_VAL(0x1c, 8, 10, 9), 318bcd8be13SSimran Rai .mdiv = REG_VAL(0x1c, 0, 8), 319bcd8be13SSimran Rai }, 320bcd8be13SSimran Rai }; 321bcd8be13SSimran Rai 322bcd8be13SSimran Rai static void __init cygnus_audiopll_clk_init(struct device_node *node) 323bcd8be13SSimran Rai { 324bcd8be13SSimran Rai iproc_pll_clk_setup(node, &audiopll, audiopll_vco_params, 325bcd8be13SSimran Rai ARRAY_SIZE(audiopll_vco_params), audiopll_clk, 326bcd8be13SSimran Rai ARRAY_SIZE(audiopll_clk)); 327bcd8be13SSimran Rai } 328bcd8be13SSimran Rai CLK_OF_DECLARE(cygnus_audiopll, "brcm,cygnus-audiopll", 329bcd8be13SSimran Rai cygnus_audiopll_clk_init); 330