161ca7b0cSRay Jui /* 261ca7b0cSRay Jui * Copyright (C) 2014 Broadcom Corporation 361ca7b0cSRay Jui * 461ca7b0cSRay Jui * This program is free software; you can redistribute it and/or 561ca7b0cSRay Jui * modify it under the terms of the GNU General Public License as 661ca7b0cSRay Jui * published by the Free Software Foundation version 2. 761ca7b0cSRay Jui * 861ca7b0cSRay Jui * This program is distributed "as is" WITHOUT ANY WARRANTY of any 961ca7b0cSRay Jui * kind, whether express or implied; without even the implied warranty 1061ca7b0cSRay Jui * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1161ca7b0cSRay Jui * GNU General Public License for more details. 1261ca7b0cSRay Jui */ 1361ca7b0cSRay Jui 1461ca7b0cSRay Jui #include <linux/kernel.h> 1561ca7b0cSRay Jui #include <linux/err.h> 1661ca7b0cSRay Jui #include <linux/clk-provider.h> 1761ca7b0cSRay Jui #include <linux/io.h> 1861ca7b0cSRay Jui #include <linux/of.h> 1961ca7b0cSRay Jui #include <linux/clkdev.h> 2061ca7b0cSRay Jui #include <linux/of_address.h> 2161ca7b0cSRay Jui #include <linux/delay.h> 2261ca7b0cSRay Jui 2361ca7b0cSRay Jui #include <dt-bindings/clock/bcm-cygnus.h> 2461ca7b0cSRay Jui #include "clk-iproc.h" 2561ca7b0cSRay Jui 262dfc8a27SJon Mason #define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, } 2761ca7b0cSRay Jui 282dfc8a27SJon Mason #define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \ 2961ca7b0cSRay Jui .pwr_shift = ps, .iso_shift = is } 3061ca7b0cSRay Jui 312dfc8a27SJon Mason #define SW_CTRL_VAL(o, s) { .offset = o, .shift = s, } 3261ca7b0cSRay Jui 332dfc8a27SJon Mason #define ASIU_DIV_VAL(o, es, hs, hw, ls, lw) \ 3461ca7b0cSRay Jui { .offset = o, .en_shift = es, .high_shift = hs, \ 3561ca7b0cSRay Jui .high_width = hw, .low_shift = ls, .low_width = lw } 3661ca7b0cSRay Jui 372dfc8a27SJon Mason #define RESET_VAL(o, rs, prs, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \ 3861ca7b0cSRay Jui .reset_shift = rs, .p_reset_shift = prs, .ki_shift = kis, \ 3961ca7b0cSRay Jui .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \ 4061ca7b0cSRay Jui .ka_width = kaw } 4161ca7b0cSRay Jui 422dfc8a27SJon Mason #define VCO_CTRL_VAL(uo, lo) { .u_offset = uo, .l_offset = lo } 4361ca7b0cSRay Jui 442dfc8a27SJon Mason #define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \ 4561ca7b0cSRay Jui .hold_shift = hs, .bypass_shift = bs } 4661ca7b0cSRay Jui 472dfc8a27SJon Mason #define ASIU_GATE_VAL(o, es) { .offset = o, .en_shift = es } 4861ca7b0cSRay Jui 4961ca7b0cSRay Jui static void __init cygnus_armpll_init(struct device_node *node) 5061ca7b0cSRay Jui { 5161ca7b0cSRay Jui iproc_armpll_setup(node); 5261ca7b0cSRay Jui } 5361ca7b0cSRay Jui CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll", cygnus_armpll_init); 5461ca7b0cSRay Jui 5561ca7b0cSRay Jui static const struct iproc_pll_ctrl genpll = { 5661ca7b0cSRay Jui .flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC | 5761ca7b0cSRay Jui IPROC_CLK_PLL_NEEDS_SW_CFG, 582dfc8a27SJon Mason .aon = AON_VAL(0x0, 2, 1, 0), 592dfc8a27SJon Mason .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 3), 602dfc8a27SJon Mason .sw_ctrl = SW_CTRL_VAL(0x10, 31), 612dfc8a27SJon Mason .ndiv_int = REG_VAL(0x10, 20, 10), 622dfc8a27SJon Mason .ndiv_frac = REG_VAL(0x10, 0, 20), 632dfc8a27SJon Mason .pdiv = REG_VAL(0x14, 0, 4), 642dfc8a27SJon Mason .vco_ctrl = VCO_CTRL_VAL(0x18, 0x1c), 652dfc8a27SJon Mason .status = REG_VAL(0x28, 12, 1), 6661ca7b0cSRay Jui }; 6761ca7b0cSRay Jui 6861ca7b0cSRay Jui static const struct iproc_clk_ctrl genpll_clk[] = { 6961ca7b0cSRay Jui [BCM_CYGNUS_GENPLL_AXI21_CLK] = { 7061ca7b0cSRay Jui .channel = BCM_CYGNUS_GENPLL_AXI21_CLK, 7161ca7b0cSRay Jui .flags = IPROC_CLK_AON, 722dfc8a27SJon Mason .enable = ENABLE_VAL(0x4, 6, 0, 12), 732dfc8a27SJon Mason .mdiv = REG_VAL(0x20, 0, 8), 7461ca7b0cSRay Jui }, 7561ca7b0cSRay Jui [BCM_CYGNUS_GENPLL_250MHZ_CLK] = { 7661ca7b0cSRay Jui .channel = BCM_CYGNUS_GENPLL_250MHZ_CLK, 7761ca7b0cSRay Jui .flags = IPROC_CLK_AON, 782dfc8a27SJon Mason .enable = ENABLE_VAL(0x4, 7, 1, 13), 792dfc8a27SJon Mason .mdiv = REG_VAL(0x20, 10, 8), 8061ca7b0cSRay Jui }, 8161ca7b0cSRay Jui [BCM_CYGNUS_GENPLL_IHOST_SYS_CLK] = { 8261ca7b0cSRay Jui .channel = BCM_CYGNUS_GENPLL_IHOST_SYS_CLK, 8361ca7b0cSRay Jui .flags = IPROC_CLK_AON, 842dfc8a27SJon Mason .enable = ENABLE_VAL(0x4, 8, 2, 14), 852dfc8a27SJon Mason .mdiv = REG_VAL(0x20, 20, 8), 8661ca7b0cSRay Jui }, 8761ca7b0cSRay Jui [BCM_CYGNUS_GENPLL_ENET_SW_CLK] = { 8861ca7b0cSRay Jui .channel = BCM_CYGNUS_GENPLL_ENET_SW_CLK, 8961ca7b0cSRay Jui .flags = IPROC_CLK_AON, 902dfc8a27SJon Mason .enable = ENABLE_VAL(0x4, 9, 3, 15), 912dfc8a27SJon Mason .mdiv = REG_VAL(0x24, 0, 8), 9261ca7b0cSRay Jui }, 9361ca7b0cSRay Jui [BCM_CYGNUS_GENPLL_AUDIO_125_CLK] = { 9461ca7b0cSRay Jui .channel = BCM_CYGNUS_GENPLL_AUDIO_125_CLK, 9561ca7b0cSRay Jui .flags = IPROC_CLK_AON, 962dfc8a27SJon Mason .enable = ENABLE_VAL(0x4, 10, 4, 16), 972dfc8a27SJon Mason .mdiv = REG_VAL(0x24, 10, 8), 9861ca7b0cSRay Jui }, 9961ca7b0cSRay Jui [BCM_CYGNUS_GENPLL_CAN_CLK] = { 10061ca7b0cSRay Jui .channel = BCM_CYGNUS_GENPLL_CAN_CLK, 10161ca7b0cSRay Jui .flags = IPROC_CLK_AON, 1022dfc8a27SJon Mason .enable = ENABLE_VAL(0x4, 11, 5, 17), 1032dfc8a27SJon Mason .mdiv = REG_VAL(0x24, 20, 8), 10461ca7b0cSRay Jui }, 10561ca7b0cSRay Jui }; 10661ca7b0cSRay Jui 10761ca7b0cSRay Jui static void __init cygnus_genpll_clk_init(struct device_node *node) 10861ca7b0cSRay Jui { 10961ca7b0cSRay Jui iproc_pll_clk_setup(node, &genpll, NULL, 0, genpll_clk, 11061ca7b0cSRay Jui ARRAY_SIZE(genpll_clk)); 11161ca7b0cSRay Jui } 11261ca7b0cSRay Jui CLK_OF_DECLARE(cygnus_genpll, "brcm,cygnus-genpll", cygnus_genpll_clk_init); 11361ca7b0cSRay Jui 11461ca7b0cSRay Jui static const struct iproc_pll_ctrl lcpll0 = { 11561ca7b0cSRay Jui .flags = IPROC_CLK_AON | IPROC_CLK_PLL_NEEDS_SW_CFG, 1162dfc8a27SJon Mason .aon = AON_VAL(0x0, 2, 5, 4), 1172dfc8a27SJon Mason .reset = RESET_VAL(0x0, 31, 30, 27, 3, 23, 4, 19, 4), 1182dfc8a27SJon Mason .sw_ctrl = SW_CTRL_VAL(0x4, 31), 1192dfc8a27SJon Mason .ndiv_int = REG_VAL(0x4, 16, 10), 1202dfc8a27SJon Mason .pdiv = REG_VAL(0x4, 26, 4), 1212dfc8a27SJon Mason .vco_ctrl = VCO_CTRL_VAL(0x10, 0x14), 1222dfc8a27SJon Mason .status = REG_VAL(0x18, 12, 1), 12361ca7b0cSRay Jui }; 12461ca7b0cSRay Jui 12561ca7b0cSRay Jui static const struct iproc_clk_ctrl lcpll0_clk[] = { 12661ca7b0cSRay Jui [BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK] = { 12761ca7b0cSRay Jui .channel = BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK, 12861ca7b0cSRay Jui .flags = IPROC_CLK_AON, 1292dfc8a27SJon Mason .enable = ENABLE_VAL(0x0, 7, 1, 13), 1302dfc8a27SJon Mason .mdiv = REG_VAL(0x8, 0, 8), 13161ca7b0cSRay Jui }, 13261ca7b0cSRay Jui [BCM_CYGNUS_LCPLL0_DDR_PHY_CLK] = { 13361ca7b0cSRay Jui .channel = BCM_CYGNUS_LCPLL0_DDR_PHY_CLK, 13461ca7b0cSRay Jui .flags = IPROC_CLK_AON, 1352dfc8a27SJon Mason .enable = ENABLE_VAL(0x0, 8, 2, 14), 1362dfc8a27SJon Mason .mdiv = REG_VAL(0x8, 10, 8), 13761ca7b0cSRay Jui }, 13861ca7b0cSRay Jui [BCM_CYGNUS_LCPLL0_SDIO_CLK] = { 13961ca7b0cSRay Jui .channel = BCM_CYGNUS_LCPLL0_SDIO_CLK, 14061ca7b0cSRay Jui .flags = IPROC_CLK_AON, 1412dfc8a27SJon Mason .enable = ENABLE_VAL(0x0, 9, 3, 15), 1422dfc8a27SJon Mason .mdiv = REG_VAL(0x8, 20, 8), 14361ca7b0cSRay Jui }, 14461ca7b0cSRay Jui [BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK] = { 14561ca7b0cSRay Jui .channel = BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK, 14661ca7b0cSRay Jui .flags = IPROC_CLK_AON, 1472dfc8a27SJon Mason .enable = ENABLE_VAL(0x0, 10, 4, 16), 1482dfc8a27SJon Mason .mdiv = REG_VAL(0xc, 0, 8), 14961ca7b0cSRay Jui }, 15061ca7b0cSRay Jui [BCM_CYGNUS_LCPLL0_SMART_CARD_CLK] = { 15161ca7b0cSRay Jui .channel = BCM_CYGNUS_LCPLL0_SMART_CARD_CLK, 15261ca7b0cSRay Jui .flags = IPROC_CLK_AON, 1532dfc8a27SJon Mason .enable = ENABLE_VAL(0x0, 11, 5, 17), 1542dfc8a27SJon Mason .mdiv = REG_VAL(0xc, 10, 8), 15561ca7b0cSRay Jui }, 15661ca7b0cSRay Jui [BCM_CYGNUS_LCPLL0_CH5_UNUSED] = { 15761ca7b0cSRay Jui .channel = BCM_CYGNUS_LCPLL0_CH5_UNUSED, 15861ca7b0cSRay Jui .flags = IPROC_CLK_AON, 1592dfc8a27SJon Mason .enable = ENABLE_VAL(0x0, 12, 6, 18), 1602dfc8a27SJon Mason .mdiv = REG_VAL(0xc, 20, 8), 16161ca7b0cSRay Jui }, 16261ca7b0cSRay Jui }; 16361ca7b0cSRay Jui 16461ca7b0cSRay Jui static void __init cygnus_lcpll0_clk_init(struct device_node *node) 16561ca7b0cSRay Jui { 16661ca7b0cSRay Jui iproc_pll_clk_setup(node, &lcpll0, NULL, 0, lcpll0_clk, 16761ca7b0cSRay Jui ARRAY_SIZE(lcpll0_clk)); 16861ca7b0cSRay Jui } 16961ca7b0cSRay Jui CLK_OF_DECLARE(cygnus_lcpll0, "brcm,cygnus-lcpll0", cygnus_lcpll0_clk_init); 17061ca7b0cSRay Jui 17161ca7b0cSRay Jui /* 17261ca7b0cSRay Jui * MIPI PLL VCO frequency parameter table 17361ca7b0cSRay Jui */ 17461ca7b0cSRay Jui static const struct iproc_pll_vco_param mipipll_vco_params[] = { 17561ca7b0cSRay Jui /* rate (Hz) ndiv_int ndiv_frac pdiv */ 17661ca7b0cSRay Jui { 750000000UL, 30, 0, 1 }, 17761ca7b0cSRay Jui { 1000000000UL, 40, 0, 1 }, 17861ca7b0cSRay Jui { 1350000000ul, 54, 0, 1 }, 17961ca7b0cSRay Jui { 2000000000UL, 80, 0, 1 }, 18061ca7b0cSRay Jui { 2100000000UL, 84, 0, 1 }, 18161ca7b0cSRay Jui { 2250000000UL, 90, 0, 1 }, 18261ca7b0cSRay Jui { 2500000000UL, 100, 0, 1 }, 18361ca7b0cSRay Jui { 2700000000UL, 54, 0, 0 }, 18461ca7b0cSRay Jui { 2975000000UL, 119, 0, 1 }, 18561ca7b0cSRay Jui { 3100000000UL, 124, 0, 1 }, 18661ca7b0cSRay Jui { 3150000000UL, 126, 0, 1 }, 18761ca7b0cSRay Jui }; 18861ca7b0cSRay Jui 18961ca7b0cSRay Jui static const struct iproc_pll_ctrl mipipll = { 19061ca7b0cSRay Jui .flags = IPROC_CLK_PLL_ASIU | IPROC_CLK_PLL_HAS_NDIV_FRAC | 19161ca7b0cSRay Jui IPROC_CLK_NEEDS_READ_BACK, 1922dfc8a27SJon Mason .aon = AON_VAL(0x0, 4, 17, 16), 1932dfc8a27SJon Mason .asiu = ASIU_GATE_VAL(0x0, 3), 1942dfc8a27SJon Mason .reset = RESET_VAL(0x0, 11, 10, 4, 3, 0, 4, 7, 4), 1952dfc8a27SJon Mason .ndiv_int = REG_VAL(0x10, 20, 10), 1962dfc8a27SJon Mason .ndiv_frac = REG_VAL(0x10, 0, 20), 1972dfc8a27SJon Mason .pdiv = REG_VAL(0x14, 0, 4), 1982dfc8a27SJon Mason .vco_ctrl = VCO_CTRL_VAL(0x18, 0x1c), 1992dfc8a27SJon Mason .status = REG_VAL(0x28, 12, 1), 20061ca7b0cSRay Jui }; 20161ca7b0cSRay Jui 20261ca7b0cSRay Jui static const struct iproc_clk_ctrl mipipll_clk[] = { 20361ca7b0cSRay Jui [BCM_CYGNUS_MIPIPLL_CH0_UNUSED] = { 20461ca7b0cSRay Jui .channel = BCM_CYGNUS_MIPIPLL_CH0_UNUSED, 20561ca7b0cSRay Jui .flags = IPROC_CLK_NEEDS_READ_BACK, 2062dfc8a27SJon Mason .enable = ENABLE_VAL(0x4, 12, 6, 18), 2072dfc8a27SJon Mason .mdiv = REG_VAL(0x20, 0, 8), 20861ca7b0cSRay Jui }, 20961ca7b0cSRay Jui [BCM_CYGNUS_MIPIPLL_CH1_LCD] = { 21061ca7b0cSRay Jui .channel = BCM_CYGNUS_MIPIPLL_CH1_LCD, 21161ca7b0cSRay Jui .flags = IPROC_CLK_NEEDS_READ_BACK, 2122dfc8a27SJon Mason .enable = ENABLE_VAL(0x4, 13, 7, 19), 2132dfc8a27SJon Mason .mdiv = REG_VAL(0x20, 10, 8), 21461ca7b0cSRay Jui }, 21561ca7b0cSRay Jui [BCM_CYGNUS_MIPIPLL_CH2_V3D] = { 21661ca7b0cSRay Jui .channel = BCM_CYGNUS_MIPIPLL_CH2_V3D, 21761ca7b0cSRay Jui .flags = IPROC_CLK_NEEDS_READ_BACK, 2182dfc8a27SJon Mason .enable = ENABLE_VAL(0x4, 14, 8, 20), 2192dfc8a27SJon Mason .mdiv = REG_VAL(0x20, 20, 8), 22061ca7b0cSRay Jui }, 22161ca7b0cSRay Jui [BCM_CYGNUS_MIPIPLL_CH3_UNUSED] = { 22261ca7b0cSRay Jui .channel = BCM_CYGNUS_MIPIPLL_CH3_UNUSED, 22361ca7b0cSRay Jui .flags = IPROC_CLK_NEEDS_READ_BACK, 2242dfc8a27SJon Mason .enable = ENABLE_VAL(0x4, 15, 9, 21), 2252dfc8a27SJon Mason .mdiv = REG_VAL(0x24, 0, 8), 22661ca7b0cSRay Jui }, 22761ca7b0cSRay Jui [BCM_CYGNUS_MIPIPLL_CH4_UNUSED] = { 22861ca7b0cSRay Jui .channel = BCM_CYGNUS_MIPIPLL_CH4_UNUSED, 22961ca7b0cSRay Jui .flags = IPROC_CLK_NEEDS_READ_BACK, 2302dfc8a27SJon Mason .enable = ENABLE_VAL(0x4, 16, 10, 22), 2312dfc8a27SJon Mason .mdiv = REG_VAL(0x24, 10, 8), 23261ca7b0cSRay Jui }, 23361ca7b0cSRay Jui [BCM_CYGNUS_MIPIPLL_CH5_UNUSED] = { 23461ca7b0cSRay Jui .channel = BCM_CYGNUS_MIPIPLL_CH5_UNUSED, 23561ca7b0cSRay Jui .flags = IPROC_CLK_NEEDS_READ_BACK, 2362dfc8a27SJon Mason .enable = ENABLE_VAL(0x4, 17, 11, 23), 2372dfc8a27SJon Mason .mdiv = REG_VAL(0x24, 20, 8), 23861ca7b0cSRay Jui }, 23961ca7b0cSRay Jui }; 24061ca7b0cSRay Jui 24161ca7b0cSRay Jui static void __init cygnus_mipipll_clk_init(struct device_node *node) 24261ca7b0cSRay Jui { 24361ca7b0cSRay Jui iproc_pll_clk_setup(node, &mipipll, mipipll_vco_params, 24461ca7b0cSRay Jui ARRAY_SIZE(mipipll_vco_params), mipipll_clk, 24561ca7b0cSRay Jui ARRAY_SIZE(mipipll_clk)); 24661ca7b0cSRay Jui } 24761ca7b0cSRay Jui CLK_OF_DECLARE(cygnus_mipipll, "brcm,cygnus-mipipll", cygnus_mipipll_clk_init); 24861ca7b0cSRay Jui 24961ca7b0cSRay Jui static const struct iproc_asiu_div asiu_div[] = { 2502dfc8a27SJon Mason [BCM_CYGNUS_ASIU_KEYPAD_CLK] = ASIU_DIV_VAL(0x0, 31, 16, 10, 0, 10), 2512dfc8a27SJon Mason [BCM_CYGNUS_ASIU_ADC_CLK] = ASIU_DIV_VAL(0x4, 31, 16, 10, 0, 10), 2522dfc8a27SJon Mason [BCM_CYGNUS_ASIU_PWM_CLK] = ASIU_DIV_VAL(0x8, 31, 16, 10, 0, 10), 25361ca7b0cSRay Jui }; 25461ca7b0cSRay Jui 25561ca7b0cSRay Jui static const struct iproc_asiu_gate asiu_gate[] = { 2562dfc8a27SJon Mason [BCM_CYGNUS_ASIU_KEYPAD_CLK] = ASIU_GATE_VAL(0x0, 7), 2572dfc8a27SJon Mason [BCM_CYGNUS_ASIU_ADC_CLK] = ASIU_GATE_VAL(0x0, 9), 2582dfc8a27SJon Mason [BCM_CYGNUS_ASIU_PWM_CLK] = ASIU_GATE_VAL(IPROC_CLK_INVALID_OFFSET, 0), 25961ca7b0cSRay Jui }; 26061ca7b0cSRay Jui 26161ca7b0cSRay Jui static void __init cygnus_asiu_init(struct device_node *node) 26261ca7b0cSRay Jui { 26361ca7b0cSRay Jui iproc_asiu_setup(node, asiu_div, asiu_gate, ARRAY_SIZE(asiu_div)); 26461ca7b0cSRay Jui } 26561ca7b0cSRay Jui CLK_OF_DECLARE(cygnus_asiu_clk, "brcm,cygnus-asiu-clk", cygnus_asiu_init); 266