1 /* 2 * Copyright (C) 2010,2015 Broadcom 3 * Copyright (C) 2012 Stephen Warren 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 */ 16 17 /** 18 * DOC: BCM2835 CPRMAN (clock manager for the "audio" domain) 19 * 20 * The clock tree on the 2835 has several levels. There's a root 21 * oscillator running at 19.2Mhz. After the oscillator there are 5 22 * PLLs, roughly divided as "camera", "ARM", "core", "DSI displays", 23 * and "HDMI displays". Those 5 PLLs each can divide their output to 24 * produce up to 4 channels. Finally, there is the level of clocks to 25 * be consumed by other hardware components (like "H264" or "HDMI 26 * state machine"), which divide off of some subset of the PLL 27 * channels. 28 * 29 * All of the clocks in the tree are exposed in the DT, because the DT 30 * may want to make assignments of the final layer of clocks to the 31 * PLL channels, and some components of the hardware will actually 32 * skip layers of the tree (for example, the pixel clock comes 33 * directly from the PLLH PIX channel without using a CM_*CTL clock 34 * generator). 35 */ 36 37 #include <linux/clk-provider.h> 38 #include <linux/clkdev.h> 39 #include <linux/clk.h> 40 #include <linux/clk/bcm2835.h> 41 #include <linux/debugfs.h> 42 #include <linux/module.h> 43 #include <linux/of.h> 44 #include <linux/platform_device.h> 45 #include <linux/slab.h> 46 #include <dt-bindings/clock/bcm2835.h> 47 48 #define CM_PASSWORD 0x5a000000 49 50 #define CM_GNRICCTL 0x000 51 #define CM_GNRICDIV 0x004 52 # define CM_DIV_FRAC_BITS 12 53 # define CM_DIV_FRAC_MASK GENMASK(CM_DIV_FRAC_BITS - 1, 0) 54 55 #define CM_VPUCTL 0x008 56 #define CM_VPUDIV 0x00c 57 #define CM_SYSCTL 0x010 58 #define CM_SYSDIV 0x014 59 #define CM_PERIACTL 0x018 60 #define CM_PERIADIV 0x01c 61 #define CM_PERIICTL 0x020 62 #define CM_PERIIDIV 0x024 63 #define CM_H264CTL 0x028 64 #define CM_H264DIV 0x02c 65 #define CM_ISPCTL 0x030 66 #define CM_ISPDIV 0x034 67 #define CM_V3DCTL 0x038 68 #define CM_V3DDIV 0x03c 69 #define CM_CAM0CTL 0x040 70 #define CM_CAM0DIV 0x044 71 #define CM_CAM1CTL 0x048 72 #define CM_CAM1DIV 0x04c 73 #define CM_CCP2CTL 0x050 74 #define CM_CCP2DIV 0x054 75 #define CM_DSI0ECTL 0x058 76 #define CM_DSI0EDIV 0x05c 77 #define CM_DSI0PCTL 0x060 78 #define CM_DSI0PDIV 0x064 79 #define CM_DPICTL 0x068 80 #define CM_DPIDIV 0x06c 81 #define CM_GP0CTL 0x070 82 #define CM_GP0DIV 0x074 83 #define CM_GP1CTL 0x078 84 #define CM_GP1DIV 0x07c 85 #define CM_GP2CTL 0x080 86 #define CM_GP2DIV 0x084 87 #define CM_HSMCTL 0x088 88 #define CM_HSMDIV 0x08c 89 #define CM_OTPCTL 0x090 90 #define CM_OTPDIV 0x094 91 #define CM_PCMCTL 0x098 92 #define CM_PCMDIV 0x09c 93 #define CM_PWMCTL 0x0a0 94 #define CM_PWMDIV 0x0a4 95 #define CM_SLIMCTL 0x0a8 96 #define CM_SLIMDIV 0x0ac 97 #define CM_SMICTL 0x0b0 98 #define CM_SMIDIV 0x0b4 99 /* no definition for 0x0b8 and 0x0bc */ 100 #define CM_TCNTCTL 0x0c0 101 #define CM_TCNTDIV 0x0c4 102 #define CM_TECCTL 0x0c8 103 #define CM_TECDIV 0x0cc 104 #define CM_TD0CTL 0x0d0 105 #define CM_TD0DIV 0x0d4 106 #define CM_TD1CTL 0x0d8 107 #define CM_TD1DIV 0x0dc 108 #define CM_TSENSCTL 0x0e0 109 #define CM_TSENSDIV 0x0e4 110 #define CM_TIMERCTL 0x0e8 111 #define CM_TIMERDIV 0x0ec 112 #define CM_UARTCTL 0x0f0 113 #define CM_UARTDIV 0x0f4 114 #define CM_VECCTL 0x0f8 115 #define CM_VECDIV 0x0fc 116 #define CM_PULSECTL 0x190 117 #define CM_PULSEDIV 0x194 118 #define CM_SDCCTL 0x1a8 119 #define CM_SDCDIV 0x1ac 120 #define CM_ARMCTL 0x1b0 121 #define CM_AVEOCTL 0x1b8 122 #define CM_AVEODIV 0x1bc 123 #define CM_EMMCCTL 0x1c0 124 #define CM_EMMCDIV 0x1c4 125 126 /* General bits for the CM_*CTL regs */ 127 # define CM_ENABLE BIT(4) 128 # define CM_KILL BIT(5) 129 # define CM_GATE_BIT 6 130 # define CM_GATE BIT(CM_GATE_BIT) 131 # define CM_BUSY BIT(7) 132 # define CM_BUSYD BIT(8) 133 # define CM_FRAC BIT(9) 134 # define CM_SRC_SHIFT 0 135 # define CM_SRC_BITS 4 136 # define CM_SRC_MASK 0xf 137 # define CM_SRC_GND 0 138 # define CM_SRC_OSC 1 139 # define CM_SRC_TESTDEBUG0 2 140 # define CM_SRC_TESTDEBUG1 3 141 # define CM_SRC_PLLA_CORE 4 142 # define CM_SRC_PLLA_PER 4 143 # define CM_SRC_PLLC_CORE0 5 144 # define CM_SRC_PLLC_PER 5 145 # define CM_SRC_PLLC_CORE1 8 146 # define CM_SRC_PLLD_CORE 6 147 # define CM_SRC_PLLD_PER 6 148 # define CM_SRC_PLLH_AUX 7 149 # define CM_SRC_PLLC_CORE1 8 150 # define CM_SRC_PLLC_CORE2 9 151 152 #define CM_OSCCOUNT 0x100 153 154 #define CM_PLLA 0x104 155 # define CM_PLL_ANARST BIT(8) 156 # define CM_PLLA_HOLDPER BIT(7) 157 # define CM_PLLA_LOADPER BIT(6) 158 # define CM_PLLA_HOLDCORE BIT(5) 159 # define CM_PLLA_LOADCORE BIT(4) 160 # define CM_PLLA_HOLDCCP2 BIT(3) 161 # define CM_PLLA_LOADCCP2 BIT(2) 162 # define CM_PLLA_HOLDDSI0 BIT(1) 163 # define CM_PLLA_LOADDSI0 BIT(0) 164 165 #define CM_PLLC 0x108 166 # define CM_PLLC_HOLDPER BIT(7) 167 # define CM_PLLC_LOADPER BIT(6) 168 # define CM_PLLC_HOLDCORE2 BIT(5) 169 # define CM_PLLC_LOADCORE2 BIT(4) 170 # define CM_PLLC_HOLDCORE1 BIT(3) 171 # define CM_PLLC_LOADCORE1 BIT(2) 172 # define CM_PLLC_HOLDCORE0 BIT(1) 173 # define CM_PLLC_LOADCORE0 BIT(0) 174 175 #define CM_PLLD 0x10c 176 # define CM_PLLD_HOLDPER BIT(7) 177 # define CM_PLLD_LOADPER BIT(6) 178 # define CM_PLLD_HOLDCORE BIT(5) 179 # define CM_PLLD_LOADCORE BIT(4) 180 # define CM_PLLD_HOLDDSI1 BIT(3) 181 # define CM_PLLD_LOADDSI1 BIT(2) 182 # define CM_PLLD_HOLDDSI0 BIT(1) 183 # define CM_PLLD_LOADDSI0 BIT(0) 184 185 #define CM_PLLH 0x110 186 # define CM_PLLH_LOADRCAL BIT(2) 187 # define CM_PLLH_LOADAUX BIT(1) 188 # define CM_PLLH_LOADPIX BIT(0) 189 190 #define CM_LOCK 0x114 191 # define CM_LOCK_FLOCKH BIT(12) 192 # define CM_LOCK_FLOCKD BIT(11) 193 # define CM_LOCK_FLOCKC BIT(10) 194 # define CM_LOCK_FLOCKB BIT(9) 195 # define CM_LOCK_FLOCKA BIT(8) 196 197 #define CM_EVENT 0x118 198 #define CM_DSI1ECTL 0x158 199 #define CM_DSI1EDIV 0x15c 200 #define CM_DSI1PCTL 0x160 201 #define CM_DSI1PDIV 0x164 202 #define CM_DFTCTL 0x168 203 #define CM_DFTDIV 0x16c 204 205 #define CM_PLLB 0x170 206 # define CM_PLLB_HOLDARM BIT(1) 207 # define CM_PLLB_LOADARM BIT(0) 208 209 #define A2W_PLLA_CTRL 0x1100 210 #define A2W_PLLC_CTRL 0x1120 211 #define A2W_PLLD_CTRL 0x1140 212 #define A2W_PLLH_CTRL 0x1160 213 #define A2W_PLLB_CTRL 0x11e0 214 # define A2W_PLL_CTRL_PRST_DISABLE BIT(17) 215 # define A2W_PLL_CTRL_PWRDN BIT(16) 216 # define A2W_PLL_CTRL_PDIV_MASK 0x000007000 217 # define A2W_PLL_CTRL_PDIV_SHIFT 12 218 # define A2W_PLL_CTRL_NDIV_MASK 0x0000003ff 219 # define A2W_PLL_CTRL_NDIV_SHIFT 0 220 221 #define A2W_PLLA_ANA0 0x1010 222 #define A2W_PLLC_ANA0 0x1030 223 #define A2W_PLLD_ANA0 0x1050 224 #define A2W_PLLH_ANA0 0x1070 225 #define A2W_PLLB_ANA0 0x10f0 226 227 #define A2W_PLL_KA_SHIFT 7 228 #define A2W_PLL_KA_MASK GENMASK(9, 7) 229 #define A2W_PLL_KI_SHIFT 19 230 #define A2W_PLL_KI_MASK GENMASK(21, 19) 231 #define A2W_PLL_KP_SHIFT 15 232 #define A2W_PLL_KP_MASK GENMASK(18, 15) 233 234 #define A2W_PLLH_KA_SHIFT 19 235 #define A2W_PLLH_KA_MASK GENMASK(21, 19) 236 #define A2W_PLLH_KI_LOW_SHIFT 22 237 #define A2W_PLLH_KI_LOW_MASK GENMASK(23, 22) 238 #define A2W_PLLH_KI_HIGH_SHIFT 0 239 #define A2W_PLLH_KI_HIGH_MASK GENMASK(0, 0) 240 #define A2W_PLLH_KP_SHIFT 1 241 #define A2W_PLLH_KP_MASK GENMASK(4, 1) 242 243 #define A2W_XOSC_CTRL 0x1190 244 # define A2W_XOSC_CTRL_PLLB_ENABLE BIT(7) 245 # define A2W_XOSC_CTRL_PLLA_ENABLE BIT(6) 246 # define A2W_XOSC_CTRL_PLLD_ENABLE BIT(5) 247 # define A2W_XOSC_CTRL_DDR_ENABLE BIT(4) 248 # define A2W_XOSC_CTRL_CPR1_ENABLE BIT(3) 249 # define A2W_XOSC_CTRL_USB_ENABLE BIT(2) 250 # define A2W_XOSC_CTRL_HDMI_ENABLE BIT(1) 251 # define A2W_XOSC_CTRL_PLLC_ENABLE BIT(0) 252 253 #define A2W_PLLA_FRAC 0x1200 254 #define A2W_PLLC_FRAC 0x1220 255 #define A2W_PLLD_FRAC 0x1240 256 #define A2W_PLLH_FRAC 0x1260 257 #define A2W_PLLB_FRAC 0x12e0 258 # define A2W_PLL_FRAC_MASK ((1 << A2W_PLL_FRAC_BITS) - 1) 259 # define A2W_PLL_FRAC_BITS 20 260 261 #define A2W_PLL_CHANNEL_DISABLE BIT(8) 262 #define A2W_PLL_DIV_BITS 8 263 #define A2W_PLL_DIV_SHIFT 0 264 265 #define A2W_PLLA_DSI0 0x1300 266 #define A2W_PLLA_CORE 0x1400 267 #define A2W_PLLA_PER 0x1500 268 #define A2W_PLLA_CCP2 0x1600 269 270 #define A2W_PLLC_CORE2 0x1320 271 #define A2W_PLLC_CORE1 0x1420 272 #define A2W_PLLC_PER 0x1520 273 #define A2W_PLLC_CORE0 0x1620 274 275 #define A2W_PLLD_DSI0 0x1340 276 #define A2W_PLLD_CORE 0x1440 277 #define A2W_PLLD_PER 0x1540 278 #define A2W_PLLD_DSI1 0x1640 279 280 #define A2W_PLLH_AUX 0x1360 281 #define A2W_PLLH_RCAL 0x1460 282 #define A2W_PLLH_PIX 0x1560 283 #define A2W_PLLH_STS 0x1660 284 285 #define A2W_PLLH_CTRLR 0x1960 286 #define A2W_PLLH_FRACR 0x1a60 287 #define A2W_PLLH_AUXR 0x1b60 288 #define A2W_PLLH_RCALR 0x1c60 289 #define A2W_PLLH_PIXR 0x1d60 290 #define A2W_PLLH_STSR 0x1e60 291 292 #define A2W_PLLB_ARM 0x13e0 293 #define A2W_PLLB_SP0 0x14e0 294 #define A2W_PLLB_SP1 0x15e0 295 #define A2W_PLLB_SP2 0x16e0 296 297 #define LOCK_TIMEOUT_NS 100000000 298 #define BCM2835_MAX_FB_RATE 1750000000u 299 300 struct bcm2835_cprman { 301 struct device *dev; 302 void __iomem *regs; 303 spinlock_t regs_lock; /* spinlock for all clocks */ 304 const char *osc_name; 305 306 /* Must be last */ 307 struct clk_hw_onecell_data onecell; 308 }; 309 310 static inline void cprman_write(struct bcm2835_cprman *cprman, u32 reg, u32 val) 311 { 312 writel(CM_PASSWORD | val, cprman->regs + reg); 313 } 314 315 static inline u32 cprman_read(struct bcm2835_cprman *cprman, u32 reg) 316 { 317 return readl(cprman->regs + reg); 318 } 319 320 static int bcm2835_debugfs_regset(struct bcm2835_cprman *cprman, u32 base, 321 struct debugfs_reg32 *regs, size_t nregs, 322 struct dentry *dentry) 323 { 324 struct dentry *regdump; 325 struct debugfs_regset32 *regset; 326 327 regset = devm_kzalloc(cprman->dev, sizeof(*regset), GFP_KERNEL); 328 if (!regset) 329 return -ENOMEM; 330 331 regset->regs = regs; 332 regset->nregs = nregs; 333 regset->base = cprman->regs + base; 334 335 regdump = debugfs_create_regset32("regdump", S_IRUGO, dentry, 336 regset); 337 338 return regdump ? 0 : -ENOMEM; 339 } 340 341 /* 342 * These are fixed clocks. They're probably not all root clocks and it may 343 * be possible to turn them on and off but until this is mapped out better 344 * it's the only way they can be used. 345 */ 346 void __init bcm2835_init_clocks(void) 347 { 348 struct clk_hw *hw; 349 int ret; 350 351 hw = clk_hw_register_fixed_rate(NULL, "apb_pclk", NULL, 0, 126000000); 352 if (IS_ERR(hw)) 353 pr_err("apb_pclk not registered\n"); 354 355 hw = clk_hw_register_fixed_rate(NULL, "uart0_pclk", NULL, 0, 3000000); 356 if (IS_ERR(hw)) 357 pr_err("uart0_pclk not registered\n"); 358 ret = clk_hw_register_clkdev(hw, NULL, "20201000.uart"); 359 if (ret) 360 pr_err("uart0_pclk alias not registered\n"); 361 362 hw = clk_hw_register_fixed_rate(NULL, "uart1_pclk", NULL, 0, 125000000); 363 if (IS_ERR(hw)) 364 pr_err("uart1_pclk not registered\n"); 365 ret = clk_hw_register_clkdev(hw, NULL, "20215000.uart"); 366 if (ret) 367 pr_err("uart1_pclk alias not registered\n"); 368 } 369 370 struct bcm2835_pll_data { 371 const char *name; 372 u32 cm_ctrl_reg; 373 u32 a2w_ctrl_reg; 374 u32 frac_reg; 375 u32 ana_reg_base; 376 u32 reference_enable_mask; 377 /* Bit in CM_LOCK to indicate when the PLL has locked. */ 378 u32 lock_mask; 379 380 const struct bcm2835_pll_ana_bits *ana; 381 382 unsigned long min_rate; 383 unsigned long max_rate; 384 /* 385 * Highest rate for the VCO before we have to use the 386 * pre-divide-by-2. 387 */ 388 unsigned long max_fb_rate; 389 }; 390 391 struct bcm2835_pll_ana_bits { 392 u32 mask0; 393 u32 set0; 394 u32 mask1; 395 u32 set1; 396 u32 mask3; 397 u32 set3; 398 u32 fb_prediv_mask; 399 }; 400 401 static const struct bcm2835_pll_ana_bits bcm2835_ana_default = { 402 .mask0 = 0, 403 .set0 = 0, 404 .mask1 = (u32)~(A2W_PLL_KI_MASK | A2W_PLL_KP_MASK), 405 .set1 = (2 << A2W_PLL_KI_SHIFT) | (8 << A2W_PLL_KP_SHIFT), 406 .mask3 = (u32)~A2W_PLL_KA_MASK, 407 .set3 = (2 << A2W_PLL_KA_SHIFT), 408 .fb_prediv_mask = BIT(14), 409 }; 410 411 static const struct bcm2835_pll_ana_bits bcm2835_ana_pllh = { 412 .mask0 = (u32)~(A2W_PLLH_KA_MASK | A2W_PLLH_KI_LOW_MASK), 413 .set0 = (2 << A2W_PLLH_KA_SHIFT) | (2 << A2W_PLLH_KI_LOW_SHIFT), 414 .mask1 = (u32)~(A2W_PLLH_KI_HIGH_MASK | A2W_PLLH_KP_MASK), 415 .set1 = (6 << A2W_PLLH_KP_SHIFT), 416 .mask3 = 0, 417 .set3 = 0, 418 .fb_prediv_mask = BIT(11), 419 }; 420 421 struct bcm2835_pll_divider_data { 422 const char *name; 423 const char *source_pll; 424 425 u32 cm_reg; 426 u32 a2w_reg; 427 428 u32 load_mask; 429 u32 hold_mask; 430 u32 fixed_divider; 431 }; 432 433 struct bcm2835_clock_data { 434 const char *name; 435 436 const char *const *parents; 437 int num_mux_parents; 438 439 u32 ctl_reg; 440 u32 div_reg; 441 442 /* Number of integer bits in the divider */ 443 u32 int_bits; 444 /* Number of fractional bits in the divider */ 445 u32 frac_bits; 446 447 u32 flags; 448 449 bool is_vpu_clock; 450 bool is_mash_clock; 451 }; 452 453 struct bcm2835_gate_data { 454 const char *name; 455 const char *parent; 456 457 u32 ctl_reg; 458 }; 459 460 struct bcm2835_pll { 461 struct clk_hw hw; 462 struct bcm2835_cprman *cprman; 463 const struct bcm2835_pll_data *data; 464 }; 465 466 static int bcm2835_pll_is_on(struct clk_hw *hw) 467 { 468 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); 469 struct bcm2835_cprman *cprman = pll->cprman; 470 const struct bcm2835_pll_data *data = pll->data; 471 472 return cprman_read(cprman, data->a2w_ctrl_reg) & 473 A2W_PLL_CTRL_PRST_DISABLE; 474 } 475 476 static void bcm2835_pll_choose_ndiv_and_fdiv(unsigned long rate, 477 unsigned long parent_rate, 478 u32 *ndiv, u32 *fdiv) 479 { 480 u64 div; 481 482 div = (u64)rate << A2W_PLL_FRAC_BITS; 483 do_div(div, parent_rate); 484 485 *ndiv = div >> A2W_PLL_FRAC_BITS; 486 *fdiv = div & ((1 << A2W_PLL_FRAC_BITS) - 1); 487 } 488 489 static long bcm2835_pll_rate_from_divisors(unsigned long parent_rate, 490 u32 ndiv, u32 fdiv, u32 pdiv) 491 { 492 u64 rate; 493 494 if (pdiv == 0) 495 return 0; 496 497 rate = (u64)parent_rate * ((ndiv << A2W_PLL_FRAC_BITS) + fdiv); 498 do_div(rate, pdiv); 499 return rate >> A2W_PLL_FRAC_BITS; 500 } 501 502 static long bcm2835_pll_round_rate(struct clk_hw *hw, unsigned long rate, 503 unsigned long *parent_rate) 504 { 505 u32 ndiv, fdiv; 506 507 bcm2835_pll_choose_ndiv_and_fdiv(rate, *parent_rate, &ndiv, &fdiv); 508 509 return bcm2835_pll_rate_from_divisors(*parent_rate, ndiv, fdiv, 1); 510 } 511 512 static unsigned long bcm2835_pll_get_rate(struct clk_hw *hw, 513 unsigned long parent_rate) 514 { 515 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); 516 struct bcm2835_cprman *cprman = pll->cprman; 517 const struct bcm2835_pll_data *data = pll->data; 518 u32 a2wctrl = cprman_read(cprman, data->a2w_ctrl_reg); 519 u32 ndiv, pdiv, fdiv; 520 bool using_prediv; 521 522 if (parent_rate == 0) 523 return 0; 524 525 fdiv = cprman_read(cprman, data->frac_reg) & A2W_PLL_FRAC_MASK; 526 ndiv = (a2wctrl & A2W_PLL_CTRL_NDIV_MASK) >> A2W_PLL_CTRL_NDIV_SHIFT; 527 pdiv = (a2wctrl & A2W_PLL_CTRL_PDIV_MASK) >> A2W_PLL_CTRL_PDIV_SHIFT; 528 using_prediv = cprman_read(cprman, data->ana_reg_base + 4) & 529 data->ana->fb_prediv_mask; 530 531 if (using_prediv) 532 ndiv *= 2; 533 534 return bcm2835_pll_rate_from_divisors(parent_rate, ndiv, fdiv, pdiv); 535 } 536 537 static void bcm2835_pll_off(struct clk_hw *hw) 538 { 539 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); 540 struct bcm2835_cprman *cprman = pll->cprman; 541 const struct bcm2835_pll_data *data = pll->data; 542 543 spin_lock(&cprman->regs_lock); 544 cprman_write(cprman, data->cm_ctrl_reg, 545 cprman_read(cprman, data->cm_ctrl_reg) | 546 CM_PLL_ANARST); 547 cprman_write(cprman, data->a2w_ctrl_reg, 548 cprman_read(cprman, data->a2w_ctrl_reg) | 549 A2W_PLL_CTRL_PWRDN); 550 spin_unlock(&cprman->regs_lock); 551 } 552 553 static int bcm2835_pll_on(struct clk_hw *hw) 554 { 555 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); 556 struct bcm2835_cprman *cprman = pll->cprman; 557 const struct bcm2835_pll_data *data = pll->data; 558 ktime_t timeout; 559 560 cprman_write(cprman, data->a2w_ctrl_reg, 561 cprman_read(cprman, data->a2w_ctrl_reg) & 562 ~A2W_PLL_CTRL_PWRDN); 563 564 /* Take the PLL out of reset. */ 565 cprman_write(cprman, data->cm_ctrl_reg, 566 cprman_read(cprman, data->cm_ctrl_reg) & ~CM_PLL_ANARST); 567 568 /* Wait for the PLL to lock. */ 569 timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS); 570 while (!(cprman_read(cprman, CM_LOCK) & data->lock_mask)) { 571 if (ktime_after(ktime_get(), timeout)) { 572 dev_err(cprman->dev, "%s: couldn't lock PLL\n", 573 clk_hw_get_name(hw)); 574 return -ETIMEDOUT; 575 } 576 577 cpu_relax(); 578 } 579 580 return 0; 581 } 582 583 static void 584 bcm2835_pll_write_ana(struct bcm2835_cprman *cprman, u32 ana_reg_base, u32 *ana) 585 { 586 int i; 587 588 /* 589 * ANA register setup is done as a series of writes to 590 * ANA3-ANA0, in that order. This lets us write all 4 591 * registers as a single cycle of the serdes interface (taking 592 * 100 xosc clocks), whereas if we were to update ana0, 1, and 593 * 3 individually through their partial-write registers, each 594 * would be their own serdes cycle. 595 */ 596 for (i = 3; i >= 0; i--) 597 cprman_write(cprman, ana_reg_base + i * 4, ana[i]); 598 } 599 600 static int bcm2835_pll_set_rate(struct clk_hw *hw, 601 unsigned long rate, unsigned long parent_rate) 602 { 603 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); 604 struct bcm2835_cprman *cprman = pll->cprman; 605 const struct bcm2835_pll_data *data = pll->data; 606 bool was_using_prediv, use_fb_prediv, do_ana_setup_first; 607 u32 ndiv, fdiv, a2w_ctl; 608 u32 ana[4]; 609 int i; 610 611 if (rate < data->min_rate || rate > data->max_rate) { 612 dev_err(cprman->dev, "%s: rate out of spec: %lu vs (%lu, %lu)\n", 613 clk_hw_get_name(hw), rate, 614 data->min_rate, data->max_rate); 615 return -EINVAL; 616 } 617 618 if (rate > data->max_fb_rate) { 619 use_fb_prediv = true; 620 rate /= 2; 621 } else { 622 use_fb_prediv = false; 623 } 624 625 bcm2835_pll_choose_ndiv_and_fdiv(rate, parent_rate, &ndiv, &fdiv); 626 627 for (i = 3; i >= 0; i--) 628 ana[i] = cprman_read(cprman, data->ana_reg_base + i * 4); 629 630 was_using_prediv = ana[1] & data->ana->fb_prediv_mask; 631 632 ana[0] &= ~data->ana->mask0; 633 ana[0] |= data->ana->set0; 634 ana[1] &= ~data->ana->mask1; 635 ana[1] |= data->ana->set1; 636 ana[3] &= ~data->ana->mask3; 637 ana[3] |= data->ana->set3; 638 639 if (was_using_prediv && !use_fb_prediv) { 640 ana[1] &= ~data->ana->fb_prediv_mask; 641 do_ana_setup_first = true; 642 } else if (!was_using_prediv && use_fb_prediv) { 643 ana[1] |= data->ana->fb_prediv_mask; 644 do_ana_setup_first = false; 645 } else { 646 do_ana_setup_first = true; 647 } 648 649 /* Unmask the reference clock from the oscillator. */ 650 cprman_write(cprman, A2W_XOSC_CTRL, 651 cprman_read(cprman, A2W_XOSC_CTRL) | 652 data->reference_enable_mask); 653 654 if (do_ana_setup_first) 655 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana); 656 657 /* Set the PLL multiplier from the oscillator. */ 658 cprman_write(cprman, data->frac_reg, fdiv); 659 660 a2w_ctl = cprman_read(cprman, data->a2w_ctrl_reg); 661 a2w_ctl &= ~A2W_PLL_CTRL_NDIV_MASK; 662 a2w_ctl |= ndiv << A2W_PLL_CTRL_NDIV_SHIFT; 663 a2w_ctl &= ~A2W_PLL_CTRL_PDIV_MASK; 664 a2w_ctl |= 1 << A2W_PLL_CTRL_PDIV_SHIFT; 665 cprman_write(cprman, data->a2w_ctrl_reg, a2w_ctl); 666 667 if (!do_ana_setup_first) 668 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana); 669 670 return 0; 671 } 672 673 static int bcm2835_pll_debug_init(struct clk_hw *hw, 674 struct dentry *dentry) 675 { 676 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); 677 struct bcm2835_cprman *cprman = pll->cprman; 678 const struct bcm2835_pll_data *data = pll->data; 679 struct debugfs_reg32 *regs; 680 681 regs = devm_kzalloc(cprman->dev, 7 * sizeof(*regs), GFP_KERNEL); 682 if (!regs) 683 return -ENOMEM; 684 685 regs[0].name = "cm_ctrl"; 686 regs[0].offset = data->cm_ctrl_reg; 687 regs[1].name = "a2w_ctrl"; 688 regs[1].offset = data->a2w_ctrl_reg; 689 regs[2].name = "frac"; 690 regs[2].offset = data->frac_reg; 691 regs[3].name = "ana0"; 692 regs[3].offset = data->ana_reg_base + 0 * 4; 693 regs[4].name = "ana1"; 694 regs[4].offset = data->ana_reg_base + 1 * 4; 695 regs[5].name = "ana2"; 696 regs[5].offset = data->ana_reg_base + 2 * 4; 697 regs[6].name = "ana3"; 698 regs[6].offset = data->ana_reg_base + 3 * 4; 699 700 return bcm2835_debugfs_regset(cprman, 0, regs, 7, dentry); 701 } 702 703 static const struct clk_ops bcm2835_pll_clk_ops = { 704 .is_prepared = bcm2835_pll_is_on, 705 .prepare = bcm2835_pll_on, 706 .unprepare = bcm2835_pll_off, 707 .recalc_rate = bcm2835_pll_get_rate, 708 .set_rate = bcm2835_pll_set_rate, 709 .round_rate = bcm2835_pll_round_rate, 710 .debug_init = bcm2835_pll_debug_init, 711 }; 712 713 struct bcm2835_pll_divider { 714 struct clk_divider div; 715 struct bcm2835_cprman *cprman; 716 const struct bcm2835_pll_divider_data *data; 717 }; 718 719 static struct bcm2835_pll_divider * 720 bcm2835_pll_divider_from_hw(struct clk_hw *hw) 721 { 722 return container_of(hw, struct bcm2835_pll_divider, div.hw); 723 } 724 725 static int bcm2835_pll_divider_is_on(struct clk_hw *hw) 726 { 727 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); 728 struct bcm2835_cprman *cprman = divider->cprman; 729 const struct bcm2835_pll_divider_data *data = divider->data; 730 731 return !(cprman_read(cprman, data->a2w_reg) & A2W_PLL_CHANNEL_DISABLE); 732 } 733 734 static long bcm2835_pll_divider_round_rate(struct clk_hw *hw, 735 unsigned long rate, 736 unsigned long *parent_rate) 737 { 738 return clk_divider_ops.round_rate(hw, rate, parent_rate); 739 } 740 741 static unsigned long bcm2835_pll_divider_get_rate(struct clk_hw *hw, 742 unsigned long parent_rate) 743 { 744 return clk_divider_ops.recalc_rate(hw, parent_rate); 745 } 746 747 static void bcm2835_pll_divider_off(struct clk_hw *hw) 748 { 749 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); 750 struct bcm2835_cprman *cprman = divider->cprman; 751 const struct bcm2835_pll_divider_data *data = divider->data; 752 753 spin_lock(&cprman->regs_lock); 754 cprman_write(cprman, data->cm_reg, 755 (cprman_read(cprman, data->cm_reg) & 756 ~data->load_mask) | data->hold_mask); 757 cprman_write(cprman, data->a2w_reg, A2W_PLL_CHANNEL_DISABLE); 758 spin_unlock(&cprman->regs_lock); 759 } 760 761 static int bcm2835_pll_divider_on(struct clk_hw *hw) 762 { 763 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); 764 struct bcm2835_cprman *cprman = divider->cprman; 765 const struct bcm2835_pll_divider_data *data = divider->data; 766 767 spin_lock(&cprman->regs_lock); 768 cprman_write(cprman, data->a2w_reg, 769 cprman_read(cprman, data->a2w_reg) & 770 ~A2W_PLL_CHANNEL_DISABLE); 771 772 cprman_write(cprman, data->cm_reg, 773 cprman_read(cprman, data->cm_reg) & ~data->hold_mask); 774 spin_unlock(&cprman->regs_lock); 775 776 return 0; 777 } 778 779 static int bcm2835_pll_divider_set_rate(struct clk_hw *hw, 780 unsigned long rate, 781 unsigned long parent_rate) 782 { 783 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); 784 struct bcm2835_cprman *cprman = divider->cprman; 785 const struct bcm2835_pll_divider_data *data = divider->data; 786 u32 cm, div, max_div = 1 << A2W_PLL_DIV_BITS; 787 788 div = DIV_ROUND_UP_ULL(parent_rate, rate); 789 790 div = min(div, max_div); 791 if (div == max_div) 792 div = 0; 793 794 cprman_write(cprman, data->a2w_reg, div); 795 cm = cprman_read(cprman, data->cm_reg); 796 cprman_write(cprman, data->cm_reg, cm | data->load_mask); 797 cprman_write(cprman, data->cm_reg, cm & ~data->load_mask); 798 799 return 0; 800 } 801 802 static int bcm2835_pll_divider_debug_init(struct clk_hw *hw, 803 struct dentry *dentry) 804 { 805 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); 806 struct bcm2835_cprman *cprman = divider->cprman; 807 const struct bcm2835_pll_divider_data *data = divider->data; 808 struct debugfs_reg32 *regs; 809 810 regs = devm_kzalloc(cprman->dev, 7 * sizeof(*regs), GFP_KERNEL); 811 if (!regs) 812 return -ENOMEM; 813 814 regs[0].name = "cm"; 815 regs[0].offset = data->cm_reg; 816 regs[1].name = "a2w"; 817 regs[1].offset = data->a2w_reg; 818 819 return bcm2835_debugfs_regset(cprman, 0, regs, 2, dentry); 820 } 821 822 static const struct clk_ops bcm2835_pll_divider_clk_ops = { 823 .is_prepared = bcm2835_pll_divider_is_on, 824 .prepare = bcm2835_pll_divider_on, 825 .unprepare = bcm2835_pll_divider_off, 826 .recalc_rate = bcm2835_pll_divider_get_rate, 827 .set_rate = bcm2835_pll_divider_set_rate, 828 .round_rate = bcm2835_pll_divider_round_rate, 829 .debug_init = bcm2835_pll_divider_debug_init, 830 }; 831 832 /* 833 * The CM dividers do fixed-point division, so we can't use the 834 * generic integer divider code like the PLL dividers do (and we can't 835 * fake it by having some fixed shifts preceding it in the clock tree, 836 * because we'd run out of bits in a 32-bit unsigned long). 837 */ 838 struct bcm2835_clock { 839 struct clk_hw hw; 840 struct bcm2835_cprman *cprman; 841 const struct bcm2835_clock_data *data; 842 }; 843 844 static struct bcm2835_clock *bcm2835_clock_from_hw(struct clk_hw *hw) 845 { 846 return container_of(hw, struct bcm2835_clock, hw); 847 } 848 849 static int bcm2835_clock_is_on(struct clk_hw *hw) 850 { 851 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 852 struct bcm2835_cprman *cprman = clock->cprman; 853 const struct bcm2835_clock_data *data = clock->data; 854 855 return (cprman_read(cprman, data->ctl_reg) & CM_ENABLE) != 0; 856 } 857 858 static u32 bcm2835_clock_choose_div(struct clk_hw *hw, 859 unsigned long rate, 860 unsigned long parent_rate, 861 bool round_up) 862 { 863 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 864 const struct bcm2835_clock_data *data = clock->data; 865 u32 unused_frac_mask = 866 GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1; 867 u64 temp = (u64)parent_rate << CM_DIV_FRAC_BITS; 868 u64 rem; 869 u32 div, mindiv, maxdiv; 870 871 rem = do_div(temp, rate); 872 div = temp; 873 874 /* Round up and mask off the unused bits */ 875 if (round_up && ((div & unused_frac_mask) != 0 || rem != 0)) 876 div += unused_frac_mask + 1; 877 div &= ~unused_frac_mask; 878 879 /* different clamping limits apply for a mash clock */ 880 if (data->is_mash_clock) { 881 /* clamp to min divider of 2 */ 882 mindiv = 2 << CM_DIV_FRAC_BITS; 883 /* clamp to the highest possible integer divider */ 884 maxdiv = (BIT(data->int_bits) - 1) << CM_DIV_FRAC_BITS; 885 } else { 886 /* clamp to min divider of 1 */ 887 mindiv = 1 << CM_DIV_FRAC_BITS; 888 /* clamp to the highest possible fractional divider */ 889 maxdiv = GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1, 890 CM_DIV_FRAC_BITS - data->frac_bits); 891 } 892 893 /* apply the clamping limits */ 894 div = max_t(u32, div, mindiv); 895 div = min_t(u32, div, maxdiv); 896 897 return div; 898 } 899 900 static long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock, 901 unsigned long parent_rate, 902 u32 div) 903 { 904 const struct bcm2835_clock_data *data = clock->data; 905 u64 temp; 906 907 /* 908 * The divisor is a 12.12 fixed point field, but only some of 909 * the bits are populated in any given clock. 910 */ 911 div >>= CM_DIV_FRAC_BITS - data->frac_bits; 912 div &= (1 << (data->int_bits + data->frac_bits)) - 1; 913 914 if (div == 0) 915 return 0; 916 917 temp = (u64)parent_rate << data->frac_bits; 918 919 do_div(temp, div); 920 921 return temp; 922 } 923 924 static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw, 925 unsigned long parent_rate) 926 { 927 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 928 struct bcm2835_cprman *cprman = clock->cprman; 929 const struct bcm2835_clock_data *data = clock->data; 930 u32 div = cprman_read(cprman, data->div_reg); 931 932 return bcm2835_clock_rate_from_divisor(clock, parent_rate, div); 933 } 934 935 static void bcm2835_clock_wait_busy(struct bcm2835_clock *clock) 936 { 937 struct bcm2835_cprman *cprman = clock->cprman; 938 const struct bcm2835_clock_data *data = clock->data; 939 ktime_t timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS); 940 941 while (cprman_read(cprman, data->ctl_reg) & CM_BUSY) { 942 if (ktime_after(ktime_get(), timeout)) { 943 dev_err(cprman->dev, "%s: couldn't lock PLL\n", 944 clk_hw_get_name(&clock->hw)); 945 return; 946 } 947 cpu_relax(); 948 } 949 } 950 951 static void bcm2835_clock_off(struct clk_hw *hw) 952 { 953 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 954 struct bcm2835_cprman *cprman = clock->cprman; 955 const struct bcm2835_clock_data *data = clock->data; 956 957 spin_lock(&cprman->regs_lock); 958 cprman_write(cprman, data->ctl_reg, 959 cprman_read(cprman, data->ctl_reg) & ~CM_ENABLE); 960 spin_unlock(&cprman->regs_lock); 961 962 /* BUSY will remain high until the divider completes its cycle. */ 963 bcm2835_clock_wait_busy(clock); 964 } 965 966 static int bcm2835_clock_on(struct clk_hw *hw) 967 { 968 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 969 struct bcm2835_cprman *cprman = clock->cprman; 970 const struct bcm2835_clock_data *data = clock->data; 971 972 spin_lock(&cprman->regs_lock); 973 cprman_write(cprman, data->ctl_reg, 974 cprman_read(cprman, data->ctl_reg) | 975 CM_ENABLE | 976 CM_GATE); 977 spin_unlock(&cprman->regs_lock); 978 979 return 0; 980 } 981 982 static int bcm2835_clock_set_rate(struct clk_hw *hw, 983 unsigned long rate, unsigned long parent_rate) 984 { 985 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 986 struct bcm2835_cprman *cprman = clock->cprman; 987 const struct bcm2835_clock_data *data = clock->data; 988 u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate, false); 989 u32 ctl; 990 991 spin_lock(&cprman->regs_lock); 992 993 /* 994 * Setting up frac support 995 * 996 * In principle it is recommended to stop/start the clock first, 997 * but as we set CLK_SET_RATE_GATE during registration of the 998 * clock this requirement should be take care of by the 999 * clk-framework. 1000 */ 1001 ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC; 1002 ctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0; 1003 cprman_write(cprman, data->ctl_reg, ctl); 1004 1005 cprman_write(cprman, data->div_reg, div); 1006 1007 spin_unlock(&cprman->regs_lock); 1008 1009 return 0; 1010 } 1011 1012 static bool 1013 bcm2835_clk_is_pllc(struct clk_hw *hw) 1014 { 1015 if (!hw) 1016 return false; 1017 1018 return strncmp(clk_hw_get_name(hw), "pllc", 4) == 0; 1019 } 1020 1021 static int bcm2835_clock_determine_rate(struct clk_hw *hw, 1022 struct clk_rate_request *req) 1023 { 1024 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 1025 struct clk_hw *parent, *best_parent = NULL; 1026 bool current_parent_is_pllc; 1027 unsigned long rate, best_rate = 0; 1028 unsigned long prate, best_prate = 0; 1029 size_t i; 1030 u32 div; 1031 1032 current_parent_is_pllc = bcm2835_clk_is_pllc(clk_hw_get_parent(hw)); 1033 1034 /* 1035 * Select parent clock that results in the closest but lower rate 1036 */ 1037 for (i = 0; i < clk_hw_get_num_parents(hw); ++i) { 1038 parent = clk_hw_get_parent_by_index(hw, i); 1039 if (!parent) 1040 continue; 1041 1042 /* 1043 * Don't choose a PLLC-derived clock as our parent 1044 * unless it had been manually set that way. PLLC's 1045 * frequency gets adjusted by the firmware due to 1046 * over-temp or under-voltage conditions, without 1047 * prior notification to our clock consumer. 1048 */ 1049 if (bcm2835_clk_is_pllc(parent) && !current_parent_is_pllc) 1050 continue; 1051 1052 prate = clk_hw_get_rate(parent); 1053 div = bcm2835_clock_choose_div(hw, req->rate, prate, true); 1054 rate = bcm2835_clock_rate_from_divisor(clock, prate, div); 1055 if (rate > best_rate && rate <= req->rate) { 1056 best_parent = parent; 1057 best_prate = prate; 1058 best_rate = rate; 1059 } 1060 } 1061 1062 if (!best_parent) 1063 return -EINVAL; 1064 1065 req->best_parent_hw = best_parent; 1066 req->best_parent_rate = best_prate; 1067 1068 req->rate = best_rate; 1069 1070 return 0; 1071 } 1072 1073 static int bcm2835_clock_set_parent(struct clk_hw *hw, u8 index) 1074 { 1075 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 1076 struct bcm2835_cprman *cprman = clock->cprman; 1077 const struct bcm2835_clock_data *data = clock->data; 1078 u8 src = (index << CM_SRC_SHIFT) & CM_SRC_MASK; 1079 1080 cprman_write(cprman, data->ctl_reg, src); 1081 return 0; 1082 } 1083 1084 static u8 bcm2835_clock_get_parent(struct clk_hw *hw) 1085 { 1086 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 1087 struct bcm2835_cprman *cprman = clock->cprman; 1088 const struct bcm2835_clock_data *data = clock->data; 1089 u32 src = cprman_read(cprman, data->ctl_reg); 1090 1091 return (src & CM_SRC_MASK) >> CM_SRC_SHIFT; 1092 } 1093 1094 static struct debugfs_reg32 bcm2835_debugfs_clock_reg32[] = { 1095 { 1096 .name = "ctl", 1097 .offset = 0, 1098 }, 1099 { 1100 .name = "div", 1101 .offset = 4, 1102 }, 1103 }; 1104 1105 static int bcm2835_clock_debug_init(struct clk_hw *hw, 1106 struct dentry *dentry) 1107 { 1108 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 1109 struct bcm2835_cprman *cprman = clock->cprman; 1110 const struct bcm2835_clock_data *data = clock->data; 1111 1112 return bcm2835_debugfs_regset( 1113 cprman, data->ctl_reg, 1114 bcm2835_debugfs_clock_reg32, 1115 ARRAY_SIZE(bcm2835_debugfs_clock_reg32), 1116 dentry); 1117 } 1118 1119 static const struct clk_ops bcm2835_clock_clk_ops = { 1120 .is_prepared = bcm2835_clock_is_on, 1121 .prepare = bcm2835_clock_on, 1122 .unprepare = bcm2835_clock_off, 1123 .recalc_rate = bcm2835_clock_get_rate, 1124 .set_rate = bcm2835_clock_set_rate, 1125 .determine_rate = bcm2835_clock_determine_rate, 1126 .set_parent = bcm2835_clock_set_parent, 1127 .get_parent = bcm2835_clock_get_parent, 1128 .debug_init = bcm2835_clock_debug_init, 1129 }; 1130 1131 static int bcm2835_vpu_clock_is_on(struct clk_hw *hw) 1132 { 1133 return true; 1134 } 1135 1136 /* 1137 * The VPU clock can never be disabled (it doesn't have an ENABLE 1138 * bit), so it gets its own set of clock ops. 1139 */ 1140 static const struct clk_ops bcm2835_vpu_clock_clk_ops = { 1141 .is_prepared = bcm2835_vpu_clock_is_on, 1142 .recalc_rate = bcm2835_clock_get_rate, 1143 .set_rate = bcm2835_clock_set_rate, 1144 .determine_rate = bcm2835_clock_determine_rate, 1145 .set_parent = bcm2835_clock_set_parent, 1146 .get_parent = bcm2835_clock_get_parent, 1147 .debug_init = bcm2835_clock_debug_init, 1148 }; 1149 1150 static struct clk_hw *bcm2835_register_pll(struct bcm2835_cprman *cprman, 1151 const struct bcm2835_pll_data *data) 1152 { 1153 struct bcm2835_pll *pll; 1154 struct clk_init_data init; 1155 int ret; 1156 1157 memset(&init, 0, sizeof(init)); 1158 1159 /* All of the PLLs derive from the external oscillator. */ 1160 init.parent_names = &cprman->osc_name; 1161 init.num_parents = 1; 1162 init.name = data->name; 1163 init.ops = &bcm2835_pll_clk_ops; 1164 init.flags = CLK_IGNORE_UNUSED; 1165 1166 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 1167 if (!pll) 1168 return NULL; 1169 1170 pll->cprman = cprman; 1171 pll->data = data; 1172 pll->hw.init = &init; 1173 1174 ret = devm_clk_hw_register(cprman->dev, &pll->hw); 1175 if (ret) 1176 return NULL; 1177 return &pll->hw; 1178 } 1179 1180 static struct clk_hw * 1181 bcm2835_register_pll_divider(struct bcm2835_cprman *cprman, 1182 const struct bcm2835_pll_divider_data *data) 1183 { 1184 struct bcm2835_pll_divider *divider; 1185 struct clk_init_data init; 1186 const char *divider_name; 1187 int ret; 1188 1189 if (data->fixed_divider != 1) { 1190 divider_name = devm_kasprintf(cprman->dev, GFP_KERNEL, 1191 "%s_prediv", data->name); 1192 if (!divider_name) 1193 return NULL; 1194 } else { 1195 divider_name = data->name; 1196 } 1197 1198 memset(&init, 0, sizeof(init)); 1199 1200 init.parent_names = &data->source_pll; 1201 init.num_parents = 1; 1202 init.name = divider_name; 1203 init.ops = &bcm2835_pll_divider_clk_ops; 1204 init.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED; 1205 1206 divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL); 1207 if (!divider) 1208 return NULL; 1209 1210 divider->div.reg = cprman->regs + data->a2w_reg; 1211 divider->div.shift = A2W_PLL_DIV_SHIFT; 1212 divider->div.width = A2W_PLL_DIV_BITS; 1213 divider->div.flags = CLK_DIVIDER_MAX_AT_ZERO; 1214 divider->div.lock = &cprman->regs_lock; 1215 divider->div.hw.init = &init; 1216 divider->div.table = NULL; 1217 1218 divider->cprman = cprman; 1219 divider->data = data; 1220 1221 ret = devm_clk_hw_register(cprman->dev, ÷r->div.hw); 1222 if (ret) 1223 return ERR_PTR(ret); 1224 1225 /* 1226 * PLLH's channels have a fixed divide by 10 afterwards, which 1227 * is what our consumers are actually using. 1228 */ 1229 if (data->fixed_divider != 1) { 1230 return clk_hw_register_fixed_factor(cprman->dev, data->name, 1231 divider_name, 1232 CLK_SET_RATE_PARENT, 1233 1, 1234 data->fixed_divider); 1235 } 1236 1237 return ÷r->div.hw; 1238 } 1239 1240 static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman, 1241 const struct bcm2835_clock_data *data) 1242 { 1243 struct bcm2835_clock *clock; 1244 struct clk_init_data init; 1245 const char *parents[1 << CM_SRC_BITS]; 1246 size_t i; 1247 int ret; 1248 1249 /* 1250 * Replace our "xosc" references with the oscillator's 1251 * actual name. 1252 */ 1253 for (i = 0; i < data->num_mux_parents; i++) { 1254 if (strcmp(data->parents[i], "xosc") == 0) 1255 parents[i] = cprman->osc_name; 1256 else 1257 parents[i] = data->parents[i]; 1258 } 1259 1260 memset(&init, 0, sizeof(init)); 1261 init.parent_names = parents; 1262 init.num_parents = data->num_mux_parents; 1263 init.name = data->name; 1264 init.flags = data->flags | CLK_IGNORE_UNUSED; 1265 1266 if (data->is_vpu_clock) { 1267 init.ops = &bcm2835_vpu_clock_clk_ops; 1268 } else { 1269 init.ops = &bcm2835_clock_clk_ops; 1270 init.flags |= CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; 1271 1272 /* If the clock wasn't actually enabled at boot, it's not 1273 * critical. 1274 */ 1275 if (!(cprman_read(cprman, data->ctl_reg) & CM_ENABLE)) 1276 init.flags &= ~CLK_IS_CRITICAL; 1277 } 1278 1279 clock = devm_kzalloc(cprman->dev, sizeof(*clock), GFP_KERNEL); 1280 if (!clock) 1281 return NULL; 1282 1283 clock->cprman = cprman; 1284 clock->data = data; 1285 clock->hw.init = &init; 1286 1287 ret = devm_clk_hw_register(cprman->dev, &clock->hw); 1288 if (ret) 1289 return ERR_PTR(ret); 1290 return &clock->hw; 1291 } 1292 1293 static struct clk *bcm2835_register_gate(struct bcm2835_cprman *cprman, 1294 const struct bcm2835_gate_data *data) 1295 { 1296 return clk_register_gate(cprman->dev, data->name, data->parent, 1297 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 1298 cprman->regs + data->ctl_reg, 1299 CM_GATE_BIT, 0, &cprman->regs_lock); 1300 } 1301 1302 typedef struct clk_hw *(*bcm2835_clk_register)(struct bcm2835_cprman *cprman, 1303 const void *data); 1304 struct bcm2835_clk_desc { 1305 bcm2835_clk_register clk_register; 1306 const void *data; 1307 }; 1308 1309 /* assignment helper macros for different clock types */ 1310 #define _REGISTER(f, ...) { .clk_register = (bcm2835_clk_register)f, \ 1311 .data = __VA_ARGS__ } 1312 #define REGISTER_PLL(...) _REGISTER(&bcm2835_register_pll, \ 1313 &(struct bcm2835_pll_data) \ 1314 {__VA_ARGS__}) 1315 #define REGISTER_PLL_DIV(...) _REGISTER(&bcm2835_register_pll_divider, \ 1316 &(struct bcm2835_pll_divider_data) \ 1317 {__VA_ARGS__}) 1318 #define REGISTER_CLK(...) _REGISTER(&bcm2835_register_clock, \ 1319 &(struct bcm2835_clock_data) \ 1320 {__VA_ARGS__}) 1321 #define REGISTER_GATE(...) _REGISTER(&bcm2835_register_gate, \ 1322 &(struct bcm2835_gate_data) \ 1323 {__VA_ARGS__}) 1324 1325 /* parent mux arrays plus helper macros */ 1326 1327 /* main oscillator parent mux */ 1328 static const char *const bcm2835_clock_osc_parents[] = { 1329 "gnd", 1330 "xosc", 1331 "testdebug0", 1332 "testdebug1" 1333 }; 1334 1335 #define REGISTER_OSC_CLK(...) REGISTER_CLK( \ 1336 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents), \ 1337 .parents = bcm2835_clock_osc_parents, \ 1338 __VA_ARGS__) 1339 1340 /* main peripherial parent mux */ 1341 static const char *const bcm2835_clock_per_parents[] = { 1342 "gnd", 1343 "xosc", 1344 "testdebug0", 1345 "testdebug1", 1346 "plla_per", 1347 "pllc_per", 1348 "plld_per", 1349 "pllh_aux", 1350 }; 1351 1352 #define REGISTER_PER_CLK(...) REGISTER_CLK( \ 1353 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), \ 1354 .parents = bcm2835_clock_per_parents, \ 1355 __VA_ARGS__) 1356 1357 /* main vpu parent mux */ 1358 static const char *const bcm2835_clock_vpu_parents[] = { 1359 "gnd", 1360 "xosc", 1361 "testdebug0", 1362 "testdebug1", 1363 "plla_core", 1364 "pllc_core0", 1365 "plld_core", 1366 "pllh_aux", 1367 "pllc_core1", 1368 "pllc_core2", 1369 }; 1370 1371 #define REGISTER_VPU_CLK(...) REGISTER_CLK( \ 1372 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), \ 1373 .parents = bcm2835_clock_vpu_parents, \ 1374 __VA_ARGS__) 1375 1376 /* 1377 * the real definition of all the pll, pll_dividers and clocks 1378 * these make use of the above REGISTER_* macros 1379 */ 1380 static const struct bcm2835_clk_desc clk_desc_array[] = { 1381 /* the PLL + PLL dividers */ 1382 1383 /* 1384 * PLLA is the auxiliary PLL, used to drive the CCP2 1385 * (Compact Camera Port 2) transmitter clock. 1386 * 1387 * It is in the PX LDO power domain, which is on when the 1388 * AUDIO domain is on. 1389 */ 1390 [BCM2835_PLLA] = REGISTER_PLL( 1391 .name = "plla", 1392 .cm_ctrl_reg = CM_PLLA, 1393 .a2w_ctrl_reg = A2W_PLLA_CTRL, 1394 .frac_reg = A2W_PLLA_FRAC, 1395 .ana_reg_base = A2W_PLLA_ANA0, 1396 .reference_enable_mask = A2W_XOSC_CTRL_PLLA_ENABLE, 1397 .lock_mask = CM_LOCK_FLOCKA, 1398 1399 .ana = &bcm2835_ana_default, 1400 1401 .min_rate = 600000000u, 1402 .max_rate = 2400000000u, 1403 .max_fb_rate = BCM2835_MAX_FB_RATE), 1404 [BCM2835_PLLA_CORE] = REGISTER_PLL_DIV( 1405 .name = "plla_core", 1406 .source_pll = "plla", 1407 .cm_reg = CM_PLLA, 1408 .a2w_reg = A2W_PLLA_CORE, 1409 .load_mask = CM_PLLA_LOADCORE, 1410 .hold_mask = CM_PLLA_HOLDCORE, 1411 .fixed_divider = 1), 1412 [BCM2835_PLLA_PER] = REGISTER_PLL_DIV( 1413 .name = "plla_per", 1414 .source_pll = "plla", 1415 .cm_reg = CM_PLLA, 1416 .a2w_reg = A2W_PLLA_PER, 1417 .load_mask = CM_PLLA_LOADPER, 1418 .hold_mask = CM_PLLA_HOLDPER, 1419 .fixed_divider = 1), 1420 [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV( 1421 .name = "plla_dsi0", 1422 .source_pll = "plla", 1423 .cm_reg = CM_PLLA, 1424 .a2w_reg = A2W_PLLA_DSI0, 1425 .load_mask = CM_PLLA_LOADDSI0, 1426 .hold_mask = CM_PLLA_HOLDDSI0, 1427 .fixed_divider = 1), 1428 [BCM2835_PLLA_CCP2] = REGISTER_PLL_DIV( 1429 .name = "plla_ccp2", 1430 .source_pll = "plla", 1431 .cm_reg = CM_PLLA, 1432 .a2w_reg = A2W_PLLA_CCP2, 1433 .load_mask = CM_PLLA_LOADCCP2, 1434 .hold_mask = CM_PLLA_HOLDCCP2, 1435 .fixed_divider = 1), 1436 1437 /* PLLB is used for the ARM's clock. */ 1438 [BCM2835_PLLB] = REGISTER_PLL( 1439 .name = "pllb", 1440 .cm_ctrl_reg = CM_PLLB, 1441 .a2w_ctrl_reg = A2W_PLLB_CTRL, 1442 .frac_reg = A2W_PLLB_FRAC, 1443 .ana_reg_base = A2W_PLLB_ANA0, 1444 .reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE, 1445 .lock_mask = CM_LOCK_FLOCKB, 1446 1447 .ana = &bcm2835_ana_default, 1448 1449 .min_rate = 600000000u, 1450 .max_rate = 3000000000u, 1451 .max_fb_rate = BCM2835_MAX_FB_RATE), 1452 [BCM2835_PLLB_ARM] = REGISTER_PLL_DIV( 1453 .name = "pllb_arm", 1454 .source_pll = "pllb", 1455 .cm_reg = CM_PLLB, 1456 .a2w_reg = A2W_PLLB_ARM, 1457 .load_mask = CM_PLLB_LOADARM, 1458 .hold_mask = CM_PLLB_HOLDARM, 1459 .fixed_divider = 1), 1460 1461 /* 1462 * PLLC is the core PLL, used to drive the core VPU clock. 1463 * 1464 * It is in the PX LDO power domain, which is on when the 1465 * AUDIO domain is on. 1466 */ 1467 [BCM2835_PLLC] = REGISTER_PLL( 1468 .name = "pllc", 1469 .cm_ctrl_reg = CM_PLLC, 1470 .a2w_ctrl_reg = A2W_PLLC_CTRL, 1471 .frac_reg = A2W_PLLC_FRAC, 1472 .ana_reg_base = A2W_PLLC_ANA0, 1473 .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE, 1474 .lock_mask = CM_LOCK_FLOCKC, 1475 1476 .ana = &bcm2835_ana_default, 1477 1478 .min_rate = 600000000u, 1479 .max_rate = 3000000000u, 1480 .max_fb_rate = BCM2835_MAX_FB_RATE), 1481 [BCM2835_PLLC_CORE0] = REGISTER_PLL_DIV( 1482 .name = "pllc_core0", 1483 .source_pll = "pllc", 1484 .cm_reg = CM_PLLC, 1485 .a2w_reg = A2W_PLLC_CORE0, 1486 .load_mask = CM_PLLC_LOADCORE0, 1487 .hold_mask = CM_PLLC_HOLDCORE0, 1488 .fixed_divider = 1), 1489 [BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV( 1490 .name = "pllc_core1", 1491 .source_pll = "pllc", 1492 .cm_reg = CM_PLLC, 1493 .a2w_reg = A2W_PLLC_CORE1, 1494 .load_mask = CM_PLLC_LOADCORE1, 1495 .hold_mask = CM_PLLC_HOLDCORE1, 1496 .fixed_divider = 1), 1497 [BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV( 1498 .name = "pllc_core2", 1499 .source_pll = "pllc", 1500 .cm_reg = CM_PLLC, 1501 .a2w_reg = A2W_PLLC_CORE2, 1502 .load_mask = CM_PLLC_LOADCORE2, 1503 .hold_mask = CM_PLLC_HOLDCORE2, 1504 .fixed_divider = 1), 1505 [BCM2835_PLLC_PER] = REGISTER_PLL_DIV( 1506 .name = "pllc_per", 1507 .source_pll = "pllc", 1508 .cm_reg = CM_PLLC, 1509 .a2w_reg = A2W_PLLC_PER, 1510 .load_mask = CM_PLLC_LOADPER, 1511 .hold_mask = CM_PLLC_HOLDPER, 1512 .fixed_divider = 1), 1513 1514 /* 1515 * PLLD is the display PLL, used to drive DSI display panels. 1516 * 1517 * It is in the PX LDO power domain, which is on when the 1518 * AUDIO domain is on. 1519 */ 1520 [BCM2835_PLLD] = REGISTER_PLL( 1521 .name = "plld", 1522 .cm_ctrl_reg = CM_PLLD, 1523 .a2w_ctrl_reg = A2W_PLLD_CTRL, 1524 .frac_reg = A2W_PLLD_FRAC, 1525 .ana_reg_base = A2W_PLLD_ANA0, 1526 .reference_enable_mask = A2W_XOSC_CTRL_DDR_ENABLE, 1527 .lock_mask = CM_LOCK_FLOCKD, 1528 1529 .ana = &bcm2835_ana_default, 1530 1531 .min_rate = 600000000u, 1532 .max_rate = 2400000000u, 1533 .max_fb_rate = BCM2835_MAX_FB_RATE), 1534 [BCM2835_PLLD_CORE] = REGISTER_PLL_DIV( 1535 .name = "plld_core", 1536 .source_pll = "plld", 1537 .cm_reg = CM_PLLD, 1538 .a2w_reg = A2W_PLLD_CORE, 1539 .load_mask = CM_PLLD_LOADCORE, 1540 .hold_mask = CM_PLLD_HOLDCORE, 1541 .fixed_divider = 1), 1542 [BCM2835_PLLD_PER] = REGISTER_PLL_DIV( 1543 .name = "plld_per", 1544 .source_pll = "plld", 1545 .cm_reg = CM_PLLD, 1546 .a2w_reg = A2W_PLLD_PER, 1547 .load_mask = CM_PLLD_LOADPER, 1548 .hold_mask = CM_PLLD_HOLDPER, 1549 .fixed_divider = 1), 1550 [BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV( 1551 .name = "plld_dsi0", 1552 .source_pll = "plld", 1553 .cm_reg = CM_PLLD, 1554 .a2w_reg = A2W_PLLD_DSI0, 1555 .load_mask = CM_PLLD_LOADDSI0, 1556 .hold_mask = CM_PLLD_HOLDDSI0, 1557 .fixed_divider = 1), 1558 [BCM2835_PLLD_DSI1] = REGISTER_PLL_DIV( 1559 .name = "plld_dsi1", 1560 .source_pll = "plld", 1561 .cm_reg = CM_PLLD, 1562 .a2w_reg = A2W_PLLD_DSI1, 1563 .load_mask = CM_PLLD_LOADDSI1, 1564 .hold_mask = CM_PLLD_HOLDDSI1, 1565 .fixed_divider = 1), 1566 1567 /* 1568 * PLLH is used to supply the pixel clock or the AUX clock for the 1569 * TV encoder. 1570 * 1571 * It is in the HDMI power domain. 1572 */ 1573 [BCM2835_PLLH] = REGISTER_PLL( 1574 "pllh", 1575 .cm_ctrl_reg = CM_PLLH, 1576 .a2w_ctrl_reg = A2W_PLLH_CTRL, 1577 .frac_reg = A2W_PLLH_FRAC, 1578 .ana_reg_base = A2W_PLLH_ANA0, 1579 .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE, 1580 .lock_mask = CM_LOCK_FLOCKH, 1581 1582 .ana = &bcm2835_ana_pllh, 1583 1584 .min_rate = 600000000u, 1585 .max_rate = 3000000000u, 1586 .max_fb_rate = BCM2835_MAX_FB_RATE), 1587 [BCM2835_PLLH_RCAL] = REGISTER_PLL_DIV( 1588 .name = "pllh_rcal", 1589 .source_pll = "pllh", 1590 .cm_reg = CM_PLLH, 1591 .a2w_reg = A2W_PLLH_RCAL, 1592 .load_mask = CM_PLLH_LOADRCAL, 1593 .hold_mask = 0, 1594 .fixed_divider = 10), 1595 [BCM2835_PLLH_AUX] = REGISTER_PLL_DIV( 1596 .name = "pllh_aux", 1597 .source_pll = "pllh", 1598 .cm_reg = CM_PLLH, 1599 .a2w_reg = A2W_PLLH_AUX, 1600 .load_mask = CM_PLLH_LOADAUX, 1601 .hold_mask = 0, 1602 .fixed_divider = 10), 1603 [BCM2835_PLLH_PIX] = REGISTER_PLL_DIV( 1604 .name = "pllh_pix", 1605 .source_pll = "pllh", 1606 .cm_reg = CM_PLLH, 1607 .a2w_reg = A2W_PLLH_PIX, 1608 .load_mask = CM_PLLH_LOADPIX, 1609 .hold_mask = 0, 1610 .fixed_divider = 10), 1611 1612 /* the clocks */ 1613 1614 /* clocks with oscillator parent mux */ 1615 1616 /* One Time Programmable Memory clock. Maximum 10Mhz. */ 1617 [BCM2835_CLOCK_OTP] = REGISTER_OSC_CLK( 1618 .name = "otp", 1619 .ctl_reg = CM_OTPCTL, 1620 .div_reg = CM_OTPDIV, 1621 .int_bits = 4, 1622 .frac_bits = 0), 1623 /* 1624 * Used for a 1Mhz clock for the system clocksource, and also used 1625 * bythe watchdog timer and the camera pulse generator. 1626 */ 1627 [BCM2835_CLOCK_TIMER] = REGISTER_OSC_CLK( 1628 .name = "timer", 1629 .ctl_reg = CM_TIMERCTL, 1630 .div_reg = CM_TIMERDIV, 1631 .int_bits = 6, 1632 .frac_bits = 12), 1633 /* 1634 * Clock for the temperature sensor. 1635 * Generally run at 2Mhz, max 5Mhz. 1636 */ 1637 [BCM2835_CLOCK_TSENS] = REGISTER_OSC_CLK( 1638 .name = "tsens", 1639 .ctl_reg = CM_TSENSCTL, 1640 .div_reg = CM_TSENSDIV, 1641 .int_bits = 5, 1642 .frac_bits = 0), 1643 [BCM2835_CLOCK_TEC] = REGISTER_OSC_CLK( 1644 .name = "tec", 1645 .ctl_reg = CM_TECCTL, 1646 .div_reg = CM_TECDIV, 1647 .int_bits = 6, 1648 .frac_bits = 0), 1649 1650 /* clocks with vpu parent mux */ 1651 [BCM2835_CLOCK_H264] = REGISTER_VPU_CLK( 1652 .name = "h264", 1653 .ctl_reg = CM_H264CTL, 1654 .div_reg = CM_H264DIV, 1655 .int_bits = 4, 1656 .frac_bits = 8), 1657 [BCM2835_CLOCK_ISP] = REGISTER_VPU_CLK( 1658 .name = "isp", 1659 .ctl_reg = CM_ISPCTL, 1660 .div_reg = CM_ISPDIV, 1661 .int_bits = 4, 1662 .frac_bits = 8), 1663 1664 /* 1665 * Secondary SDRAM clock. Used for low-voltage modes when the PLL 1666 * in the SDRAM controller can't be used. 1667 */ 1668 [BCM2835_CLOCK_SDRAM] = REGISTER_VPU_CLK( 1669 .name = "sdram", 1670 .ctl_reg = CM_SDCCTL, 1671 .div_reg = CM_SDCDIV, 1672 .int_bits = 6, 1673 .frac_bits = 0), 1674 [BCM2835_CLOCK_V3D] = REGISTER_VPU_CLK( 1675 .name = "v3d", 1676 .ctl_reg = CM_V3DCTL, 1677 .div_reg = CM_V3DDIV, 1678 .int_bits = 4, 1679 .frac_bits = 8), 1680 /* 1681 * VPU clock. This doesn't have an enable bit, since it drives 1682 * the bus for everything else, and is special so it doesn't need 1683 * to be gated for rate changes. It is also known as "clk_audio" 1684 * in various hardware documentation. 1685 */ 1686 [BCM2835_CLOCK_VPU] = REGISTER_VPU_CLK( 1687 .name = "vpu", 1688 .ctl_reg = CM_VPUCTL, 1689 .div_reg = CM_VPUDIV, 1690 .int_bits = 12, 1691 .frac_bits = 8, 1692 .flags = CLK_IS_CRITICAL, 1693 .is_vpu_clock = true), 1694 1695 /* clocks with per parent mux */ 1696 [BCM2835_CLOCK_AVEO] = REGISTER_PER_CLK( 1697 .name = "aveo", 1698 .ctl_reg = CM_AVEOCTL, 1699 .div_reg = CM_AVEODIV, 1700 .int_bits = 4, 1701 .frac_bits = 0), 1702 [BCM2835_CLOCK_CAM0] = REGISTER_PER_CLK( 1703 .name = "cam0", 1704 .ctl_reg = CM_CAM0CTL, 1705 .div_reg = CM_CAM0DIV, 1706 .int_bits = 4, 1707 .frac_bits = 8), 1708 [BCM2835_CLOCK_CAM1] = REGISTER_PER_CLK( 1709 .name = "cam1", 1710 .ctl_reg = CM_CAM1CTL, 1711 .div_reg = CM_CAM1DIV, 1712 .int_bits = 4, 1713 .frac_bits = 8), 1714 [BCM2835_CLOCK_DFT] = REGISTER_PER_CLK( 1715 .name = "dft", 1716 .ctl_reg = CM_DFTCTL, 1717 .div_reg = CM_DFTDIV, 1718 .int_bits = 5, 1719 .frac_bits = 0), 1720 [BCM2835_CLOCK_DPI] = REGISTER_PER_CLK( 1721 .name = "dpi", 1722 .ctl_reg = CM_DPICTL, 1723 .div_reg = CM_DPIDIV, 1724 .int_bits = 4, 1725 .frac_bits = 8), 1726 1727 /* Arasan EMMC clock */ 1728 [BCM2835_CLOCK_EMMC] = REGISTER_PER_CLK( 1729 .name = "emmc", 1730 .ctl_reg = CM_EMMCCTL, 1731 .div_reg = CM_EMMCDIV, 1732 .int_bits = 4, 1733 .frac_bits = 8), 1734 1735 /* General purpose (GPIO) clocks */ 1736 [BCM2835_CLOCK_GP0] = REGISTER_PER_CLK( 1737 .name = "gp0", 1738 .ctl_reg = CM_GP0CTL, 1739 .div_reg = CM_GP0DIV, 1740 .int_bits = 12, 1741 .frac_bits = 12, 1742 .is_mash_clock = true), 1743 [BCM2835_CLOCK_GP1] = REGISTER_PER_CLK( 1744 .name = "gp1", 1745 .ctl_reg = CM_GP1CTL, 1746 .div_reg = CM_GP1DIV, 1747 .int_bits = 12, 1748 .frac_bits = 12, 1749 .flags = CLK_IS_CRITICAL, 1750 .is_mash_clock = true), 1751 [BCM2835_CLOCK_GP2] = REGISTER_PER_CLK( 1752 .name = "gp2", 1753 .ctl_reg = CM_GP2CTL, 1754 .div_reg = CM_GP2DIV, 1755 .int_bits = 12, 1756 .frac_bits = 12, 1757 .flags = CLK_IS_CRITICAL), 1758 1759 /* HDMI state machine */ 1760 [BCM2835_CLOCK_HSM] = REGISTER_PER_CLK( 1761 .name = "hsm", 1762 .ctl_reg = CM_HSMCTL, 1763 .div_reg = CM_HSMDIV, 1764 .int_bits = 4, 1765 .frac_bits = 8), 1766 [BCM2835_CLOCK_PCM] = REGISTER_PER_CLK( 1767 .name = "pcm", 1768 .ctl_reg = CM_PCMCTL, 1769 .div_reg = CM_PCMDIV, 1770 .int_bits = 12, 1771 .frac_bits = 12, 1772 .is_mash_clock = true), 1773 [BCM2835_CLOCK_PWM] = REGISTER_PER_CLK( 1774 .name = "pwm", 1775 .ctl_reg = CM_PWMCTL, 1776 .div_reg = CM_PWMDIV, 1777 .int_bits = 12, 1778 .frac_bits = 12, 1779 .is_mash_clock = true), 1780 [BCM2835_CLOCK_SLIM] = REGISTER_PER_CLK( 1781 .name = "slim", 1782 .ctl_reg = CM_SLIMCTL, 1783 .div_reg = CM_SLIMDIV, 1784 .int_bits = 12, 1785 .frac_bits = 12, 1786 .is_mash_clock = true), 1787 [BCM2835_CLOCK_SMI] = REGISTER_PER_CLK( 1788 .name = "smi", 1789 .ctl_reg = CM_SMICTL, 1790 .div_reg = CM_SMIDIV, 1791 .int_bits = 4, 1792 .frac_bits = 8), 1793 [BCM2835_CLOCK_UART] = REGISTER_PER_CLK( 1794 .name = "uart", 1795 .ctl_reg = CM_UARTCTL, 1796 .div_reg = CM_UARTDIV, 1797 .int_bits = 10, 1798 .frac_bits = 12), 1799 1800 /* TV encoder clock. Only operating frequency is 108Mhz. */ 1801 [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK( 1802 .name = "vec", 1803 .ctl_reg = CM_VECCTL, 1804 .div_reg = CM_VECDIV, 1805 .int_bits = 4, 1806 .frac_bits = 0), 1807 1808 /* dsi clocks */ 1809 [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK( 1810 .name = "dsi0e", 1811 .ctl_reg = CM_DSI0ECTL, 1812 .div_reg = CM_DSI0EDIV, 1813 .int_bits = 4, 1814 .frac_bits = 8), 1815 [BCM2835_CLOCK_DSI1E] = REGISTER_PER_CLK( 1816 .name = "dsi1e", 1817 .ctl_reg = CM_DSI1ECTL, 1818 .div_reg = CM_DSI1EDIV, 1819 .int_bits = 4, 1820 .frac_bits = 8), 1821 1822 /* the gates */ 1823 1824 /* 1825 * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if 1826 * you have the debug bit set in the power manager, which we 1827 * don't bother exposing) are individual gates off of the 1828 * non-stop vpu clock. 1829 */ 1830 [BCM2835_CLOCK_PERI_IMAGE] = REGISTER_GATE( 1831 .name = "peri_image", 1832 .parent = "vpu", 1833 .ctl_reg = CM_PERIICTL), 1834 }; 1835 1836 /* 1837 * Permanently take a reference on the parent of the SDRAM clock. 1838 * 1839 * While the SDRAM is being driven by its dedicated PLL most of the 1840 * time, there is a little loop running in the firmware that 1841 * periodically switches the SDRAM to using our CM clock to do PVT 1842 * recalibration, with the assumption that the previously configured 1843 * SDRAM parent is still enabled and running. 1844 */ 1845 static int bcm2835_mark_sdc_parent_critical(struct clk *sdc) 1846 { 1847 struct clk *parent = clk_get_parent(sdc); 1848 1849 if (IS_ERR(parent)) 1850 return PTR_ERR(parent); 1851 1852 return clk_prepare_enable(parent); 1853 } 1854 1855 static int bcm2835_clk_probe(struct platform_device *pdev) 1856 { 1857 struct device *dev = &pdev->dev; 1858 struct clk_hw **hws; 1859 struct bcm2835_cprman *cprman; 1860 struct resource *res; 1861 const struct bcm2835_clk_desc *desc; 1862 const size_t asize = ARRAY_SIZE(clk_desc_array); 1863 size_t i; 1864 int ret; 1865 1866 cprman = devm_kzalloc(dev, sizeof(*cprman) + 1867 sizeof(*cprman->onecell.hws) * asize, 1868 GFP_KERNEL); 1869 if (!cprman) 1870 return -ENOMEM; 1871 1872 spin_lock_init(&cprman->regs_lock); 1873 cprman->dev = dev; 1874 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1875 cprman->regs = devm_ioremap_resource(dev, res); 1876 if (IS_ERR(cprman->regs)) 1877 return PTR_ERR(cprman->regs); 1878 1879 cprman->osc_name = of_clk_get_parent_name(dev->of_node, 0); 1880 if (!cprman->osc_name) 1881 return -ENODEV; 1882 1883 platform_set_drvdata(pdev, cprman); 1884 1885 cprman->onecell.num = asize; 1886 hws = cprman->onecell.hws; 1887 1888 for (i = 0; i < asize; i++) { 1889 desc = &clk_desc_array[i]; 1890 if (desc->clk_register && desc->data) 1891 hws[i] = desc->clk_register(cprman, desc->data); 1892 } 1893 1894 ret = bcm2835_mark_sdc_parent_critical(hws[BCM2835_CLOCK_SDRAM]->clk); 1895 if (ret) 1896 return ret; 1897 1898 return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, 1899 &cprman->onecell); 1900 } 1901 1902 static const struct of_device_id bcm2835_clk_of_match[] = { 1903 { .compatible = "brcm,bcm2835-cprman", }, 1904 {} 1905 }; 1906 MODULE_DEVICE_TABLE(of, bcm2835_clk_of_match); 1907 1908 static struct platform_driver bcm2835_clk_driver = { 1909 .driver = { 1910 .name = "bcm2835-clk", 1911 .of_match_table = bcm2835_clk_of_match, 1912 }, 1913 .probe = bcm2835_clk_probe, 1914 }; 1915 1916 builtin_platform_driver(bcm2835_clk_driver); 1917 1918 MODULE_AUTHOR("Eric Anholt <eric@anholt.net>"); 1919 MODULE_DESCRIPTION("BCM2835 clock driver"); 1920 MODULE_LICENSE("GPL v2"); 1921