1 /* 2 * Copyright (C) 2010,2015 Broadcom 3 * Copyright (C) 2012 Stephen Warren 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 */ 16 17 /** 18 * DOC: BCM2835 CPRMAN (clock manager for the "audio" domain) 19 * 20 * The clock tree on the 2835 has several levels. There's a root 21 * oscillator running at 19.2Mhz. After the oscillator there are 5 22 * PLLs, roughly divided as "camera", "ARM", "core", "DSI displays", 23 * and "HDMI displays". Those 5 PLLs each can divide their output to 24 * produce up to 4 channels. Finally, there is the level of clocks to 25 * be consumed by other hardware components (like "H264" or "HDMI 26 * state machine"), which divide off of some subset of the PLL 27 * channels. 28 * 29 * All of the clocks in the tree are exposed in the DT, because the DT 30 * may want to make assignments of the final layer of clocks to the 31 * PLL channels, and some components of the hardware will actually 32 * skip layers of the tree (for example, the pixel clock comes 33 * directly from the PLLH PIX channel without using a CM_*CTL clock 34 * generator). 35 */ 36 37 #include <linux/clk-provider.h> 38 #include <linux/clkdev.h> 39 #include <linux/clk.h> 40 #include <linux/clk/bcm2835.h> 41 #include <linux/debugfs.h> 42 #include <linux/module.h> 43 #include <linux/of.h> 44 #include <linux/platform_device.h> 45 #include <linux/slab.h> 46 #include <dt-bindings/clock/bcm2835.h> 47 48 #define CM_PASSWORD 0x5a000000 49 50 #define CM_GNRICCTL 0x000 51 #define CM_GNRICDIV 0x004 52 # define CM_DIV_FRAC_BITS 12 53 # define CM_DIV_FRAC_MASK GENMASK(CM_DIV_FRAC_BITS - 1, 0) 54 55 #define CM_VPUCTL 0x008 56 #define CM_VPUDIV 0x00c 57 #define CM_SYSCTL 0x010 58 #define CM_SYSDIV 0x014 59 #define CM_PERIACTL 0x018 60 #define CM_PERIADIV 0x01c 61 #define CM_PERIICTL 0x020 62 #define CM_PERIIDIV 0x024 63 #define CM_H264CTL 0x028 64 #define CM_H264DIV 0x02c 65 #define CM_ISPCTL 0x030 66 #define CM_ISPDIV 0x034 67 #define CM_V3DCTL 0x038 68 #define CM_V3DDIV 0x03c 69 #define CM_CAM0CTL 0x040 70 #define CM_CAM0DIV 0x044 71 #define CM_CAM1CTL 0x048 72 #define CM_CAM1DIV 0x04c 73 #define CM_CCP2CTL 0x050 74 #define CM_CCP2DIV 0x054 75 #define CM_DSI0ECTL 0x058 76 #define CM_DSI0EDIV 0x05c 77 #define CM_DSI0PCTL 0x060 78 #define CM_DSI0PDIV 0x064 79 #define CM_DPICTL 0x068 80 #define CM_DPIDIV 0x06c 81 #define CM_GP0CTL 0x070 82 #define CM_GP0DIV 0x074 83 #define CM_GP1CTL 0x078 84 #define CM_GP1DIV 0x07c 85 #define CM_GP2CTL 0x080 86 #define CM_GP2DIV 0x084 87 #define CM_HSMCTL 0x088 88 #define CM_HSMDIV 0x08c 89 #define CM_OTPCTL 0x090 90 #define CM_OTPDIV 0x094 91 #define CM_PCMCTL 0x098 92 #define CM_PCMDIV 0x09c 93 #define CM_PWMCTL 0x0a0 94 #define CM_PWMDIV 0x0a4 95 #define CM_SLIMCTL 0x0a8 96 #define CM_SLIMDIV 0x0ac 97 #define CM_SMICTL 0x0b0 98 #define CM_SMIDIV 0x0b4 99 /* no definition for 0x0b8 and 0x0bc */ 100 #define CM_TCNTCTL 0x0c0 101 #define CM_TCNTDIV 0x0c4 102 #define CM_TECCTL 0x0c8 103 #define CM_TECDIV 0x0cc 104 #define CM_TD0CTL 0x0d0 105 #define CM_TD0DIV 0x0d4 106 #define CM_TD1CTL 0x0d8 107 #define CM_TD1DIV 0x0dc 108 #define CM_TSENSCTL 0x0e0 109 #define CM_TSENSDIV 0x0e4 110 #define CM_TIMERCTL 0x0e8 111 #define CM_TIMERDIV 0x0ec 112 #define CM_UARTCTL 0x0f0 113 #define CM_UARTDIV 0x0f4 114 #define CM_VECCTL 0x0f8 115 #define CM_VECDIV 0x0fc 116 #define CM_PULSECTL 0x190 117 #define CM_PULSEDIV 0x194 118 #define CM_SDCCTL 0x1a8 119 #define CM_SDCDIV 0x1ac 120 #define CM_ARMCTL 0x1b0 121 #define CM_AVEOCTL 0x1b8 122 #define CM_AVEODIV 0x1bc 123 #define CM_EMMCCTL 0x1c0 124 #define CM_EMMCDIV 0x1c4 125 126 /* General bits for the CM_*CTL regs */ 127 # define CM_ENABLE BIT(4) 128 # define CM_KILL BIT(5) 129 # define CM_GATE_BIT 6 130 # define CM_GATE BIT(CM_GATE_BIT) 131 # define CM_BUSY BIT(7) 132 # define CM_BUSYD BIT(8) 133 # define CM_FRAC BIT(9) 134 # define CM_SRC_SHIFT 0 135 # define CM_SRC_BITS 4 136 # define CM_SRC_MASK 0xf 137 # define CM_SRC_GND 0 138 # define CM_SRC_OSC 1 139 # define CM_SRC_TESTDEBUG0 2 140 # define CM_SRC_TESTDEBUG1 3 141 # define CM_SRC_PLLA_CORE 4 142 # define CM_SRC_PLLA_PER 4 143 # define CM_SRC_PLLC_CORE0 5 144 # define CM_SRC_PLLC_PER 5 145 # define CM_SRC_PLLC_CORE1 8 146 # define CM_SRC_PLLD_CORE 6 147 # define CM_SRC_PLLD_PER 6 148 # define CM_SRC_PLLH_AUX 7 149 # define CM_SRC_PLLC_CORE1 8 150 # define CM_SRC_PLLC_CORE2 9 151 152 #define CM_OSCCOUNT 0x100 153 154 #define CM_PLLA 0x104 155 # define CM_PLL_ANARST BIT(8) 156 # define CM_PLLA_HOLDPER BIT(7) 157 # define CM_PLLA_LOADPER BIT(6) 158 # define CM_PLLA_HOLDCORE BIT(5) 159 # define CM_PLLA_LOADCORE BIT(4) 160 # define CM_PLLA_HOLDCCP2 BIT(3) 161 # define CM_PLLA_LOADCCP2 BIT(2) 162 # define CM_PLLA_HOLDDSI0 BIT(1) 163 # define CM_PLLA_LOADDSI0 BIT(0) 164 165 #define CM_PLLC 0x108 166 # define CM_PLLC_HOLDPER BIT(7) 167 # define CM_PLLC_LOADPER BIT(6) 168 # define CM_PLLC_HOLDCORE2 BIT(5) 169 # define CM_PLLC_LOADCORE2 BIT(4) 170 # define CM_PLLC_HOLDCORE1 BIT(3) 171 # define CM_PLLC_LOADCORE1 BIT(2) 172 # define CM_PLLC_HOLDCORE0 BIT(1) 173 # define CM_PLLC_LOADCORE0 BIT(0) 174 175 #define CM_PLLD 0x10c 176 # define CM_PLLD_HOLDPER BIT(7) 177 # define CM_PLLD_LOADPER BIT(6) 178 # define CM_PLLD_HOLDCORE BIT(5) 179 # define CM_PLLD_LOADCORE BIT(4) 180 # define CM_PLLD_HOLDDSI1 BIT(3) 181 # define CM_PLLD_LOADDSI1 BIT(2) 182 # define CM_PLLD_HOLDDSI0 BIT(1) 183 # define CM_PLLD_LOADDSI0 BIT(0) 184 185 #define CM_PLLH 0x110 186 # define CM_PLLH_LOADRCAL BIT(2) 187 # define CM_PLLH_LOADAUX BIT(1) 188 # define CM_PLLH_LOADPIX BIT(0) 189 190 #define CM_LOCK 0x114 191 # define CM_LOCK_FLOCKH BIT(12) 192 # define CM_LOCK_FLOCKD BIT(11) 193 # define CM_LOCK_FLOCKC BIT(10) 194 # define CM_LOCK_FLOCKB BIT(9) 195 # define CM_LOCK_FLOCKA BIT(8) 196 197 #define CM_EVENT 0x118 198 #define CM_DSI1ECTL 0x158 199 #define CM_DSI1EDIV 0x15c 200 #define CM_DSI1PCTL 0x160 201 #define CM_DSI1PDIV 0x164 202 #define CM_DFTCTL 0x168 203 #define CM_DFTDIV 0x16c 204 205 #define CM_PLLB 0x170 206 # define CM_PLLB_HOLDARM BIT(1) 207 # define CM_PLLB_LOADARM BIT(0) 208 209 #define A2W_PLLA_CTRL 0x1100 210 #define A2W_PLLC_CTRL 0x1120 211 #define A2W_PLLD_CTRL 0x1140 212 #define A2W_PLLH_CTRL 0x1160 213 #define A2W_PLLB_CTRL 0x11e0 214 # define A2W_PLL_CTRL_PRST_DISABLE BIT(17) 215 # define A2W_PLL_CTRL_PWRDN BIT(16) 216 # define A2W_PLL_CTRL_PDIV_MASK 0x000007000 217 # define A2W_PLL_CTRL_PDIV_SHIFT 12 218 # define A2W_PLL_CTRL_NDIV_MASK 0x0000003ff 219 # define A2W_PLL_CTRL_NDIV_SHIFT 0 220 221 #define A2W_PLLA_ANA0 0x1010 222 #define A2W_PLLC_ANA0 0x1030 223 #define A2W_PLLD_ANA0 0x1050 224 #define A2W_PLLH_ANA0 0x1070 225 #define A2W_PLLB_ANA0 0x10f0 226 227 #define A2W_PLL_KA_SHIFT 7 228 #define A2W_PLL_KA_MASK GENMASK(9, 7) 229 #define A2W_PLL_KI_SHIFT 19 230 #define A2W_PLL_KI_MASK GENMASK(21, 19) 231 #define A2W_PLL_KP_SHIFT 15 232 #define A2W_PLL_KP_MASK GENMASK(18, 15) 233 234 #define A2W_PLLH_KA_SHIFT 19 235 #define A2W_PLLH_KA_MASK GENMASK(21, 19) 236 #define A2W_PLLH_KI_LOW_SHIFT 22 237 #define A2W_PLLH_KI_LOW_MASK GENMASK(23, 22) 238 #define A2W_PLLH_KI_HIGH_SHIFT 0 239 #define A2W_PLLH_KI_HIGH_MASK GENMASK(0, 0) 240 #define A2W_PLLH_KP_SHIFT 1 241 #define A2W_PLLH_KP_MASK GENMASK(4, 1) 242 243 #define A2W_XOSC_CTRL 0x1190 244 # define A2W_XOSC_CTRL_PLLB_ENABLE BIT(7) 245 # define A2W_XOSC_CTRL_PLLA_ENABLE BIT(6) 246 # define A2W_XOSC_CTRL_PLLD_ENABLE BIT(5) 247 # define A2W_XOSC_CTRL_DDR_ENABLE BIT(4) 248 # define A2W_XOSC_CTRL_CPR1_ENABLE BIT(3) 249 # define A2W_XOSC_CTRL_USB_ENABLE BIT(2) 250 # define A2W_XOSC_CTRL_HDMI_ENABLE BIT(1) 251 # define A2W_XOSC_CTRL_PLLC_ENABLE BIT(0) 252 253 #define A2W_PLLA_FRAC 0x1200 254 #define A2W_PLLC_FRAC 0x1220 255 #define A2W_PLLD_FRAC 0x1240 256 #define A2W_PLLH_FRAC 0x1260 257 #define A2W_PLLB_FRAC 0x12e0 258 # define A2W_PLL_FRAC_MASK ((1 << A2W_PLL_FRAC_BITS) - 1) 259 # define A2W_PLL_FRAC_BITS 20 260 261 #define A2W_PLL_CHANNEL_DISABLE BIT(8) 262 #define A2W_PLL_DIV_BITS 8 263 #define A2W_PLL_DIV_SHIFT 0 264 265 #define A2W_PLLA_DSI0 0x1300 266 #define A2W_PLLA_CORE 0x1400 267 #define A2W_PLLA_PER 0x1500 268 #define A2W_PLLA_CCP2 0x1600 269 270 #define A2W_PLLC_CORE2 0x1320 271 #define A2W_PLLC_CORE1 0x1420 272 #define A2W_PLLC_PER 0x1520 273 #define A2W_PLLC_CORE0 0x1620 274 275 #define A2W_PLLD_DSI0 0x1340 276 #define A2W_PLLD_CORE 0x1440 277 #define A2W_PLLD_PER 0x1540 278 #define A2W_PLLD_DSI1 0x1640 279 280 #define A2W_PLLH_AUX 0x1360 281 #define A2W_PLLH_RCAL 0x1460 282 #define A2W_PLLH_PIX 0x1560 283 #define A2W_PLLH_STS 0x1660 284 285 #define A2W_PLLH_CTRLR 0x1960 286 #define A2W_PLLH_FRACR 0x1a60 287 #define A2W_PLLH_AUXR 0x1b60 288 #define A2W_PLLH_RCALR 0x1c60 289 #define A2W_PLLH_PIXR 0x1d60 290 #define A2W_PLLH_STSR 0x1e60 291 292 #define A2W_PLLB_ARM 0x13e0 293 #define A2W_PLLB_SP0 0x14e0 294 #define A2W_PLLB_SP1 0x15e0 295 #define A2W_PLLB_SP2 0x16e0 296 297 #define LOCK_TIMEOUT_NS 100000000 298 #define BCM2835_MAX_FB_RATE 1750000000u 299 300 struct bcm2835_cprman { 301 struct device *dev; 302 void __iomem *regs; 303 spinlock_t regs_lock; /* spinlock for all clocks */ 304 const char *osc_name; 305 306 /* Must be last */ 307 struct clk_hw_onecell_data onecell; 308 }; 309 310 static inline void cprman_write(struct bcm2835_cprman *cprman, u32 reg, u32 val) 311 { 312 writel(CM_PASSWORD | val, cprman->regs + reg); 313 } 314 315 static inline u32 cprman_read(struct bcm2835_cprman *cprman, u32 reg) 316 { 317 return readl(cprman->regs + reg); 318 } 319 320 static int bcm2835_debugfs_regset(struct bcm2835_cprman *cprman, u32 base, 321 struct debugfs_reg32 *regs, size_t nregs, 322 struct dentry *dentry) 323 { 324 struct dentry *regdump; 325 struct debugfs_regset32 *regset; 326 327 regset = devm_kzalloc(cprman->dev, sizeof(*regset), GFP_KERNEL); 328 if (!regset) 329 return -ENOMEM; 330 331 regset->regs = regs; 332 regset->nregs = nregs; 333 regset->base = cprman->regs + base; 334 335 regdump = debugfs_create_regset32("regdump", S_IRUGO, dentry, 336 regset); 337 338 return regdump ? 0 : -ENOMEM; 339 } 340 341 /* 342 * These are fixed clocks. They're probably not all root clocks and it may 343 * be possible to turn them on and off but until this is mapped out better 344 * it's the only way they can be used. 345 */ 346 void __init bcm2835_init_clocks(void) 347 { 348 struct clk_hw *hw; 349 int ret; 350 351 hw = clk_hw_register_fixed_rate(NULL, "apb_pclk", NULL, 0, 126000000); 352 if (IS_ERR(hw)) 353 pr_err("apb_pclk not registered\n"); 354 355 hw = clk_hw_register_fixed_rate(NULL, "uart0_pclk", NULL, 0, 3000000); 356 if (IS_ERR(hw)) 357 pr_err("uart0_pclk not registered\n"); 358 ret = clk_hw_register_clkdev(hw, NULL, "20201000.uart"); 359 if (ret) 360 pr_err("uart0_pclk alias not registered\n"); 361 362 hw = clk_hw_register_fixed_rate(NULL, "uart1_pclk", NULL, 0, 125000000); 363 if (IS_ERR(hw)) 364 pr_err("uart1_pclk not registered\n"); 365 ret = clk_hw_register_clkdev(hw, NULL, "20215000.uart"); 366 if (ret) 367 pr_err("uart1_pclk alias not registered\n"); 368 } 369 370 struct bcm2835_pll_data { 371 const char *name; 372 u32 cm_ctrl_reg; 373 u32 a2w_ctrl_reg; 374 u32 frac_reg; 375 u32 ana_reg_base; 376 u32 reference_enable_mask; 377 /* Bit in CM_LOCK to indicate when the PLL has locked. */ 378 u32 lock_mask; 379 380 const struct bcm2835_pll_ana_bits *ana; 381 382 unsigned long min_rate; 383 unsigned long max_rate; 384 /* 385 * Highest rate for the VCO before we have to use the 386 * pre-divide-by-2. 387 */ 388 unsigned long max_fb_rate; 389 }; 390 391 struct bcm2835_pll_ana_bits { 392 u32 mask0; 393 u32 set0; 394 u32 mask1; 395 u32 set1; 396 u32 mask3; 397 u32 set3; 398 u32 fb_prediv_mask; 399 }; 400 401 static const struct bcm2835_pll_ana_bits bcm2835_ana_default = { 402 .mask0 = 0, 403 .set0 = 0, 404 .mask1 = (u32)~(A2W_PLL_KI_MASK | A2W_PLL_KP_MASK), 405 .set1 = (2 << A2W_PLL_KI_SHIFT) | (8 << A2W_PLL_KP_SHIFT), 406 .mask3 = (u32)~A2W_PLL_KA_MASK, 407 .set3 = (2 << A2W_PLL_KA_SHIFT), 408 .fb_prediv_mask = BIT(14), 409 }; 410 411 static const struct bcm2835_pll_ana_bits bcm2835_ana_pllh = { 412 .mask0 = (u32)~(A2W_PLLH_KA_MASK | A2W_PLLH_KI_LOW_MASK), 413 .set0 = (2 << A2W_PLLH_KA_SHIFT) | (2 << A2W_PLLH_KI_LOW_SHIFT), 414 .mask1 = (u32)~(A2W_PLLH_KI_HIGH_MASK | A2W_PLLH_KP_MASK), 415 .set1 = (6 << A2W_PLLH_KP_SHIFT), 416 .mask3 = 0, 417 .set3 = 0, 418 .fb_prediv_mask = BIT(11), 419 }; 420 421 struct bcm2835_pll_divider_data { 422 const char *name; 423 const char *source_pll; 424 425 u32 cm_reg; 426 u32 a2w_reg; 427 428 u32 load_mask; 429 u32 hold_mask; 430 u32 fixed_divider; 431 }; 432 433 struct bcm2835_clock_data { 434 const char *name; 435 436 const char *const *parents; 437 int num_mux_parents; 438 439 /* Bitmap encoding which parents accept rate change propagation. */ 440 unsigned int set_rate_parent; 441 442 u32 ctl_reg; 443 u32 div_reg; 444 445 /* Number of integer bits in the divider */ 446 u32 int_bits; 447 /* Number of fractional bits in the divider */ 448 u32 frac_bits; 449 450 u32 flags; 451 452 bool is_vpu_clock; 453 bool is_mash_clock; 454 }; 455 456 struct bcm2835_gate_data { 457 const char *name; 458 const char *parent; 459 460 u32 ctl_reg; 461 }; 462 463 struct bcm2835_pll { 464 struct clk_hw hw; 465 struct bcm2835_cprman *cprman; 466 const struct bcm2835_pll_data *data; 467 }; 468 469 static int bcm2835_pll_is_on(struct clk_hw *hw) 470 { 471 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); 472 struct bcm2835_cprman *cprman = pll->cprman; 473 const struct bcm2835_pll_data *data = pll->data; 474 475 return cprman_read(cprman, data->a2w_ctrl_reg) & 476 A2W_PLL_CTRL_PRST_DISABLE; 477 } 478 479 static void bcm2835_pll_choose_ndiv_and_fdiv(unsigned long rate, 480 unsigned long parent_rate, 481 u32 *ndiv, u32 *fdiv) 482 { 483 u64 div; 484 485 div = (u64)rate << A2W_PLL_FRAC_BITS; 486 do_div(div, parent_rate); 487 488 *ndiv = div >> A2W_PLL_FRAC_BITS; 489 *fdiv = div & ((1 << A2W_PLL_FRAC_BITS) - 1); 490 } 491 492 static long bcm2835_pll_rate_from_divisors(unsigned long parent_rate, 493 u32 ndiv, u32 fdiv, u32 pdiv) 494 { 495 u64 rate; 496 497 if (pdiv == 0) 498 return 0; 499 500 rate = (u64)parent_rate * ((ndiv << A2W_PLL_FRAC_BITS) + fdiv); 501 do_div(rate, pdiv); 502 return rate >> A2W_PLL_FRAC_BITS; 503 } 504 505 static long bcm2835_pll_round_rate(struct clk_hw *hw, unsigned long rate, 506 unsigned long *parent_rate) 507 { 508 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); 509 const struct bcm2835_pll_data *data = pll->data; 510 u32 ndiv, fdiv; 511 512 rate = clamp(rate, data->min_rate, data->max_rate); 513 514 bcm2835_pll_choose_ndiv_and_fdiv(rate, *parent_rate, &ndiv, &fdiv); 515 516 return bcm2835_pll_rate_from_divisors(*parent_rate, ndiv, fdiv, 1); 517 } 518 519 static unsigned long bcm2835_pll_get_rate(struct clk_hw *hw, 520 unsigned long parent_rate) 521 { 522 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); 523 struct bcm2835_cprman *cprman = pll->cprman; 524 const struct bcm2835_pll_data *data = pll->data; 525 u32 a2wctrl = cprman_read(cprman, data->a2w_ctrl_reg); 526 u32 ndiv, pdiv, fdiv; 527 bool using_prediv; 528 529 if (parent_rate == 0) 530 return 0; 531 532 fdiv = cprman_read(cprman, data->frac_reg) & A2W_PLL_FRAC_MASK; 533 ndiv = (a2wctrl & A2W_PLL_CTRL_NDIV_MASK) >> A2W_PLL_CTRL_NDIV_SHIFT; 534 pdiv = (a2wctrl & A2W_PLL_CTRL_PDIV_MASK) >> A2W_PLL_CTRL_PDIV_SHIFT; 535 using_prediv = cprman_read(cprman, data->ana_reg_base + 4) & 536 data->ana->fb_prediv_mask; 537 538 if (using_prediv) 539 ndiv *= 2; 540 541 return bcm2835_pll_rate_from_divisors(parent_rate, ndiv, fdiv, pdiv); 542 } 543 544 static void bcm2835_pll_off(struct clk_hw *hw) 545 { 546 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); 547 struct bcm2835_cprman *cprman = pll->cprman; 548 const struct bcm2835_pll_data *data = pll->data; 549 550 spin_lock(&cprman->regs_lock); 551 cprman_write(cprman, data->cm_ctrl_reg, 552 cprman_read(cprman, data->cm_ctrl_reg) | 553 CM_PLL_ANARST); 554 cprman_write(cprman, data->a2w_ctrl_reg, 555 cprman_read(cprman, data->a2w_ctrl_reg) | 556 A2W_PLL_CTRL_PWRDN); 557 spin_unlock(&cprman->regs_lock); 558 } 559 560 static int bcm2835_pll_on(struct clk_hw *hw) 561 { 562 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); 563 struct bcm2835_cprman *cprman = pll->cprman; 564 const struct bcm2835_pll_data *data = pll->data; 565 ktime_t timeout; 566 567 cprman_write(cprman, data->a2w_ctrl_reg, 568 cprman_read(cprman, data->a2w_ctrl_reg) & 569 ~A2W_PLL_CTRL_PWRDN); 570 571 /* Take the PLL out of reset. */ 572 cprman_write(cprman, data->cm_ctrl_reg, 573 cprman_read(cprman, data->cm_ctrl_reg) & ~CM_PLL_ANARST); 574 575 /* Wait for the PLL to lock. */ 576 timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS); 577 while (!(cprman_read(cprman, CM_LOCK) & data->lock_mask)) { 578 if (ktime_after(ktime_get(), timeout)) { 579 dev_err(cprman->dev, "%s: couldn't lock PLL\n", 580 clk_hw_get_name(hw)); 581 return -ETIMEDOUT; 582 } 583 584 cpu_relax(); 585 } 586 587 return 0; 588 } 589 590 static void 591 bcm2835_pll_write_ana(struct bcm2835_cprman *cprman, u32 ana_reg_base, u32 *ana) 592 { 593 int i; 594 595 /* 596 * ANA register setup is done as a series of writes to 597 * ANA3-ANA0, in that order. This lets us write all 4 598 * registers as a single cycle of the serdes interface (taking 599 * 100 xosc clocks), whereas if we were to update ana0, 1, and 600 * 3 individually through their partial-write registers, each 601 * would be their own serdes cycle. 602 */ 603 for (i = 3; i >= 0; i--) 604 cprman_write(cprman, ana_reg_base + i * 4, ana[i]); 605 } 606 607 static int bcm2835_pll_set_rate(struct clk_hw *hw, 608 unsigned long rate, unsigned long parent_rate) 609 { 610 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); 611 struct bcm2835_cprman *cprman = pll->cprman; 612 const struct bcm2835_pll_data *data = pll->data; 613 bool was_using_prediv, use_fb_prediv, do_ana_setup_first; 614 u32 ndiv, fdiv, a2w_ctl; 615 u32 ana[4]; 616 int i; 617 618 if (rate > data->max_fb_rate) { 619 use_fb_prediv = true; 620 rate /= 2; 621 } else { 622 use_fb_prediv = false; 623 } 624 625 bcm2835_pll_choose_ndiv_and_fdiv(rate, parent_rate, &ndiv, &fdiv); 626 627 for (i = 3; i >= 0; i--) 628 ana[i] = cprman_read(cprman, data->ana_reg_base + i * 4); 629 630 was_using_prediv = ana[1] & data->ana->fb_prediv_mask; 631 632 ana[0] &= ~data->ana->mask0; 633 ana[0] |= data->ana->set0; 634 ana[1] &= ~data->ana->mask1; 635 ana[1] |= data->ana->set1; 636 ana[3] &= ~data->ana->mask3; 637 ana[3] |= data->ana->set3; 638 639 if (was_using_prediv && !use_fb_prediv) { 640 ana[1] &= ~data->ana->fb_prediv_mask; 641 do_ana_setup_first = true; 642 } else if (!was_using_prediv && use_fb_prediv) { 643 ana[1] |= data->ana->fb_prediv_mask; 644 do_ana_setup_first = false; 645 } else { 646 do_ana_setup_first = true; 647 } 648 649 /* Unmask the reference clock from the oscillator. */ 650 cprman_write(cprman, A2W_XOSC_CTRL, 651 cprman_read(cprman, A2W_XOSC_CTRL) | 652 data->reference_enable_mask); 653 654 if (do_ana_setup_first) 655 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana); 656 657 /* Set the PLL multiplier from the oscillator. */ 658 cprman_write(cprman, data->frac_reg, fdiv); 659 660 a2w_ctl = cprman_read(cprman, data->a2w_ctrl_reg); 661 a2w_ctl &= ~A2W_PLL_CTRL_NDIV_MASK; 662 a2w_ctl |= ndiv << A2W_PLL_CTRL_NDIV_SHIFT; 663 a2w_ctl &= ~A2W_PLL_CTRL_PDIV_MASK; 664 a2w_ctl |= 1 << A2W_PLL_CTRL_PDIV_SHIFT; 665 cprman_write(cprman, data->a2w_ctrl_reg, a2w_ctl); 666 667 if (!do_ana_setup_first) 668 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana); 669 670 return 0; 671 } 672 673 static int bcm2835_pll_debug_init(struct clk_hw *hw, 674 struct dentry *dentry) 675 { 676 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); 677 struct bcm2835_cprman *cprman = pll->cprman; 678 const struct bcm2835_pll_data *data = pll->data; 679 struct debugfs_reg32 *regs; 680 681 regs = devm_kzalloc(cprman->dev, 7 * sizeof(*regs), GFP_KERNEL); 682 if (!regs) 683 return -ENOMEM; 684 685 regs[0].name = "cm_ctrl"; 686 regs[0].offset = data->cm_ctrl_reg; 687 regs[1].name = "a2w_ctrl"; 688 regs[1].offset = data->a2w_ctrl_reg; 689 regs[2].name = "frac"; 690 regs[2].offset = data->frac_reg; 691 regs[3].name = "ana0"; 692 regs[3].offset = data->ana_reg_base + 0 * 4; 693 regs[4].name = "ana1"; 694 regs[4].offset = data->ana_reg_base + 1 * 4; 695 regs[5].name = "ana2"; 696 regs[5].offset = data->ana_reg_base + 2 * 4; 697 regs[6].name = "ana3"; 698 regs[6].offset = data->ana_reg_base + 3 * 4; 699 700 return bcm2835_debugfs_regset(cprman, 0, regs, 7, dentry); 701 } 702 703 static const struct clk_ops bcm2835_pll_clk_ops = { 704 .is_prepared = bcm2835_pll_is_on, 705 .prepare = bcm2835_pll_on, 706 .unprepare = bcm2835_pll_off, 707 .recalc_rate = bcm2835_pll_get_rate, 708 .set_rate = bcm2835_pll_set_rate, 709 .round_rate = bcm2835_pll_round_rate, 710 .debug_init = bcm2835_pll_debug_init, 711 }; 712 713 struct bcm2835_pll_divider { 714 struct clk_divider div; 715 struct bcm2835_cprman *cprman; 716 const struct bcm2835_pll_divider_data *data; 717 }; 718 719 static struct bcm2835_pll_divider * 720 bcm2835_pll_divider_from_hw(struct clk_hw *hw) 721 { 722 return container_of(hw, struct bcm2835_pll_divider, div.hw); 723 } 724 725 static int bcm2835_pll_divider_is_on(struct clk_hw *hw) 726 { 727 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); 728 struct bcm2835_cprman *cprman = divider->cprman; 729 const struct bcm2835_pll_divider_data *data = divider->data; 730 731 return !(cprman_read(cprman, data->a2w_reg) & A2W_PLL_CHANNEL_DISABLE); 732 } 733 734 static long bcm2835_pll_divider_round_rate(struct clk_hw *hw, 735 unsigned long rate, 736 unsigned long *parent_rate) 737 { 738 return clk_divider_ops.round_rate(hw, rate, parent_rate); 739 } 740 741 static unsigned long bcm2835_pll_divider_get_rate(struct clk_hw *hw, 742 unsigned long parent_rate) 743 { 744 return clk_divider_ops.recalc_rate(hw, parent_rate); 745 } 746 747 static void bcm2835_pll_divider_off(struct clk_hw *hw) 748 { 749 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); 750 struct bcm2835_cprman *cprman = divider->cprman; 751 const struct bcm2835_pll_divider_data *data = divider->data; 752 753 spin_lock(&cprman->regs_lock); 754 cprman_write(cprman, data->cm_reg, 755 (cprman_read(cprman, data->cm_reg) & 756 ~data->load_mask) | data->hold_mask); 757 cprman_write(cprman, data->a2w_reg, 758 cprman_read(cprman, data->a2w_reg) | 759 A2W_PLL_CHANNEL_DISABLE); 760 spin_unlock(&cprman->regs_lock); 761 } 762 763 static int bcm2835_pll_divider_on(struct clk_hw *hw) 764 { 765 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); 766 struct bcm2835_cprman *cprman = divider->cprman; 767 const struct bcm2835_pll_divider_data *data = divider->data; 768 769 spin_lock(&cprman->regs_lock); 770 cprman_write(cprman, data->a2w_reg, 771 cprman_read(cprman, data->a2w_reg) & 772 ~A2W_PLL_CHANNEL_DISABLE); 773 774 cprman_write(cprman, data->cm_reg, 775 cprman_read(cprman, data->cm_reg) & ~data->hold_mask); 776 spin_unlock(&cprman->regs_lock); 777 778 return 0; 779 } 780 781 static int bcm2835_pll_divider_set_rate(struct clk_hw *hw, 782 unsigned long rate, 783 unsigned long parent_rate) 784 { 785 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); 786 struct bcm2835_cprman *cprman = divider->cprman; 787 const struct bcm2835_pll_divider_data *data = divider->data; 788 u32 cm, div, max_div = 1 << A2W_PLL_DIV_BITS; 789 790 div = DIV_ROUND_UP_ULL(parent_rate, rate); 791 792 div = min(div, max_div); 793 if (div == max_div) 794 div = 0; 795 796 cprman_write(cprman, data->a2w_reg, div); 797 cm = cprman_read(cprman, data->cm_reg); 798 cprman_write(cprman, data->cm_reg, cm | data->load_mask); 799 cprman_write(cprman, data->cm_reg, cm & ~data->load_mask); 800 801 return 0; 802 } 803 804 static int bcm2835_pll_divider_debug_init(struct clk_hw *hw, 805 struct dentry *dentry) 806 { 807 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); 808 struct bcm2835_cprman *cprman = divider->cprman; 809 const struct bcm2835_pll_divider_data *data = divider->data; 810 struct debugfs_reg32 *regs; 811 812 regs = devm_kzalloc(cprman->dev, 7 * sizeof(*regs), GFP_KERNEL); 813 if (!regs) 814 return -ENOMEM; 815 816 regs[0].name = "cm"; 817 regs[0].offset = data->cm_reg; 818 regs[1].name = "a2w"; 819 regs[1].offset = data->a2w_reg; 820 821 return bcm2835_debugfs_regset(cprman, 0, regs, 2, dentry); 822 } 823 824 static const struct clk_ops bcm2835_pll_divider_clk_ops = { 825 .is_prepared = bcm2835_pll_divider_is_on, 826 .prepare = bcm2835_pll_divider_on, 827 .unprepare = bcm2835_pll_divider_off, 828 .recalc_rate = bcm2835_pll_divider_get_rate, 829 .set_rate = bcm2835_pll_divider_set_rate, 830 .round_rate = bcm2835_pll_divider_round_rate, 831 .debug_init = bcm2835_pll_divider_debug_init, 832 }; 833 834 /* 835 * The CM dividers do fixed-point division, so we can't use the 836 * generic integer divider code like the PLL dividers do (and we can't 837 * fake it by having some fixed shifts preceding it in the clock tree, 838 * because we'd run out of bits in a 32-bit unsigned long). 839 */ 840 struct bcm2835_clock { 841 struct clk_hw hw; 842 struct bcm2835_cprman *cprman; 843 const struct bcm2835_clock_data *data; 844 }; 845 846 static struct bcm2835_clock *bcm2835_clock_from_hw(struct clk_hw *hw) 847 { 848 return container_of(hw, struct bcm2835_clock, hw); 849 } 850 851 static int bcm2835_clock_is_on(struct clk_hw *hw) 852 { 853 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 854 struct bcm2835_cprman *cprman = clock->cprman; 855 const struct bcm2835_clock_data *data = clock->data; 856 857 return (cprman_read(cprman, data->ctl_reg) & CM_ENABLE) != 0; 858 } 859 860 static u32 bcm2835_clock_choose_div(struct clk_hw *hw, 861 unsigned long rate, 862 unsigned long parent_rate, 863 bool round_up) 864 { 865 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 866 const struct bcm2835_clock_data *data = clock->data; 867 u32 unused_frac_mask = 868 GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1; 869 u64 temp = (u64)parent_rate << CM_DIV_FRAC_BITS; 870 u64 rem; 871 u32 div, mindiv, maxdiv; 872 873 rem = do_div(temp, rate); 874 div = temp; 875 876 /* Round up and mask off the unused bits */ 877 if (round_up && ((div & unused_frac_mask) != 0 || rem != 0)) 878 div += unused_frac_mask + 1; 879 div &= ~unused_frac_mask; 880 881 /* different clamping limits apply for a mash clock */ 882 if (data->is_mash_clock) { 883 /* clamp to min divider of 2 */ 884 mindiv = 2 << CM_DIV_FRAC_BITS; 885 /* clamp to the highest possible integer divider */ 886 maxdiv = (BIT(data->int_bits) - 1) << CM_DIV_FRAC_BITS; 887 } else { 888 /* clamp to min divider of 1 */ 889 mindiv = 1 << CM_DIV_FRAC_BITS; 890 /* clamp to the highest possible fractional divider */ 891 maxdiv = GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1, 892 CM_DIV_FRAC_BITS - data->frac_bits); 893 } 894 895 /* apply the clamping limits */ 896 div = max_t(u32, div, mindiv); 897 div = min_t(u32, div, maxdiv); 898 899 return div; 900 } 901 902 static long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock, 903 unsigned long parent_rate, 904 u32 div) 905 { 906 const struct bcm2835_clock_data *data = clock->data; 907 u64 temp; 908 909 /* 910 * The divisor is a 12.12 fixed point field, but only some of 911 * the bits are populated in any given clock. 912 */ 913 div >>= CM_DIV_FRAC_BITS - data->frac_bits; 914 div &= (1 << (data->int_bits + data->frac_bits)) - 1; 915 916 if (div == 0) 917 return 0; 918 919 temp = (u64)parent_rate << data->frac_bits; 920 921 do_div(temp, div); 922 923 return temp; 924 } 925 926 static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw, 927 unsigned long parent_rate) 928 { 929 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 930 struct bcm2835_cprman *cprman = clock->cprman; 931 const struct bcm2835_clock_data *data = clock->data; 932 u32 div = cprman_read(cprman, data->div_reg); 933 934 return bcm2835_clock_rate_from_divisor(clock, parent_rate, div); 935 } 936 937 static void bcm2835_clock_wait_busy(struct bcm2835_clock *clock) 938 { 939 struct bcm2835_cprman *cprman = clock->cprman; 940 const struct bcm2835_clock_data *data = clock->data; 941 ktime_t timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS); 942 943 while (cprman_read(cprman, data->ctl_reg) & CM_BUSY) { 944 if (ktime_after(ktime_get(), timeout)) { 945 dev_err(cprman->dev, "%s: couldn't lock PLL\n", 946 clk_hw_get_name(&clock->hw)); 947 return; 948 } 949 cpu_relax(); 950 } 951 } 952 953 static void bcm2835_clock_off(struct clk_hw *hw) 954 { 955 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 956 struct bcm2835_cprman *cprman = clock->cprman; 957 const struct bcm2835_clock_data *data = clock->data; 958 959 spin_lock(&cprman->regs_lock); 960 cprman_write(cprman, data->ctl_reg, 961 cprman_read(cprman, data->ctl_reg) & ~CM_ENABLE); 962 spin_unlock(&cprman->regs_lock); 963 964 /* BUSY will remain high until the divider completes its cycle. */ 965 bcm2835_clock_wait_busy(clock); 966 } 967 968 static int bcm2835_clock_on(struct clk_hw *hw) 969 { 970 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 971 struct bcm2835_cprman *cprman = clock->cprman; 972 const struct bcm2835_clock_data *data = clock->data; 973 974 spin_lock(&cprman->regs_lock); 975 cprman_write(cprman, data->ctl_reg, 976 cprman_read(cprman, data->ctl_reg) | 977 CM_ENABLE | 978 CM_GATE); 979 spin_unlock(&cprman->regs_lock); 980 981 return 0; 982 } 983 984 static int bcm2835_clock_set_rate(struct clk_hw *hw, 985 unsigned long rate, unsigned long parent_rate) 986 { 987 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 988 struct bcm2835_cprman *cprman = clock->cprman; 989 const struct bcm2835_clock_data *data = clock->data; 990 u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate, false); 991 u32 ctl; 992 993 spin_lock(&cprman->regs_lock); 994 995 /* 996 * Setting up frac support 997 * 998 * In principle it is recommended to stop/start the clock first, 999 * but as we set CLK_SET_RATE_GATE during registration of the 1000 * clock this requirement should be take care of by the 1001 * clk-framework. 1002 */ 1003 ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC; 1004 ctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0; 1005 cprman_write(cprman, data->ctl_reg, ctl); 1006 1007 cprman_write(cprman, data->div_reg, div); 1008 1009 spin_unlock(&cprman->regs_lock); 1010 1011 return 0; 1012 } 1013 1014 static bool 1015 bcm2835_clk_is_pllc(struct clk_hw *hw) 1016 { 1017 if (!hw) 1018 return false; 1019 1020 return strncmp(clk_hw_get_name(hw), "pllc", 4) == 0; 1021 } 1022 1023 static unsigned long bcm2835_clock_choose_div_and_prate(struct clk_hw *hw, 1024 int parent_idx, 1025 unsigned long rate, 1026 u32 *div, 1027 unsigned long *prate) 1028 { 1029 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 1030 struct bcm2835_cprman *cprman = clock->cprman; 1031 const struct bcm2835_clock_data *data = clock->data; 1032 unsigned long best_rate = 0; 1033 u32 curdiv, mindiv, maxdiv; 1034 struct clk_hw *parent; 1035 1036 parent = clk_hw_get_parent_by_index(hw, parent_idx); 1037 1038 if (!(BIT(parent_idx) & data->set_rate_parent)) { 1039 *prate = clk_hw_get_rate(parent); 1040 *div = bcm2835_clock_choose_div(hw, rate, *prate, true); 1041 1042 return bcm2835_clock_rate_from_divisor(clock, *prate, 1043 *div); 1044 } 1045 1046 if (data->frac_bits) 1047 dev_warn(cprman->dev, 1048 "frac bits are not used when propagating rate change"); 1049 1050 /* clamp to min divider of 2 if we're dealing with a mash clock */ 1051 mindiv = data->is_mash_clock ? 2 : 1; 1052 maxdiv = BIT(data->int_bits) - 1; 1053 1054 /* TODO: Be smart, and only test a subset of the available divisors. */ 1055 for (curdiv = mindiv; curdiv <= maxdiv; curdiv++) { 1056 unsigned long tmp_rate; 1057 1058 tmp_rate = clk_hw_round_rate(parent, rate * curdiv); 1059 tmp_rate /= curdiv; 1060 if (curdiv == mindiv || 1061 (tmp_rate > best_rate && tmp_rate <= rate)) 1062 best_rate = tmp_rate; 1063 1064 if (best_rate == rate) 1065 break; 1066 } 1067 1068 *div = curdiv << CM_DIV_FRAC_BITS; 1069 *prate = curdiv * best_rate; 1070 1071 return best_rate; 1072 } 1073 1074 static int bcm2835_clock_determine_rate(struct clk_hw *hw, 1075 struct clk_rate_request *req) 1076 { 1077 struct clk_hw *parent, *best_parent = NULL; 1078 bool current_parent_is_pllc; 1079 unsigned long rate, best_rate = 0; 1080 unsigned long prate, best_prate = 0; 1081 size_t i; 1082 u32 div; 1083 1084 current_parent_is_pllc = bcm2835_clk_is_pllc(clk_hw_get_parent(hw)); 1085 1086 /* 1087 * Select parent clock that results in the closest but lower rate 1088 */ 1089 for (i = 0; i < clk_hw_get_num_parents(hw); ++i) { 1090 parent = clk_hw_get_parent_by_index(hw, i); 1091 if (!parent) 1092 continue; 1093 1094 /* 1095 * Don't choose a PLLC-derived clock as our parent 1096 * unless it had been manually set that way. PLLC's 1097 * frequency gets adjusted by the firmware due to 1098 * over-temp or under-voltage conditions, without 1099 * prior notification to our clock consumer. 1100 */ 1101 if (bcm2835_clk_is_pllc(parent) && !current_parent_is_pllc) 1102 continue; 1103 1104 rate = bcm2835_clock_choose_div_and_prate(hw, i, req->rate, 1105 &div, &prate); 1106 if (rate > best_rate && rate <= req->rate) { 1107 best_parent = parent; 1108 best_prate = prate; 1109 best_rate = rate; 1110 } 1111 } 1112 1113 if (!best_parent) 1114 return -EINVAL; 1115 1116 req->best_parent_hw = best_parent; 1117 req->best_parent_rate = best_prate; 1118 1119 req->rate = best_rate; 1120 1121 return 0; 1122 } 1123 1124 static int bcm2835_clock_set_parent(struct clk_hw *hw, u8 index) 1125 { 1126 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 1127 struct bcm2835_cprman *cprman = clock->cprman; 1128 const struct bcm2835_clock_data *data = clock->data; 1129 u8 src = (index << CM_SRC_SHIFT) & CM_SRC_MASK; 1130 1131 cprman_write(cprman, data->ctl_reg, src); 1132 return 0; 1133 } 1134 1135 static u8 bcm2835_clock_get_parent(struct clk_hw *hw) 1136 { 1137 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 1138 struct bcm2835_cprman *cprman = clock->cprman; 1139 const struct bcm2835_clock_data *data = clock->data; 1140 u32 src = cprman_read(cprman, data->ctl_reg); 1141 1142 return (src & CM_SRC_MASK) >> CM_SRC_SHIFT; 1143 } 1144 1145 static struct debugfs_reg32 bcm2835_debugfs_clock_reg32[] = { 1146 { 1147 .name = "ctl", 1148 .offset = 0, 1149 }, 1150 { 1151 .name = "div", 1152 .offset = 4, 1153 }, 1154 }; 1155 1156 static int bcm2835_clock_debug_init(struct clk_hw *hw, 1157 struct dentry *dentry) 1158 { 1159 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 1160 struct bcm2835_cprman *cprman = clock->cprman; 1161 const struct bcm2835_clock_data *data = clock->data; 1162 1163 return bcm2835_debugfs_regset( 1164 cprman, data->ctl_reg, 1165 bcm2835_debugfs_clock_reg32, 1166 ARRAY_SIZE(bcm2835_debugfs_clock_reg32), 1167 dentry); 1168 } 1169 1170 static const struct clk_ops bcm2835_clock_clk_ops = { 1171 .is_prepared = bcm2835_clock_is_on, 1172 .prepare = bcm2835_clock_on, 1173 .unprepare = bcm2835_clock_off, 1174 .recalc_rate = bcm2835_clock_get_rate, 1175 .set_rate = bcm2835_clock_set_rate, 1176 .determine_rate = bcm2835_clock_determine_rate, 1177 .set_parent = bcm2835_clock_set_parent, 1178 .get_parent = bcm2835_clock_get_parent, 1179 .debug_init = bcm2835_clock_debug_init, 1180 }; 1181 1182 static int bcm2835_vpu_clock_is_on(struct clk_hw *hw) 1183 { 1184 return true; 1185 } 1186 1187 /* 1188 * The VPU clock can never be disabled (it doesn't have an ENABLE 1189 * bit), so it gets its own set of clock ops. 1190 */ 1191 static const struct clk_ops bcm2835_vpu_clock_clk_ops = { 1192 .is_prepared = bcm2835_vpu_clock_is_on, 1193 .recalc_rate = bcm2835_clock_get_rate, 1194 .set_rate = bcm2835_clock_set_rate, 1195 .determine_rate = bcm2835_clock_determine_rate, 1196 .set_parent = bcm2835_clock_set_parent, 1197 .get_parent = bcm2835_clock_get_parent, 1198 .debug_init = bcm2835_clock_debug_init, 1199 }; 1200 1201 static struct clk_hw *bcm2835_register_pll(struct bcm2835_cprman *cprman, 1202 const struct bcm2835_pll_data *data) 1203 { 1204 struct bcm2835_pll *pll; 1205 struct clk_init_data init; 1206 int ret; 1207 1208 memset(&init, 0, sizeof(init)); 1209 1210 /* All of the PLLs derive from the external oscillator. */ 1211 init.parent_names = &cprman->osc_name; 1212 init.num_parents = 1; 1213 init.name = data->name; 1214 init.ops = &bcm2835_pll_clk_ops; 1215 init.flags = CLK_IGNORE_UNUSED; 1216 1217 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 1218 if (!pll) 1219 return NULL; 1220 1221 pll->cprman = cprman; 1222 pll->data = data; 1223 pll->hw.init = &init; 1224 1225 ret = devm_clk_hw_register(cprman->dev, &pll->hw); 1226 if (ret) 1227 return NULL; 1228 return &pll->hw; 1229 } 1230 1231 static struct clk_hw * 1232 bcm2835_register_pll_divider(struct bcm2835_cprman *cprman, 1233 const struct bcm2835_pll_divider_data *data) 1234 { 1235 struct bcm2835_pll_divider *divider; 1236 struct clk_init_data init; 1237 const char *divider_name; 1238 int ret; 1239 1240 if (data->fixed_divider != 1) { 1241 divider_name = devm_kasprintf(cprman->dev, GFP_KERNEL, 1242 "%s_prediv", data->name); 1243 if (!divider_name) 1244 return NULL; 1245 } else { 1246 divider_name = data->name; 1247 } 1248 1249 memset(&init, 0, sizeof(init)); 1250 1251 init.parent_names = &data->source_pll; 1252 init.num_parents = 1; 1253 init.name = divider_name; 1254 init.ops = &bcm2835_pll_divider_clk_ops; 1255 init.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED; 1256 1257 divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL); 1258 if (!divider) 1259 return NULL; 1260 1261 divider->div.reg = cprman->regs + data->a2w_reg; 1262 divider->div.shift = A2W_PLL_DIV_SHIFT; 1263 divider->div.width = A2W_PLL_DIV_BITS; 1264 divider->div.flags = CLK_DIVIDER_MAX_AT_ZERO; 1265 divider->div.lock = &cprman->regs_lock; 1266 divider->div.hw.init = &init; 1267 divider->div.table = NULL; 1268 1269 divider->cprman = cprman; 1270 divider->data = data; 1271 1272 ret = devm_clk_hw_register(cprman->dev, ÷r->div.hw); 1273 if (ret) 1274 return ERR_PTR(ret); 1275 1276 /* 1277 * PLLH's channels have a fixed divide by 10 afterwards, which 1278 * is what our consumers are actually using. 1279 */ 1280 if (data->fixed_divider != 1) { 1281 return clk_hw_register_fixed_factor(cprman->dev, data->name, 1282 divider_name, 1283 CLK_SET_RATE_PARENT, 1284 1, 1285 data->fixed_divider); 1286 } 1287 1288 return ÷r->div.hw; 1289 } 1290 1291 static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman, 1292 const struct bcm2835_clock_data *data) 1293 { 1294 struct bcm2835_clock *clock; 1295 struct clk_init_data init; 1296 const char *parents[1 << CM_SRC_BITS]; 1297 size_t i; 1298 int ret; 1299 1300 /* 1301 * Replace our "xosc" references with the oscillator's 1302 * actual name. 1303 */ 1304 for (i = 0; i < data->num_mux_parents; i++) { 1305 if (strcmp(data->parents[i], "xosc") == 0) 1306 parents[i] = cprman->osc_name; 1307 else 1308 parents[i] = data->parents[i]; 1309 } 1310 1311 memset(&init, 0, sizeof(init)); 1312 init.parent_names = parents; 1313 init.num_parents = data->num_mux_parents; 1314 init.name = data->name; 1315 init.flags = data->flags | CLK_IGNORE_UNUSED; 1316 1317 /* 1318 * Pass the CLK_SET_RATE_PARENT flag if we are allowed to propagate 1319 * rate changes on at least of the parents. 1320 */ 1321 if (data->set_rate_parent) 1322 init.flags |= CLK_SET_RATE_PARENT; 1323 1324 if (data->is_vpu_clock) { 1325 init.ops = &bcm2835_vpu_clock_clk_ops; 1326 } else { 1327 init.ops = &bcm2835_clock_clk_ops; 1328 init.flags |= CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; 1329 1330 /* If the clock wasn't actually enabled at boot, it's not 1331 * critical. 1332 */ 1333 if (!(cprman_read(cprman, data->ctl_reg) & CM_ENABLE)) 1334 init.flags &= ~CLK_IS_CRITICAL; 1335 } 1336 1337 clock = devm_kzalloc(cprman->dev, sizeof(*clock), GFP_KERNEL); 1338 if (!clock) 1339 return NULL; 1340 1341 clock->cprman = cprman; 1342 clock->data = data; 1343 clock->hw.init = &init; 1344 1345 ret = devm_clk_hw_register(cprman->dev, &clock->hw); 1346 if (ret) 1347 return ERR_PTR(ret); 1348 return &clock->hw; 1349 } 1350 1351 static struct clk *bcm2835_register_gate(struct bcm2835_cprman *cprman, 1352 const struct bcm2835_gate_data *data) 1353 { 1354 return clk_register_gate(cprman->dev, data->name, data->parent, 1355 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 1356 cprman->regs + data->ctl_reg, 1357 CM_GATE_BIT, 0, &cprman->regs_lock); 1358 } 1359 1360 typedef struct clk_hw *(*bcm2835_clk_register)(struct bcm2835_cprman *cprman, 1361 const void *data); 1362 struct bcm2835_clk_desc { 1363 bcm2835_clk_register clk_register; 1364 const void *data; 1365 }; 1366 1367 /* assignment helper macros for different clock types */ 1368 #define _REGISTER(f, ...) { .clk_register = (bcm2835_clk_register)f, \ 1369 .data = __VA_ARGS__ } 1370 #define REGISTER_PLL(...) _REGISTER(&bcm2835_register_pll, \ 1371 &(struct bcm2835_pll_data) \ 1372 {__VA_ARGS__}) 1373 #define REGISTER_PLL_DIV(...) _REGISTER(&bcm2835_register_pll_divider, \ 1374 &(struct bcm2835_pll_divider_data) \ 1375 {__VA_ARGS__}) 1376 #define REGISTER_CLK(...) _REGISTER(&bcm2835_register_clock, \ 1377 &(struct bcm2835_clock_data) \ 1378 {__VA_ARGS__}) 1379 #define REGISTER_GATE(...) _REGISTER(&bcm2835_register_gate, \ 1380 &(struct bcm2835_gate_data) \ 1381 {__VA_ARGS__}) 1382 1383 /* parent mux arrays plus helper macros */ 1384 1385 /* main oscillator parent mux */ 1386 static const char *const bcm2835_clock_osc_parents[] = { 1387 "gnd", 1388 "xosc", 1389 "testdebug0", 1390 "testdebug1" 1391 }; 1392 1393 #define REGISTER_OSC_CLK(...) REGISTER_CLK( \ 1394 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents), \ 1395 .parents = bcm2835_clock_osc_parents, \ 1396 __VA_ARGS__) 1397 1398 /* main peripherial parent mux */ 1399 static const char *const bcm2835_clock_per_parents[] = { 1400 "gnd", 1401 "xosc", 1402 "testdebug0", 1403 "testdebug1", 1404 "plla_per", 1405 "pllc_per", 1406 "plld_per", 1407 "pllh_aux", 1408 }; 1409 1410 #define REGISTER_PER_CLK(...) REGISTER_CLK( \ 1411 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), \ 1412 .parents = bcm2835_clock_per_parents, \ 1413 __VA_ARGS__) 1414 1415 /* main vpu parent mux */ 1416 static const char *const bcm2835_clock_vpu_parents[] = { 1417 "gnd", 1418 "xosc", 1419 "testdebug0", 1420 "testdebug1", 1421 "plla_core", 1422 "pllc_core0", 1423 "plld_core", 1424 "pllh_aux", 1425 "pllc_core1", 1426 "pllc_core2", 1427 }; 1428 1429 #define REGISTER_VPU_CLK(...) REGISTER_CLK( \ 1430 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), \ 1431 .parents = bcm2835_clock_vpu_parents, \ 1432 __VA_ARGS__) 1433 1434 /* 1435 * the real definition of all the pll, pll_dividers and clocks 1436 * these make use of the above REGISTER_* macros 1437 */ 1438 static const struct bcm2835_clk_desc clk_desc_array[] = { 1439 /* the PLL + PLL dividers */ 1440 1441 /* 1442 * PLLA is the auxiliary PLL, used to drive the CCP2 1443 * (Compact Camera Port 2) transmitter clock. 1444 * 1445 * It is in the PX LDO power domain, which is on when the 1446 * AUDIO domain is on. 1447 */ 1448 [BCM2835_PLLA] = REGISTER_PLL( 1449 .name = "plla", 1450 .cm_ctrl_reg = CM_PLLA, 1451 .a2w_ctrl_reg = A2W_PLLA_CTRL, 1452 .frac_reg = A2W_PLLA_FRAC, 1453 .ana_reg_base = A2W_PLLA_ANA0, 1454 .reference_enable_mask = A2W_XOSC_CTRL_PLLA_ENABLE, 1455 .lock_mask = CM_LOCK_FLOCKA, 1456 1457 .ana = &bcm2835_ana_default, 1458 1459 .min_rate = 600000000u, 1460 .max_rate = 2400000000u, 1461 .max_fb_rate = BCM2835_MAX_FB_RATE), 1462 [BCM2835_PLLA_CORE] = REGISTER_PLL_DIV( 1463 .name = "plla_core", 1464 .source_pll = "plla", 1465 .cm_reg = CM_PLLA, 1466 .a2w_reg = A2W_PLLA_CORE, 1467 .load_mask = CM_PLLA_LOADCORE, 1468 .hold_mask = CM_PLLA_HOLDCORE, 1469 .fixed_divider = 1), 1470 [BCM2835_PLLA_PER] = REGISTER_PLL_DIV( 1471 .name = "plla_per", 1472 .source_pll = "plla", 1473 .cm_reg = CM_PLLA, 1474 .a2w_reg = A2W_PLLA_PER, 1475 .load_mask = CM_PLLA_LOADPER, 1476 .hold_mask = CM_PLLA_HOLDPER, 1477 .fixed_divider = 1), 1478 [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV( 1479 .name = "plla_dsi0", 1480 .source_pll = "plla", 1481 .cm_reg = CM_PLLA, 1482 .a2w_reg = A2W_PLLA_DSI0, 1483 .load_mask = CM_PLLA_LOADDSI0, 1484 .hold_mask = CM_PLLA_HOLDDSI0, 1485 .fixed_divider = 1), 1486 [BCM2835_PLLA_CCP2] = REGISTER_PLL_DIV( 1487 .name = "plla_ccp2", 1488 .source_pll = "plla", 1489 .cm_reg = CM_PLLA, 1490 .a2w_reg = A2W_PLLA_CCP2, 1491 .load_mask = CM_PLLA_LOADCCP2, 1492 .hold_mask = CM_PLLA_HOLDCCP2, 1493 .fixed_divider = 1), 1494 1495 /* PLLB is used for the ARM's clock. */ 1496 [BCM2835_PLLB] = REGISTER_PLL( 1497 .name = "pllb", 1498 .cm_ctrl_reg = CM_PLLB, 1499 .a2w_ctrl_reg = A2W_PLLB_CTRL, 1500 .frac_reg = A2W_PLLB_FRAC, 1501 .ana_reg_base = A2W_PLLB_ANA0, 1502 .reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE, 1503 .lock_mask = CM_LOCK_FLOCKB, 1504 1505 .ana = &bcm2835_ana_default, 1506 1507 .min_rate = 600000000u, 1508 .max_rate = 3000000000u, 1509 .max_fb_rate = BCM2835_MAX_FB_RATE), 1510 [BCM2835_PLLB_ARM] = REGISTER_PLL_DIV( 1511 .name = "pllb_arm", 1512 .source_pll = "pllb", 1513 .cm_reg = CM_PLLB, 1514 .a2w_reg = A2W_PLLB_ARM, 1515 .load_mask = CM_PLLB_LOADARM, 1516 .hold_mask = CM_PLLB_HOLDARM, 1517 .fixed_divider = 1), 1518 1519 /* 1520 * PLLC is the core PLL, used to drive the core VPU clock. 1521 * 1522 * It is in the PX LDO power domain, which is on when the 1523 * AUDIO domain is on. 1524 */ 1525 [BCM2835_PLLC] = REGISTER_PLL( 1526 .name = "pllc", 1527 .cm_ctrl_reg = CM_PLLC, 1528 .a2w_ctrl_reg = A2W_PLLC_CTRL, 1529 .frac_reg = A2W_PLLC_FRAC, 1530 .ana_reg_base = A2W_PLLC_ANA0, 1531 .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE, 1532 .lock_mask = CM_LOCK_FLOCKC, 1533 1534 .ana = &bcm2835_ana_default, 1535 1536 .min_rate = 600000000u, 1537 .max_rate = 3000000000u, 1538 .max_fb_rate = BCM2835_MAX_FB_RATE), 1539 [BCM2835_PLLC_CORE0] = REGISTER_PLL_DIV( 1540 .name = "pllc_core0", 1541 .source_pll = "pllc", 1542 .cm_reg = CM_PLLC, 1543 .a2w_reg = A2W_PLLC_CORE0, 1544 .load_mask = CM_PLLC_LOADCORE0, 1545 .hold_mask = CM_PLLC_HOLDCORE0, 1546 .fixed_divider = 1), 1547 [BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV( 1548 .name = "pllc_core1", 1549 .source_pll = "pllc", 1550 .cm_reg = CM_PLLC, 1551 .a2w_reg = A2W_PLLC_CORE1, 1552 .load_mask = CM_PLLC_LOADCORE1, 1553 .hold_mask = CM_PLLC_HOLDCORE1, 1554 .fixed_divider = 1), 1555 [BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV( 1556 .name = "pllc_core2", 1557 .source_pll = "pllc", 1558 .cm_reg = CM_PLLC, 1559 .a2w_reg = A2W_PLLC_CORE2, 1560 .load_mask = CM_PLLC_LOADCORE2, 1561 .hold_mask = CM_PLLC_HOLDCORE2, 1562 .fixed_divider = 1), 1563 [BCM2835_PLLC_PER] = REGISTER_PLL_DIV( 1564 .name = "pllc_per", 1565 .source_pll = "pllc", 1566 .cm_reg = CM_PLLC, 1567 .a2w_reg = A2W_PLLC_PER, 1568 .load_mask = CM_PLLC_LOADPER, 1569 .hold_mask = CM_PLLC_HOLDPER, 1570 .fixed_divider = 1), 1571 1572 /* 1573 * PLLD is the display PLL, used to drive DSI display panels. 1574 * 1575 * It is in the PX LDO power domain, which is on when the 1576 * AUDIO domain is on. 1577 */ 1578 [BCM2835_PLLD] = REGISTER_PLL( 1579 .name = "plld", 1580 .cm_ctrl_reg = CM_PLLD, 1581 .a2w_ctrl_reg = A2W_PLLD_CTRL, 1582 .frac_reg = A2W_PLLD_FRAC, 1583 .ana_reg_base = A2W_PLLD_ANA0, 1584 .reference_enable_mask = A2W_XOSC_CTRL_DDR_ENABLE, 1585 .lock_mask = CM_LOCK_FLOCKD, 1586 1587 .ana = &bcm2835_ana_default, 1588 1589 .min_rate = 600000000u, 1590 .max_rate = 2400000000u, 1591 .max_fb_rate = BCM2835_MAX_FB_RATE), 1592 [BCM2835_PLLD_CORE] = REGISTER_PLL_DIV( 1593 .name = "plld_core", 1594 .source_pll = "plld", 1595 .cm_reg = CM_PLLD, 1596 .a2w_reg = A2W_PLLD_CORE, 1597 .load_mask = CM_PLLD_LOADCORE, 1598 .hold_mask = CM_PLLD_HOLDCORE, 1599 .fixed_divider = 1), 1600 [BCM2835_PLLD_PER] = REGISTER_PLL_DIV( 1601 .name = "plld_per", 1602 .source_pll = "plld", 1603 .cm_reg = CM_PLLD, 1604 .a2w_reg = A2W_PLLD_PER, 1605 .load_mask = CM_PLLD_LOADPER, 1606 .hold_mask = CM_PLLD_HOLDPER, 1607 .fixed_divider = 1), 1608 [BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV( 1609 .name = "plld_dsi0", 1610 .source_pll = "plld", 1611 .cm_reg = CM_PLLD, 1612 .a2w_reg = A2W_PLLD_DSI0, 1613 .load_mask = CM_PLLD_LOADDSI0, 1614 .hold_mask = CM_PLLD_HOLDDSI0, 1615 .fixed_divider = 1), 1616 [BCM2835_PLLD_DSI1] = REGISTER_PLL_DIV( 1617 .name = "plld_dsi1", 1618 .source_pll = "plld", 1619 .cm_reg = CM_PLLD, 1620 .a2w_reg = A2W_PLLD_DSI1, 1621 .load_mask = CM_PLLD_LOADDSI1, 1622 .hold_mask = CM_PLLD_HOLDDSI1, 1623 .fixed_divider = 1), 1624 1625 /* 1626 * PLLH is used to supply the pixel clock or the AUX clock for the 1627 * TV encoder. 1628 * 1629 * It is in the HDMI power domain. 1630 */ 1631 [BCM2835_PLLH] = REGISTER_PLL( 1632 "pllh", 1633 .cm_ctrl_reg = CM_PLLH, 1634 .a2w_ctrl_reg = A2W_PLLH_CTRL, 1635 .frac_reg = A2W_PLLH_FRAC, 1636 .ana_reg_base = A2W_PLLH_ANA0, 1637 .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE, 1638 .lock_mask = CM_LOCK_FLOCKH, 1639 1640 .ana = &bcm2835_ana_pllh, 1641 1642 .min_rate = 600000000u, 1643 .max_rate = 3000000000u, 1644 .max_fb_rate = BCM2835_MAX_FB_RATE), 1645 [BCM2835_PLLH_RCAL] = REGISTER_PLL_DIV( 1646 .name = "pllh_rcal", 1647 .source_pll = "pllh", 1648 .cm_reg = CM_PLLH, 1649 .a2w_reg = A2W_PLLH_RCAL, 1650 .load_mask = CM_PLLH_LOADRCAL, 1651 .hold_mask = 0, 1652 .fixed_divider = 10), 1653 [BCM2835_PLLH_AUX] = REGISTER_PLL_DIV( 1654 .name = "pllh_aux", 1655 .source_pll = "pllh", 1656 .cm_reg = CM_PLLH, 1657 .a2w_reg = A2W_PLLH_AUX, 1658 .load_mask = CM_PLLH_LOADAUX, 1659 .hold_mask = 0, 1660 .fixed_divider = 1), 1661 [BCM2835_PLLH_PIX] = REGISTER_PLL_DIV( 1662 .name = "pllh_pix", 1663 .source_pll = "pllh", 1664 .cm_reg = CM_PLLH, 1665 .a2w_reg = A2W_PLLH_PIX, 1666 .load_mask = CM_PLLH_LOADPIX, 1667 .hold_mask = 0, 1668 .fixed_divider = 10), 1669 1670 /* the clocks */ 1671 1672 /* clocks with oscillator parent mux */ 1673 1674 /* One Time Programmable Memory clock. Maximum 10Mhz. */ 1675 [BCM2835_CLOCK_OTP] = REGISTER_OSC_CLK( 1676 .name = "otp", 1677 .ctl_reg = CM_OTPCTL, 1678 .div_reg = CM_OTPDIV, 1679 .int_bits = 4, 1680 .frac_bits = 0), 1681 /* 1682 * Used for a 1Mhz clock for the system clocksource, and also used 1683 * bythe watchdog timer and the camera pulse generator. 1684 */ 1685 [BCM2835_CLOCK_TIMER] = REGISTER_OSC_CLK( 1686 .name = "timer", 1687 .ctl_reg = CM_TIMERCTL, 1688 .div_reg = CM_TIMERDIV, 1689 .int_bits = 6, 1690 .frac_bits = 12), 1691 /* 1692 * Clock for the temperature sensor. 1693 * Generally run at 2Mhz, max 5Mhz. 1694 */ 1695 [BCM2835_CLOCK_TSENS] = REGISTER_OSC_CLK( 1696 .name = "tsens", 1697 .ctl_reg = CM_TSENSCTL, 1698 .div_reg = CM_TSENSDIV, 1699 .int_bits = 5, 1700 .frac_bits = 0), 1701 [BCM2835_CLOCK_TEC] = REGISTER_OSC_CLK( 1702 .name = "tec", 1703 .ctl_reg = CM_TECCTL, 1704 .div_reg = CM_TECDIV, 1705 .int_bits = 6, 1706 .frac_bits = 0), 1707 1708 /* clocks with vpu parent mux */ 1709 [BCM2835_CLOCK_H264] = REGISTER_VPU_CLK( 1710 .name = "h264", 1711 .ctl_reg = CM_H264CTL, 1712 .div_reg = CM_H264DIV, 1713 .int_bits = 4, 1714 .frac_bits = 8), 1715 [BCM2835_CLOCK_ISP] = REGISTER_VPU_CLK( 1716 .name = "isp", 1717 .ctl_reg = CM_ISPCTL, 1718 .div_reg = CM_ISPDIV, 1719 .int_bits = 4, 1720 .frac_bits = 8), 1721 1722 /* 1723 * Secondary SDRAM clock. Used for low-voltage modes when the PLL 1724 * in the SDRAM controller can't be used. 1725 */ 1726 [BCM2835_CLOCK_SDRAM] = REGISTER_VPU_CLK( 1727 .name = "sdram", 1728 .ctl_reg = CM_SDCCTL, 1729 .div_reg = CM_SDCDIV, 1730 .int_bits = 6, 1731 .frac_bits = 0), 1732 [BCM2835_CLOCK_V3D] = REGISTER_VPU_CLK( 1733 .name = "v3d", 1734 .ctl_reg = CM_V3DCTL, 1735 .div_reg = CM_V3DDIV, 1736 .int_bits = 4, 1737 .frac_bits = 8), 1738 /* 1739 * VPU clock. This doesn't have an enable bit, since it drives 1740 * the bus for everything else, and is special so it doesn't need 1741 * to be gated for rate changes. It is also known as "clk_audio" 1742 * in various hardware documentation. 1743 */ 1744 [BCM2835_CLOCK_VPU] = REGISTER_VPU_CLK( 1745 .name = "vpu", 1746 .ctl_reg = CM_VPUCTL, 1747 .div_reg = CM_VPUDIV, 1748 .int_bits = 12, 1749 .frac_bits = 8, 1750 .flags = CLK_IS_CRITICAL, 1751 .is_vpu_clock = true), 1752 1753 /* clocks with per parent mux */ 1754 [BCM2835_CLOCK_AVEO] = REGISTER_PER_CLK( 1755 .name = "aveo", 1756 .ctl_reg = CM_AVEOCTL, 1757 .div_reg = CM_AVEODIV, 1758 .int_bits = 4, 1759 .frac_bits = 0), 1760 [BCM2835_CLOCK_CAM0] = REGISTER_PER_CLK( 1761 .name = "cam0", 1762 .ctl_reg = CM_CAM0CTL, 1763 .div_reg = CM_CAM0DIV, 1764 .int_bits = 4, 1765 .frac_bits = 8), 1766 [BCM2835_CLOCK_CAM1] = REGISTER_PER_CLK( 1767 .name = "cam1", 1768 .ctl_reg = CM_CAM1CTL, 1769 .div_reg = CM_CAM1DIV, 1770 .int_bits = 4, 1771 .frac_bits = 8), 1772 [BCM2835_CLOCK_DFT] = REGISTER_PER_CLK( 1773 .name = "dft", 1774 .ctl_reg = CM_DFTCTL, 1775 .div_reg = CM_DFTDIV, 1776 .int_bits = 5, 1777 .frac_bits = 0), 1778 [BCM2835_CLOCK_DPI] = REGISTER_PER_CLK( 1779 .name = "dpi", 1780 .ctl_reg = CM_DPICTL, 1781 .div_reg = CM_DPIDIV, 1782 .int_bits = 4, 1783 .frac_bits = 8), 1784 1785 /* Arasan EMMC clock */ 1786 [BCM2835_CLOCK_EMMC] = REGISTER_PER_CLK( 1787 .name = "emmc", 1788 .ctl_reg = CM_EMMCCTL, 1789 .div_reg = CM_EMMCDIV, 1790 .int_bits = 4, 1791 .frac_bits = 8), 1792 1793 /* General purpose (GPIO) clocks */ 1794 [BCM2835_CLOCK_GP0] = REGISTER_PER_CLK( 1795 .name = "gp0", 1796 .ctl_reg = CM_GP0CTL, 1797 .div_reg = CM_GP0DIV, 1798 .int_bits = 12, 1799 .frac_bits = 12, 1800 .is_mash_clock = true), 1801 [BCM2835_CLOCK_GP1] = REGISTER_PER_CLK( 1802 .name = "gp1", 1803 .ctl_reg = CM_GP1CTL, 1804 .div_reg = CM_GP1DIV, 1805 .int_bits = 12, 1806 .frac_bits = 12, 1807 .flags = CLK_IS_CRITICAL, 1808 .is_mash_clock = true), 1809 [BCM2835_CLOCK_GP2] = REGISTER_PER_CLK( 1810 .name = "gp2", 1811 .ctl_reg = CM_GP2CTL, 1812 .div_reg = CM_GP2DIV, 1813 .int_bits = 12, 1814 .frac_bits = 12, 1815 .flags = CLK_IS_CRITICAL), 1816 1817 /* HDMI state machine */ 1818 [BCM2835_CLOCK_HSM] = REGISTER_PER_CLK( 1819 .name = "hsm", 1820 .ctl_reg = CM_HSMCTL, 1821 .div_reg = CM_HSMDIV, 1822 .int_bits = 4, 1823 .frac_bits = 8), 1824 [BCM2835_CLOCK_PCM] = REGISTER_PER_CLK( 1825 .name = "pcm", 1826 .ctl_reg = CM_PCMCTL, 1827 .div_reg = CM_PCMDIV, 1828 .int_bits = 12, 1829 .frac_bits = 12, 1830 .is_mash_clock = true), 1831 [BCM2835_CLOCK_PWM] = REGISTER_PER_CLK( 1832 .name = "pwm", 1833 .ctl_reg = CM_PWMCTL, 1834 .div_reg = CM_PWMDIV, 1835 .int_bits = 12, 1836 .frac_bits = 12, 1837 .is_mash_clock = true), 1838 [BCM2835_CLOCK_SLIM] = REGISTER_PER_CLK( 1839 .name = "slim", 1840 .ctl_reg = CM_SLIMCTL, 1841 .div_reg = CM_SLIMDIV, 1842 .int_bits = 12, 1843 .frac_bits = 12, 1844 .is_mash_clock = true), 1845 [BCM2835_CLOCK_SMI] = REGISTER_PER_CLK( 1846 .name = "smi", 1847 .ctl_reg = CM_SMICTL, 1848 .div_reg = CM_SMIDIV, 1849 .int_bits = 4, 1850 .frac_bits = 8), 1851 [BCM2835_CLOCK_UART] = REGISTER_PER_CLK( 1852 .name = "uart", 1853 .ctl_reg = CM_UARTCTL, 1854 .div_reg = CM_UARTDIV, 1855 .int_bits = 10, 1856 .frac_bits = 12), 1857 1858 /* TV encoder clock. Only operating frequency is 108Mhz. */ 1859 [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK( 1860 .name = "vec", 1861 .ctl_reg = CM_VECCTL, 1862 .div_reg = CM_VECDIV, 1863 .int_bits = 4, 1864 .frac_bits = 0, 1865 /* 1866 * Allow rate change propagation only on PLLH_AUX which is 1867 * assigned index 7 in the parent array. 1868 */ 1869 .set_rate_parent = BIT(7)), 1870 1871 /* dsi clocks */ 1872 [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK( 1873 .name = "dsi0e", 1874 .ctl_reg = CM_DSI0ECTL, 1875 .div_reg = CM_DSI0EDIV, 1876 .int_bits = 4, 1877 .frac_bits = 8), 1878 [BCM2835_CLOCK_DSI1E] = REGISTER_PER_CLK( 1879 .name = "dsi1e", 1880 .ctl_reg = CM_DSI1ECTL, 1881 .div_reg = CM_DSI1EDIV, 1882 .int_bits = 4, 1883 .frac_bits = 8), 1884 1885 /* the gates */ 1886 1887 /* 1888 * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if 1889 * you have the debug bit set in the power manager, which we 1890 * don't bother exposing) are individual gates off of the 1891 * non-stop vpu clock. 1892 */ 1893 [BCM2835_CLOCK_PERI_IMAGE] = REGISTER_GATE( 1894 .name = "peri_image", 1895 .parent = "vpu", 1896 .ctl_reg = CM_PERIICTL), 1897 }; 1898 1899 /* 1900 * Permanently take a reference on the parent of the SDRAM clock. 1901 * 1902 * While the SDRAM is being driven by its dedicated PLL most of the 1903 * time, there is a little loop running in the firmware that 1904 * periodically switches the SDRAM to using our CM clock to do PVT 1905 * recalibration, with the assumption that the previously configured 1906 * SDRAM parent is still enabled and running. 1907 */ 1908 static int bcm2835_mark_sdc_parent_critical(struct clk *sdc) 1909 { 1910 struct clk *parent = clk_get_parent(sdc); 1911 1912 if (IS_ERR(parent)) 1913 return PTR_ERR(parent); 1914 1915 return clk_prepare_enable(parent); 1916 } 1917 1918 static int bcm2835_clk_probe(struct platform_device *pdev) 1919 { 1920 struct device *dev = &pdev->dev; 1921 struct clk_hw **hws; 1922 struct bcm2835_cprman *cprman; 1923 struct resource *res; 1924 const struct bcm2835_clk_desc *desc; 1925 const size_t asize = ARRAY_SIZE(clk_desc_array); 1926 size_t i; 1927 int ret; 1928 1929 cprman = devm_kzalloc(dev, sizeof(*cprman) + 1930 sizeof(*cprman->onecell.hws) * asize, 1931 GFP_KERNEL); 1932 if (!cprman) 1933 return -ENOMEM; 1934 1935 spin_lock_init(&cprman->regs_lock); 1936 cprman->dev = dev; 1937 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1938 cprman->regs = devm_ioremap_resource(dev, res); 1939 if (IS_ERR(cprman->regs)) 1940 return PTR_ERR(cprman->regs); 1941 1942 cprman->osc_name = of_clk_get_parent_name(dev->of_node, 0); 1943 if (!cprman->osc_name) 1944 return -ENODEV; 1945 1946 platform_set_drvdata(pdev, cprman); 1947 1948 cprman->onecell.num = asize; 1949 hws = cprman->onecell.hws; 1950 1951 for (i = 0; i < asize; i++) { 1952 desc = &clk_desc_array[i]; 1953 if (desc->clk_register && desc->data) 1954 hws[i] = desc->clk_register(cprman, desc->data); 1955 } 1956 1957 ret = bcm2835_mark_sdc_parent_critical(hws[BCM2835_CLOCK_SDRAM]->clk); 1958 if (ret) 1959 return ret; 1960 1961 return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, 1962 &cprman->onecell); 1963 } 1964 1965 static const struct of_device_id bcm2835_clk_of_match[] = { 1966 { .compatible = "brcm,bcm2835-cprman", }, 1967 {} 1968 }; 1969 MODULE_DEVICE_TABLE(of, bcm2835_clk_of_match); 1970 1971 static struct platform_driver bcm2835_clk_driver = { 1972 .driver = { 1973 .name = "bcm2835-clk", 1974 .of_match_table = bcm2835_clk_of_match, 1975 }, 1976 .probe = bcm2835_clk_probe, 1977 }; 1978 1979 builtin_platform_driver(bcm2835_clk_driver); 1980 1981 MODULE_AUTHOR("Eric Anholt <eric@anholt.net>"); 1982 MODULE_DESCRIPTION("BCM2835 clock driver"); 1983 MODULE_LICENSE("GPL v2"); 1984