1 /* 2 * Copyright (C) 2010,2015 Broadcom 3 * Copyright (C) 2012 Stephen Warren 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 */ 16 17 /** 18 * DOC: BCM2835 CPRMAN (clock manager for the "audio" domain) 19 * 20 * The clock tree on the 2835 has several levels. There's a root 21 * oscillator running at 19.2Mhz. After the oscillator there are 5 22 * PLLs, roughly divided as "camera", "ARM", "core", "DSI displays", 23 * and "HDMI displays". Those 5 PLLs each can divide their output to 24 * produce up to 4 channels. Finally, there is the level of clocks to 25 * be consumed by other hardware components (like "H264" or "HDMI 26 * state machine"), which divide off of some subset of the PLL 27 * channels. 28 * 29 * All of the clocks in the tree are exposed in the DT, because the DT 30 * may want to make assignments of the final layer of clocks to the 31 * PLL channels, and some components of the hardware will actually 32 * skip layers of the tree (for example, the pixel clock comes 33 * directly from the PLLH PIX channel without using a CM_*CTL clock 34 * generator). 35 */ 36 37 #include <linux/clk-provider.h> 38 #include <linux/clkdev.h> 39 #include <linux/clk.h> 40 #include <linux/clk/bcm2835.h> 41 #include <linux/debugfs.h> 42 #include <linux/delay.h> 43 #include <linux/module.h> 44 #include <linux/of.h> 45 #include <linux/platform_device.h> 46 #include <linux/slab.h> 47 #include <dt-bindings/clock/bcm2835.h> 48 49 #define CM_PASSWORD 0x5a000000 50 51 #define CM_GNRICCTL 0x000 52 #define CM_GNRICDIV 0x004 53 # define CM_DIV_FRAC_BITS 12 54 # define CM_DIV_FRAC_MASK GENMASK(CM_DIV_FRAC_BITS - 1, 0) 55 56 #define CM_VPUCTL 0x008 57 #define CM_VPUDIV 0x00c 58 #define CM_SYSCTL 0x010 59 #define CM_SYSDIV 0x014 60 #define CM_PERIACTL 0x018 61 #define CM_PERIADIV 0x01c 62 #define CM_PERIICTL 0x020 63 #define CM_PERIIDIV 0x024 64 #define CM_H264CTL 0x028 65 #define CM_H264DIV 0x02c 66 #define CM_ISPCTL 0x030 67 #define CM_ISPDIV 0x034 68 #define CM_V3DCTL 0x038 69 #define CM_V3DDIV 0x03c 70 #define CM_CAM0CTL 0x040 71 #define CM_CAM0DIV 0x044 72 #define CM_CAM1CTL 0x048 73 #define CM_CAM1DIV 0x04c 74 #define CM_CCP2CTL 0x050 75 #define CM_CCP2DIV 0x054 76 #define CM_DSI0ECTL 0x058 77 #define CM_DSI0EDIV 0x05c 78 #define CM_DSI0PCTL 0x060 79 #define CM_DSI0PDIV 0x064 80 #define CM_DPICTL 0x068 81 #define CM_DPIDIV 0x06c 82 #define CM_GP0CTL 0x070 83 #define CM_GP0DIV 0x074 84 #define CM_GP1CTL 0x078 85 #define CM_GP1DIV 0x07c 86 #define CM_GP2CTL 0x080 87 #define CM_GP2DIV 0x084 88 #define CM_HSMCTL 0x088 89 #define CM_HSMDIV 0x08c 90 #define CM_OTPCTL 0x090 91 #define CM_OTPDIV 0x094 92 #define CM_PCMCTL 0x098 93 #define CM_PCMDIV 0x09c 94 #define CM_PWMCTL 0x0a0 95 #define CM_PWMDIV 0x0a4 96 #define CM_SLIMCTL 0x0a8 97 #define CM_SLIMDIV 0x0ac 98 #define CM_SMICTL 0x0b0 99 #define CM_SMIDIV 0x0b4 100 /* no definition for 0x0b8 and 0x0bc */ 101 #define CM_TCNTCTL 0x0c0 102 # define CM_TCNT_SRC1_SHIFT 12 103 #define CM_TCNTCNT 0x0c4 104 #define CM_TECCTL 0x0c8 105 #define CM_TECDIV 0x0cc 106 #define CM_TD0CTL 0x0d0 107 #define CM_TD0DIV 0x0d4 108 #define CM_TD1CTL 0x0d8 109 #define CM_TD1DIV 0x0dc 110 #define CM_TSENSCTL 0x0e0 111 #define CM_TSENSDIV 0x0e4 112 #define CM_TIMERCTL 0x0e8 113 #define CM_TIMERDIV 0x0ec 114 #define CM_UARTCTL 0x0f0 115 #define CM_UARTDIV 0x0f4 116 #define CM_VECCTL 0x0f8 117 #define CM_VECDIV 0x0fc 118 #define CM_PULSECTL 0x190 119 #define CM_PULSEDIV 0x194 120 #define CM_SDCCTL 0x1a8 121 #define CM_SDCDIV 0x1ac 122 #define CM_ARMCTL 0x1b0 123 #define CM_AVEOCTL 0x1b8 124 #define CM_AVEODIV 0x1bc 125 #define CM_EMMCCTL 0x1c0 126 #define CM_EMMCDIV 0x1c4 127 128 /* General bits for the CM_*CTL regs */ 129 # define CM_ENABLE BIT(4) 130 # define CM_KILL BIT(5) 131 # define CM_GATE_BIT 6 132 # define CM_GATE BIT(CM_GATE_BIT) 133 # define CM_BUSY BIT(7) 134 # define CM_BUSYD BIT(8) 135 # define CM_FRAC BIT(9) 136 # define CM_SRC_SHIFT 0 137 # define CM_SRC_BITS 4 138 # define CM_SRC_MASK 0xf 139 # define CM_SRC_GND 0 140 # define CM_SRC_OSC 1 141 # define CM_SRC_TESTDEBUG0 2 142 # define CM_SRC_TESTDEBUG1 3 143 # define CM_SRC_PLLA_CORE 4 144 # define CM_SRC_PLLA_PER 4 145 # define CM_SRC_PLLC_CORE0 5 146 # define CM_SRC_PLLC_PER 5 147 # define CM_SRC_PLLC_CORE1 8 148 # define CM_SRC_PLLD_CORE 6 149 # define CM_SRC_PLLD_PER 6 150 # define CM_SRC_PLLH_AUX 7 151 # define CM_SRC_PLLC_CORE1 8 152 # define CM_SRC_PLLC_CORE2 9 153 154 #define CM_OSCCOUNT 0x100 155 156 #define CM_PLLA 0x104 157 # define CM_PLL_ANARST BIT(8) 158 # define CM_PLLA_HOLDPER BIT(7) 159 # define CM_PLLA_LOADPER BIT(6) 160 # define CM_PLLA_HOLDCORE BIT(5) 161 # define CM_PLLA_LOADCORE BIT(4) 162 # define CM_PLLA_HOLDCCP2 BIT(3) 163 # define CM_PLLA_LOADCCP2 BIT(2) 164 # define CM_PLLA_HOLDDSI0 BIT(1) 165 # define CM_PLLA_LOADDSI0 BIT(0) 166 167 #define CM_PLLC 0x108 168 # define CM_PLLC_HOLDPER BIT(7) 169 # define CM_PLLC_LOADPER BIT(6) 170 # define CM_PLLC_HOLDCORE2 BIT(5) 171 # define CM_PLLC_LOADCORE2 BIT(4) 172 # define CM_PLLC_HOLDCORE1 BIT(3) 173 # define CM_PLLC_LOADCORE1 BIT(2) 174 # define CM_PLLC_HOLDCORE0 BIT(1) 175 # define CM_PLLC_LOADCORE0 BIT(0) 176 177 #define CM_PLLD 0x10c 178 # define CM_PLLD_HOLDPER BIT(7) 179 # define CM_PLLD_LOADPER BIT(6) 180 # define CM_PLLD_HOLDCORE BIT(5) 181 # define CM_PLLD_LOADCORE BIT(4) 182 # define CM_PLLD_HOLDDSI1 BIT(3) 183 # define CM_PLLD_LOADDSI1 BIT(2) 184 # define CM_PLLD_HOLDDSI0 BIT(1) 185 # define CM_PLLD_LOADDSI0 BIT(0) 186 187 #define CM_PLLH 0x110 188 # define CM_PLLH_LOADRCAL BIT(2) 189 # define CM_PLLH_LOADAUX BIT(1) 190 # define CM_PLLH_LOADPIX BIT(0) 191 192 #define CM_LOCK 0x114 193 # define CM_LOCK_FLOCKH BIT(12) 194 # define CM_LOCK_FLOCKD BIT(11) 195 # define CM_LOCK_FLOCKC BIT(10) 196 # define CM_LOCK_FLOCKB BIT(9) 197 # define CM_LOCK_FLOCKA BIT(8) 198 199 #define CM_EVENT 0x118 200 #define CM_DSI1ECTL 0x158 201 #define CM_DSI1EDIV 0x15c 202 #define CM_DSI1PCTL 0x160 203 #define CM_DSI1PDIV 0x164 204 #define CM_DFTCTL 0x168 205 #define CM_DFTDIV 0x16c 206 207 #define CM_PLLB 0x170 208 # define CM_PLLB_HOLDARM BIT(1) 209 # define CM_PLLB_LOADARM BIT(0) 210 211 #define A2W_PLLA_CTRL 0x1100 212 #define A2W_PLLC_CTRL 0x1120 213 #define A2W_PLLD_CTRL 0x1140 214 #define A2W_PLLH_CTRL 0x1160 215 #define A2W_PLLB_CTRL 0x11e0 216 # define A2W_PLL_CTRL_PRST_DISABLE BIT(17) 217 # define A2W_PLL_CTRL_PWRDN BIT(16) 218 # define A2W_PLL_CTRL_PDIV_MASK 0x000007000 219 # define A2W_PLL_CTRL_PDIV_SHIFT 12 220 # define A2W_PLL_CTRL_NDIV_MASK 0x0000003ff 221 # define A2W_PLL_CTRL_NDIV_SHIFT 0 222 223 #define A2W_PLLA_ANA0 0x1010 224 #define A2W_PLLC_ANA0 0x1030 225 #define A2W_PLLD_ANA0 0x1050 226 #define A2W_PLLH_ANA0 0x1070 227 #define A2W_PLLB_ANA0 0x10f0 228 229 #define A2W_PLL_KA_SHIFT 7 230 #define A2W_PLL_KA_MASK GENMASK(9, 7) 231 #define A2W_PLL_KI_SHIFT 19 232 #define A2W_PLL_KI_MASK GENMASK(21, 19) 233 #define A2W_PLL_KP_SHIFT 15 234 #define A2W_PLL_KP_MASK GENMASK(18, 15) 235 236 #define A2W_PLLH_KA_SHIFT 19 237 #define A2W_PLLH_KA_MASK GENMASK(21, 19) 238 #define A2W_PLLH_KI_LOW_SHIFT 22 239 #define A2W_PLLH_KI_LOW_MASK GENMASK(23, 22) 240 #define A2W_PLLH_KI_HIGH_SHIFT 0 241 #define A2W_PLLH_KI_HIGH_MASK GENMASK(0, 0) 242 #define A2W_PLLH_KP_SHIFT 1 243 #define A2W_PLLH_KP_MASK GENMASK(4, 1) 244 245 #define A2W_XOSC_CTRL 0x1190 246 # define A2W_XOSC_CTRL_PLLB_ENABLE BIT(7) 247 # define A2W_XOSC_CTRL_PLLA_ENABLE BIT(6) 248 # define A2W_XOSC_CTRL_PLLD_ENABLE BIT(5) 249 # define A2W_XOSC_CTRL_DDR_ENABLE BIT(4) 250 # define A2W_XOSC_CTRL_CPR1_ENABLE BIT(3) 251 # define A2W_XOSC_CTRL_USB_ENABLE BIT(2) 252 # define A2W_XOSC_CTRL_HDMI_ENABLE BIT(1) 253 # define A2W_XOSC_CTRL_PLLC_ENABLE BIT(0) 254 255 #define A2W_PLLA_FRAC 0x1200 256 #define A2W_PLLC_FRAC 0x1220 257 #define A2W_PLLD_FRAC 0x1240 258 #define A2W_PLLH_FRAC 0x1260 259 #define A2W_PLLB_FRAC 0x12e0 260 # define A2W_PLL_FRAC_MASK ((1 << A2W_PLL_FRAC_BITS) - 1) 261 # define A2W_PLL_FRAC_BITS 20 262 263 #define A2W_PLL_CHANNEL_DISABLE BIT(8) 264 #define A2W_PLL_DIV_BITS 8 265 #define A2W_PLL_DIV_SHIFT 0 266 267 #define A2W_PLLA_DSI0 0x1300 268 #define A2W_PLLA_CORE 0x1400 269 #define A2W_PLLA_PER 0x1500 270 #define A2W_PLLA_CCP2 0x1600 271 272 #define A2W_PLLC_CORE2 0x1320 273 #define A2W_PLLC_CORE1 0x1420 274 #define A2W_PLLC_PER 0x1520 275 #define A2W_PLLC_CORE0 0x1620 276 277 #define A2W_PLLD_DSI0 0x1340 278 #define A2W_PLLD_CORE 0x1440 279 #define A2W_PLLD_PER 0x1540 280 #define A2W_PLLD_DSI1 0x1640 281 282 #define A2W_PLLH_AUX 0x1360 283 #define A2W_PLLH_RCAL 0x1460 284 #define A2W_PLLH_PIX 0x1560 285 #define A2W_PLLH_STS 0x1660 286 287 #define A2W_PLLH_CTRLR 0x1960 288 #define A2W_PLLH_FRACR 0x1a60 289 #define A2W_PLLH_AUXR 0x1b60 290 #define A2W_PLLH_RCALR 0x1c60 291 #define A2W_PLLH_PIXR 0x1d60 292 #define A2W_PLLH_STSR 0x1e60 293 294 #define A2W_PLLB_ARM 0x13e0 295 #define A2W_PLLB_SP0 0x14e0 296 #define A2W_PLLB_SP1 0x15e0 297 #define A2W_PLLB_SP2 0x16e0 298 299 #define LOCK_TIMEOUT_NS 100000000 300 #define BCM2835_MAX_FB_RATE 1750000000u 301 302 /* 303 * Names of clocks used within the driver that need to be replaced 304 * with an external parent's name. This array is in the order that 305 * the clocks node in the DT references external clocks. 306 */ 307 static const char *const cprman_parent_names[] = { 308 "xosc", 309 "dsi0_byte", 310 "dsi0_ddr2", 311 "dsi0_ddr", 312 "dsi1_byte", 313 "dsi1_ddr2", 314 "dsi1_ddr", 315 }; 316 317 struct bcm2835_cprman { 318 struct device *dev; 319 void __iomem *regs; 320 spinlock_t regs_lock; /* spinlock for all clocks */ 321 322 /* 323 * Real names of cprman clock parents looked up through 324 * of_clk_get_parent_name(), which will be used in the 325 * parent_names[] arrays for clock registration. 326 */ 327 const char *real_parent_names[ARRAY_SIZE(cprman_parent_names)]; 328 329 /* Must be last */ 330 struct clk_hw_onecell_data onecell; 331 }; 332 333 static inline void cprman_write(struct bcm2835_cprman *cprman, u32 reg, u32 val) 334 { 335 writel(CM_PASSWORD | val, cprman->regs + reg); 336 } 337 338 static inline u32 cprman_read(struct bcm2835_cprman *cprman, u32 reg) 339 { 340 return readl(cprman->regs + reg); 341 } 342 343 /* Does a cycle of measuring a clock through the TCNT clock, which may 344 * source from many other clocks in the system. 345 */ 346 static unsigned long bcm2835_measure_tcnt_mux(struct bcm2835_cprman *cprman, 347 u32 tcnt_mux) 348 { 349 u32 osccount = 19200; /* 1ms */ 350 u32 count; 351 ktime_t timeout; 352 353 spin_lock(&cprman->regs_lock); 354 355 cprman_write(cprman, CM_TCNTCTL, CM_KILL); 356 357 cprman_write(cprman, CM_TCNTCTL, 358 (tcnt_mux & CM_SRC_MASK) | 359 (tcnt_mux >> CM_SRC_BITS) << CM_TCNT_SRC1_SHIFT); 360 361 cprman_write(cprman, CM_OSCCOUNT, osccount); 362 363 /* do a kind delay at the start */ 364 mdelay(1); 365 366 /* Finish off whatever is left of OSCCOUNT */ 367 timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS); 368 while (cprman_read(cprman, CM_OSCCOUNT)) { 369 if (ktime_after(ktime_get(), timeout)) { 370 dev_err(cprman->dev, "timeout waiting for OSCCOUNT\n"); 371 count = 0; 372 goto out; 373 } 374 cpu_relax(); 375 } 376 377 /* Wait for BUSY to clear. */ 378 timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS); 379 while (cprman_read(cprman, CM_TCNTCTL) & CM_BUSY) { 380 if (ktime_after(ktime_get(), timeout)) { 381 dev_err(cprman->dev, "timeout waiting for !BUSY\n"); 382 count = 0; 383 goto out; 384 } 385 cpu_relax(); 386 } 387 388 count = cprman_read(cprman, CM_TCNTCNT); 389 390 cprman_write(cprman, CM_TCNTCTL, 0); 391 392 out: 393 spin_unlock(&cprman->regs_lock); 394 395 return count * 1000; 396 } 397 398 static int bcm2835_debugfs_regset(struct bcm2835_cprman *cprman, u32 base, 399 struct debugfs_reg32 *regs, size_t nregs, 400 struct dentry *dentry) 401 { 402 struct dentry *regdump; 403 struct debugfs_regset32 *regset; 404 405 regset = devm_kzalloc(cprman->dev, sizeof(*regset), GFP_KERNEL); 406 if (!regset) 407 return -ENOMEM; 408 409 regset->regs = regs; 410 regset->nregs = nregs; 411 regset->base = cprman->regs + base; 412 413 regdump = debugfs_create_regset32("regdump", S_IRUGO, dentry, 414 regset); 415 416 return regdump ? 0 : -ENOMEM; 417 } 418 419 /* 420 * These are fixed clocks. They're probably not all root clocks and it may 421 * be possible to turn them on and off but until this is mapped out better 422 * it's the only way they can be used. 423 */ 424 void __init bcm2835_init_clocks(void) 425 { 426 struct clk_hw *hw; 427 int ret; 428 429 hw = clk_hw_register_fixed_rate(NULL, "apb_pclk", NULL, 0, 126000000); 430 if (IS_ERR(hw)) 431 pr_err("apb_pclk not registered\n"); 432 433 hw = clk_hw_register_fixed_rate(NULL, "uart0_pclk", NULL, 0, 3000000); 434 if (IS_ERR(hw)) 435 pr_err("uart0_pclk not registered\n"); 436 ret = clk_hw_register_clkdev(hw, NULL, "20201000.uart"); 437 if (ret) 438 pr_err("uart0_pclk alias not registered\n"); 439 440 hw = clk_hw_register_fixed_rate(NULL, "uart1_pclk", NULL, 0, 125000000); 441 if (IS_ERR(hw)) 442 pr_err("uart1_pclk not registered\n"); 443 ret = clk_hw_register_clkdev(hw, NULL, "20215000.uart"); 444 if (ret) 445 pr_err("uart1_pclk alias not registered\n"); 446 } 447 448 struct bcm2835_pll_data { 449 const char *name; 450 u32 cm_ctrl_reg; 451 u32 a2w_ctrl_reg; 452 u32 frac_reg; 453 u32 ana_reg_base; 454 u32 reference_enable_mask; 455 /* Bit in CM_LOCK to indicate when the PLL has locked. */ 456 u32 lock_mask; 457 458 const struct bcm2835_pll_ana_bits *ana; 459 460 unsigned long min_rate; 461 unsigned long max_rate; 462 /* 463 * Highest rate for the VCO before we have to use the 464 * pre-divide-by-2. 465 */ 466 unsigned long max_fb_rate; 467 }; 468 469 struct bcm2835_pll_ana_bits { 470 u32 mask0; 471 u32 set0; 472 u32 mask1; 473 u32 set1; 474 u32 mask3; 475 u32 set3; 476 u32 fb_prediv_mask; 477 }; 478 479 static const struct bcm2835_pll_ana_bits bcm2835_ana_default = { 480 .mask0 = 0, 481 .set0 = 0, 482 .mask1 = (u32)~(A2W_PLL_KI_MASK | A2W_PLL_KP_MASK), 483 .set1 = (2 << A2W_PLL_KI_SHIFT) | (8 << A2W_PLL_KP_SHIFT), 484 .mask3 = (u32)~A2W_PLL_KA_MASK, 485 .set3 = (2 << A2W_PLL_KA_SHIFT), 486 .fb_prediv_mask = BIT(14), 487 }; 488 489 static const struct bcm2835_pll_ana_bits bcm2835_ana_pllh = { 490 .mask0 = (u32)~(A2W_PLLH_KA_MASK | A2W_PLLH_KI_LOW_MASK), 491 .set0 = (2 << A2W_PLLH_KA_SHIFT) | (2 << A2W_PLLH_KI_LOW_SHIFT), 492 .mask1 = (u32)~(A2W_PLLH_KI_HIGH_MASK | A2W_PLLH_KP_MASK), 493 .set1 = (6 << A2W_PLLH_KP_SHIFT), 494 .mask3 = 0, 495 .set3 = 0, 496 .fb_prediv_mask = BIT(11), 497 }; 498 499 struct bcm2835_pll_divider_data { 500 const char *name; 501 const char *source_pll; 502 503 u32 cm_reg; 504 u32 a2w_reg; 505 506 u32 load_mask; 507 u32 hold_mask; 508 u32 fixed_divider; 509 u32 flags; 510 }; 511 512 struct bcm2835_clock_data { 513 const char *name; 514 515 const char *const *parents; 516 int num_mux_parents; 517 518 /* Bitmap encoding which parents accept rate change propagation. */ 519 unsigned int set_rate_parent; 520 521 u32 ctl_reg; 522 u32 div_reg; 523 524 /* Number of integer bits in the divider */ 525 u32 int_bits; 526 /* Number of fractional bits in the divider */ 527 u32 frac_bits; 528 529 u32 flags; 530 531 bool is_vpu_clock; 532 bool is_mash_clock; 533 534 u32 tcnt_mux; 535 }; 536 537 struct bcm2835_gate_data { 538 const char *name; 539 const char *parent; 540 541 u32 ctl_reg; 542 }; 543 544 struct bcm2835_pll { 545 struct clk_hw hw; 546 struct bcm2835_cprman *cprman; 547 const struct bcm2835_pll_data *data; 548 }; 549 550 static int bcm2835_pll_is_on(struct clk_hw *hw) 551 { 552 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); 553 struct bcm2835_cprman *cprman = pll->cprman; 554 const struct bcm2835_pll_data *data = pll->data; 555 556 return cprman_read(cprman, data->a2w_ctrl_reg) & 557 A2W_PLL_CTRL_PRST_DISABLE; 558 } 559 560 static void bcm2835_pll_choose_ndiv_and_fdiv(unsigned long rate, 561 unsigned long parent_rate, 562 u32 *ndiv, u32 *fdiv) 563 { 564 u64 div; 565 566 div = (u64)rate << A2W_PLL_FRAC_BITS; 567 do_div(div, parent_rate); 568 569 *ndiv = div >> A2W_PLL_FRAC_BITS; 570 *fdiv = div & ((1 << A2W_PLL_FRAC_BITS) - 1); 571 } 572 573 static long bcm2835_pll_rate_from_divisors(unsigned long parent_rate, 574 u32 ndiv, u32 fdiv, u32 pdiv) 575 { 576 u64 rate; 577 578 if (pdiv == 0) 579 return 0; 580 581 rate = (u64)parent_rate * ((ndiv << A2W_PLL_FRAC_BITS) + fdiv); 582 do_div(rate, pdiv); 583 return rate >> A2W_PLL_FRAC_BITS; 584 } 585 586 static long bcm2835_pll_round_rate(struct clk_hw *hw, unsigned long rate, 587 unsigned long *parent_rate) 588 { 589 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); 590 const struct bcm2835_pll_data *data = pll->data; 591 u32 ndiv, fdiv; 592 593 rate = clamp(rate, data->min_rate, data->max_rate); 594 595 bcm2835_pll_choose_ndiv_and_fdiv(rate, *parent_rate, &ndiv, &fdiv); 596 597 return bcm2835_pll_rate_from_divisors(*parent_rate, ndiv, fdiv, 1); 598 } 599 600 static unsigned long bcm2835_pll_get_rate(struct clk_hw *hw, 601 unsigned long parent_rate) 602 { 603 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); 604 struct bcm2835_cprman *cprman = pll->cprman; 605 const struct bcm2835_pll_data *data = pll->data; 606 u32 a2wctrl = cprman_read(cprman, data->a2w_ctrl_reg); 607 u32 ndiv, pdiv, fdiv; 608 bool using_prediv; 609 610 if (parent_rate == 0) 611 return 0; 612 613 fdiv = cprman_read(cprman, data->frac_reg) & A2W_PLL_FRAC_MASK; 614 ndiv = (a2wctrl & A2W_PLL_CTRL_NDIV_MASK) >> A2W_PLL_CTRL_NDIV_SHIFT; 615 pdiv = (a2wctrl & A2W_PLL_CTRL_PDIV_MASK) >> A2W_PLL_CTRL_PDIV_SHIFT; 616 using_prediv = cprman_read(cprman, data->ana_reg_base + 4) & 617 data->ana->fb_prediv_mask; 618 619 if (using_prediv) 620 ndiv *= 2; 621 622 return bcm2835_pll_rate_from_divisors(parent_rate, ndiv, fdiv, pdiv); 623 } 624 625 static void bcm2835_pll_off(struct clk_hw *hw) 626 { 627 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); 628 struct bcm2835_cprman *cprman = pll->cprman; 629 const struct bcm2835_pll_data *data = pll->data; 630 631 spin_lock(&cprman->regs_lock); 632 cprman_write(cprman, data->cm_ctrl_reg, 633 cprman_read(cprman, data->cm_ctrl_reg) | 634 CM_PLL_ANARST); 635 cprman_write(cprman, data->a2w_ctrl_reg, 636 cprman_read(cprman, data->a2w_ctrl_reg) | 637 A2W_PLL_CTRL_PWRDN); 638 spin_unlock(&cprman->regs_lock); 639 } 640 641 static int bcm2835_pll_on(struct clk_hw *hw) 642 { 643 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); 644 struct bcm2835_cprman *cprman = pll->cprman; 645 const struct bcm2835_pll_data *data = pll->data; 646 ktime_t timeout; 647 648 cprman_write(cprman, data->a2w_ctrl_reg, 649 cprman_read(cprman, data->a2w_ctrl_reg) & 650 ~A2W_PLL_CTRL_PWRDN); 651 652 /* Take the PLL out of reset. */ 653 cprman_write(cprman, data->cm_ctrl_reg, 654 cprman_read(cprman, data->cm_ctrl_reg) & ~CM_PLL_ANARST); 655 656 /* Wait for the PLL to lock. */ 657 timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS); 658 while (!(cprman_read(cprman, CM_LOCK) & data->lock_mask)) { 659 if (ktime_after(ktime_get(), timeout)) { 660 dev_err(cprman->dev, "%s: couldn't lock PLL\n", 661 clk_hw_get_name(hw)); 662 return -ETIMEDOUT; 663 } 664 665 cpu_relax(); 666 } 667 668 return 0; 669 } 670 671 static void 672 bcm2835_pll_write_ana(struct bcm2835_cprman *cprman, u32 ana_reg_base, u32 *ana) 673 { 674 int i; 675 676 /* 677 * ANA register setup is done as a series of writes to 678 * ANA3-ANA0, in that order. This lets us write all 4 679 * registers as a single cycle of the serdes interface (taking 680 * 100 xosc clocks), whereas if we were to update ana0, 1, and 681 * 3 individually through their partial-write registers, each 682 * would be their own serdes cycle. 683 */ 684 for (i = 3; i >= 0; i--) 685 cprman_write(cprman, ana_reg_base + i * 4, ana[i]); 686 } 687 688 static int bcm2835_pll_set_rate(struct clk_hw *hw, 689 unsigned long rate, unsigned long parent_rate) 690 { 691 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); 692 struct bcm2835_cprman *cprman = pll->cprman; 693 const struct bcm2835_pll_data *data = pll->data; 694 bool was_using_prediv, use_fb_prediv, do_ana_setup_first; 695 u32 ndiv, fdiv, a2w_ctl; 696 u32 ana[4]; 697 int i; 698 699 if (rate > data->max_fb_rate) { 700 use_fb_prediv = true; 701 rate /= 2; 702 } else { 703 use_fb_prediv = false; 704 } 705 706 bcm2835_pll_choose_ndiv_and_fdiv(rate, parent_rate, &ndiv, &fdiv); 707 708 for (i = 3; i >= 0; i--) 709 ana[i] = cprman_read(cprman, data->ana_reg_base + i * 4); 710 711 was_using_prediv = ana[1] & data->ana->fb_prediv_mask; 712 713 ana[0] &= ~data->ana->mask0; 714 ana[0] |= data->ana->set0; 715 ana[1] &= ~data->ana->mask1; 716 ana[1] |= data->ana->set1; 717 ana[3] &= ~data->ana->mask3; 718 ana[3] |= data->ana->set3; 719 720 if (was_using_prediv && !use_fb_prediv) { 721 ana[1] &= ~data->ana->fb_prediv_mask; 722 do_ana_setup_first = true; 723 } else if (!was_using_prediv && use_fb_prediv) { 724 ana[1] |= data->ana->fb_prediv_mask; 725 do_ana_setup_first = false; 726 } else { 727 do_ana_setup_first = true; 728 } 729 730 /* Unmask the reference clock from the oscillator. */ 731 cprman_write(cprman, A2W_XOSC_CTRL, 732 cprman_read(cprman, A2W_XOSC_CTRL) | 733 data->reference_enable_mask); 734 735 if (do_ana_setup_first) 736 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana); 737 738 /* Set the PLL multiplier from the oscillator. */ 739 cprman_write(cprman, data->frac_reg, fdiv); 740 741 a2w_ctl = cprman_read(cprman, data->a2w_ctrl_reg); 742 a2w_ctl &= ~A2W_PLL_CTRL_NDIV_MASK; 743 a2w_ctl |= ndiv << A2W_PLL_CTRL_NDIV_SHIFT; 744 a2w_ctl &= ~A2W_PLL_CTRL_PDIV_MASK; 745 a2w_ctl |= 1 << A2W_PLL_CTRL_PDIV_SHIFT; 746 cprman_write(cprman, data->a2w_ctrl_reg, a2w_ctl); 747 748 if (!do_ana_setup_first) 749 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana); 750 751 return 0; 752 } 753 754 static int bcm2835_pll_debug_init(struct clk_hw *hw, 755 struct dentry *dentry) 756 { 757 struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw); 758 struct bcm2835_cprman *cprman = pll->cprman; 759 const struct bcm2835_pll_data *data = pll->data; 760 struct debugfs_reg32 *regs; 761 762 regs = devm_kzalloc(cprman->dev, 7 * sizeof(*regs), GFP_KERNEL); 763 if (!regs) 764 return -ENOMEM; 765 766 regs[0].name = "cm_ctrl"; 767 regs[0].offset = data->cm_ctrl_reg; 768 regs[1].name = "a2w_ctrl"; 769 regs[1].offset = data->a2w_ctrl_reg; 770 regs[2].name = "frac"; 771 regs[2].offset = data->frac_reg; 772 regs[3].name = "ana0"; 773 regs[3].offset = data->ana_reg_base + 0 * 4; 774 regs[4].name = "ana1"; 775 regs[4].offset = data->ana_reg_base + 1 * 4; 776 regs[5].name = "ana2"; 777 regs[5].offset = data->ana_reg_base + 2 * 4; 778 regs[6].name = "ana3"; 779 regs[6].offset = data->ana_reg_base + 3 * 4; 780 781 return bcm2835_debugfs_regset(cprman, 0, regs, 7, dentry); 782 } 783 784 static const struct clk_ops bcm2835_pll_clk_ops = { 785 .is_prepared = bcm2835_pll_is_on, 786 .prepare = bcm2835_pll_on, 787 .unprepare = bcm2835_pll_off, 788 .recalc_rate = bcm2835_pll_get_rate, 789 .set_rate = bcm2835_pll_set_rate, 790 .round_rate = bcm2835_pll_round_rate, 791 .debug_init = bcm2835_pll_debug_init, 792 }; 793 794 struct bcm2835_pll_divider { 795 struct clk_divider div; 796 struct bcm2835_cprman *cprman; 797 const struct bcm2835_pll_divider_data *data; 798 }; 799 800 static struct bcm2835_pll_divider * 801 bcm2835_pll_divider_from_hw(struct clk_hw *hw) 802 { 803 return container_of(hw, struct bcm2835_pll_divider, div.hw); 804 } 805 806 static int bcm2835_pll_divider_is_on(struct clk_hw *hw) 807 { 808 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); 809 struct bcm2835_cprman *cprman = divider->cprman; 810 const struct bcm2835_pll_divider_data *data = divider->data; 811 812 return !(cprman_read(cprman, data->a2w_reg) & A2W_PLL_CHANNEL_DISABLE); 813 } 814 815 static long bcm2835_pll_divider_round_rate(struct clk_hw *hw, 816 unsigned long rate, 817 unsigned long *parent_rate) 818 { 819 return clk_divider_ops.round_rate(hw, rate, parent_rate); 820 } 821 822 static unsigned long bcm2835_pll_divider_get_rate(struct clk_hw *hw, 823 unsigned long parent_rate) 824 { 825 return clk_divider_ops.recalc_rate(hw, parent_rate); 826 } 827 828 static void bcm2835_pll_divider_off(struct clk_hw *hw) 829 { 830 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); 831 struct bcm2835_cprman *cprman = divider->cprman; 832 const struct bcm2835_pll_divider_data *data = divider->data; 833 834 spin_lock(&cprman->regs_lock); 835 cprman_write(cprman, data->cm_reg, 836 (cprman_read(cprman, data->cm_reg) & 837 ~data->load_mask) | data->hold_mask); 838 cprman_write(cprman, data->a2w_reg, 839 cprman_read(cprman, data->a2w_reg) | 840 A2W_PLL_CHANNEL_DISABLE); 841 spin_unlock(&cprman->regs_lock); 842 } 843 844 static int bcm2835_pll_divider_on(struct clk_hw *hw) 845 { 846 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); 847 struct bcm2835_cprman *cprman = divider->cprman; 848 const struct bcm2835_pll_divider_data *data = divider->data; 849 850 spin_lock(&cprman->regs_lock); 851 cprman_write(cprman, data->a2w_reg, 852 cprman_read(cprman, data->a2w_reg) & 853 ~A2W_PLL_CHANNEL_DISABLE); 854 855 cprman_write(cprman, data->cm_reg, 856 cprman_read(cprman, data->cm_reg) & ~data->hold_mask); 857 spin_unlock(&cprman->regs_lock); 858 859 return 0; 860 } 861 862 static int bcm2835_pll_divider_set_rate(struct clk_hw *hw, 863 unsigned long rate, 864 unsigned long parent_rate) 865 { 866 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); 867 struct bcm2835_cprman *cprman = divider->cprman; 868 const struct bcm2835_pll_divider_data *data = divider->data; 869 u32 cm, div, max_div = 1 << A2W_PLL_DIV_BITS; 870 871 div = DIV_ROUND_UP_ULL(parent_rate, rate); 872 873 div = min(div, max_div); 874 if (div == max_div) 875 div = 0; 876 877 cprman_write(cprman, data->a2w_reg, div); 878 cm = cprman_read(cprman, data->cm_reg); 879 cprman_write(cprman, data->cm_reg, cm | data->load_mask); 880 cprman_write(cprman, data->cm_reg, cm & ~data->load_mask); 881 882 return 0; 883 } 884 885 static int bcm2835_pll_divider_debug_init(struct clk_hw *hw, 886 struct dentry *dentry) 887 { 888 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw); 889 struct bcm2835_cprman *cprman = divider->cprman; 890 const struct bcm2835_pll_divider_data *data = divider->data; 891 struct debugfs_reg32 *regs; 892 893 regs = devm_kzalloc(cprman->dev, 7 * sizeof(*regs), GFP_KERNEL); 894 if (!regs) 895 return -ENOMEM; 896 897 regs[0].name = "cm"; 898 regs[0].offset = data->cm_reg; 899 regs[1].name = "a2w"; 900 regs[1].offset = data->a2w_reg; 901 902 return bcm2835_debugfs_regset(cprman, 0, regs, 2, dentry); 903 } 904 905 static const struct clk_ops bcm2835_pll_divider_clk_ops = { 906 .is_prepared = bcm2835_pll_divider_is_on, 907 .prepare = bcm2835_pll_divider_on, 908 .unprepare = bcm2835_pll_divider_off, 909 .recalc_rate = bcm2835_pll_divider_get_rate, 910 .set_rate = bcm2835_pll_divider_set_rate, 911 .round_rate = bcm2835_pll_divider_round_rate, 912 .debug_init = bcm2835_pll_divider_debug_init, 913 }; 914 915 /* 916 * The CM dividers do fixed-point division, so we can't use the 917 * generic integer divider code like the PLL dividers do (and we can't 918 * fake it by having some fixed shifts preceding it in the clock tree, 919 * because we'd run out of bits in a 32-bit unsigned long). 920 */ 921 struct bcm2835_clock { 922 struct clk_hw hw; 923 struct bcm2835_cprman *cprman; 924 const struct bcm2835_clock_data *data; 925 }; 926 927 static struct bcm2835_clock *bcm2835_clock_from_hw(struct clk_hw *hw) 928 { 929 return container_of(hw, struct bcm2835_clock, hw); 930 } 931 932 static int bcm2835_clock_is_on(struct clk_hw *hw) 933 { 934 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 935 struct bcm2835_cprman *cprman = clock->cprman; 936 const struct bcm2835_clock_data *data = clock->data; 937 938 return (cprman_read(cprman, data->ctl_reg) & CM_ENABLE) != 0; 939 } 940 941 static u32 bcm2835_clock_choose_div(struct clk_hw *hw, 942 unsigned long rate, 943 unsigned long parent_rate, 944 bool round_up) 945 { 946 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 947 const struct bcm2835_clock_data *data = clock->data; 948 u32 unused_frac_mask = 949 GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1; 950 u64 temp = (u64)parent_rate << CM_DIV_FRAC_BITS; 951 u64 rem; 952 u32 div, mindiv, maxdiv; 953 954 rem = do_div(temp, rate); 955 div = temp; 956 957 /* Round up and mask off the unused bits */ 958 if (round_up && ((div & unused_frac_mask) != 0 || rem != 0)) 959 div += unused_frac_mask + 1; 960 div &= ~unused_frac_mask; 961 962 /* different clamping limits apply for a mash clock */ 963 if (data->is_mash_clock) { 964 /* clamp to min divider of 2 */ 965 mindiv = 2 << CM_DIV_FRAC_BITS; 966 /* clamp to the highest possible integer divider */ 967 maxdiv = (BIT(data->int_bits) - 1) << CM_DIV_FRAC_BITS; 968 } else { 969 /* clamp to min divider of 1 */ 970 mindiv = 1 << CM_DIV_FRAC_BITS; 971 /* clamp to the highest possible fractional divider */ 972 maxdiv = GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1, 973 CM_DIV_FRAC_BITS - data->frac_bits); 974 } 975 976 /* apply the clamping limits */ 977 div = max_t(u32, div, mindiv); 978 div = min_t(u32, div, maxdiv); 979 980 return div; 981 } 982 983 static long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock, 984 unsigned long parent_rate, 985 u32 div) 986 { 987 const struct bcm2835_clock_data *data = clock->data; 988 u64 temp; 989 990 if (data->int_bits == 0 && data->frac_bits == 0) 991 return parent_rate; 992 993 /* 994 * The divisor is a 12.12 fixed point field, but only some of 995 * the bits are populated in any given clock. 996 */ 997 div >>= CM_DIV_FRAC_BITS - data->frac_bits; 998 div &= (1 << (data->int_bits + data->frac_bits)) - 1; 999 1000 if (div == 0) 1001 return 0; 1002 1003 temp = (u64)parent_rate << data->frac_bits; 1004 1005 do_div(temp, div); 1006 1007 return temp; 1008 } 1009 1010 static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw, 1011 unsigned long parent_rate) 1012 { 1013 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 1014 struct bcm2835_cprman *cprman = clock->cprman; 1015 const struct bcm2835_clock_data *data = clock->data; 1016 u32 div; 1017 1018 if (data->int_bits == 0 && data->frac_bits == 0) 1019 return parent_rate; 1020 1021 div = cprman_read(cprman, data->div_reg); 1022 1023 return bcm2835_clock_rate_from_divisor(clock, parent_rate, div); 1024 } 1025 1026 static void bcm2835_clock_wait_busy(struct bcm2835_clock *clock) 1027 { 1028 struct bcm2835_cprman *cprman = clock->cprman; 1029 const struct bcm2835_clock_data *data = clock->data; 1030 ktime_t timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS); 1031 1032 while (cprman_read(cprman, data->ctl_reg) & CM_BUSY) { 1033 if (ktime_after(ktime_get(), timeout)) { 1034 dev_err(cprman->dev, "%s: couldn't lock PLL\n", 1035 clk_hw_get_name(&clock->hw)); 1036 return; 1037 } 1038 cpu_relax(); 1039 } 1040 } 1041 1042 static void bcm2835_clock_off(struct clk_hw *hw) 1043 { 1044 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 1045 struct bcm2835_cprman *cprman = clock->cprman; 1046 const struct bcm2835_clock_data *data = clock->data; 1047 1048 spin_lock(&cprman->regs_lock); 1049 cprman_write(cprman, data->ctl_reg, 1050 cprman_read(cprman, data->ctl_reg) & ~CM_ENABLE); 1051 spin_unlock(&cprman->regs_lock); 1052 1053 /* BUSY will remain high until the divider completes its cycle. */ 1054 bcm2835_clock_wait_busy(clock); 1055 } 1056 1057 static int bcm2835_clock_on(struct clk_hw *hw) 1058 { 1059 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 1060 struct bcm2835_cprman *cprman = clock->cprman; 1061 const struct bcm2835_clock_data *data = clock->data; 1062 1063 spin_lock(&cprman->regs_lock); 1064 cprman_write(cprman, data->ctl_reg, 1065 cprman_read(cprman, data->ctl_reg) | 1066 CM_ENABLE | 1067 CM_GATE); 1068 spin_unlock(&cprman->regs_lock); 1069 1070 /* Debug code to measure the clock once it's turned on to see 1071 * if it's ticking at the rate we expect. 1072 */ 1073 if (data->tcnt_mux && false) { 1074 dev_info(cprman->dev, 1075 "clk %s: rate %ld, measure %ld\n", 1076 data->name, 1077 clk_hw_get_rate(hw), 1078 bcm2835_measure_tcnt_mux(cprman, data->tcnt_mux)); 1079 } 1080 1081 return 0; 1082 } 1083 1084 static int bcm2835_clock_set_rate(struct clk_hw *hw, 1085 unsigned long rate, unsigned long parent_rate) 1086 { 1087 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 1088 struct bcm2835_cprman *cprman = clock->cprman; 1089 const struct bcm2835_clock_data *data = clock->data; 1090 u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate, false); 1091 u32 ctl; 1092 1093 spin_lock(&cprman->regs_lock); 1094 1095 /* 1096 * Setting up frac support 1097 * 1098 * In principle it is recommended to stop/start the clock first, 1099 * but as we set CLK_SET_RATE_GATE during registration of the 1100 * clock this requirement should be take care of by the 1101 * clk-framework. 1102 */ 1103 ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC; 1104 ctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0; 1105 cprman_write(cprman, data->ctl_reg, ctl); 1106 1107 cprman_write(cprman, data->div_reg, div); 1108 1109 spin_unlock(&cprman->regs_lock); 1110 1111 return 0; 1112 } 1113 1114 static bool 1115 bcm2835_clk_is_pllc(struct clk_hw *hw) 1116 { 1117 if (!hw) 1118 return false; 1119 1120 return strncmp(clk_hw_get_name(hw), "pllc", 4) == 0; 1121 } 1122 1123 static unsigned long bcm2835_clock_choose_div_and_prate(struct clk_hw *hw, 1124 int parent_idx, 1125 unsigned long rate, 1126 u32 *div, 1127 unsigned long *prate) 1128 { 1129 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 1130 struct bcm2835_cprman *cprman = clock->cprman; 1131 const struct bcm2835_clock_data *data = clock->data; 1132 unsigned long best_rate = 0; 1133 u32 curdiv, mindiv, maxdiv; 1134 struct clk_hw *parent; 1135 1136 parent = clk_hw_get_parent_by_index(hw, parent_idx); 1137 1138 if (!(BIT(parent_idx) & data->set_rate_parent)) { 1139 *prate = clk_hw_get_rate(parent); 1140 *div = bcm2835_clock_choose_div(hw, rate, *prate, true); 1141 1142 return bcm2835_clock_rate_from_divisor(clock, *prate, 1143 *div); 1144 } 1145 1146 if (data->frac_bits) 1147 dev_warn(cprman->dev, 1148 "frac bits are not used when propagating rate change"); 1149 1150 /* clamp to min divider of 2 if we're dealing with a mash clock */ 1151 mindiv = data->is_mash_clock ? 2 : 1; 1152 maxdiv = BIT(data->int_bits) - 1; 1153 1154 /* TODO: Be smart, and only test a subset of the available divisors. */ 1155 for (curdiv = mindiv; curdiv <= maxdiv; curdiv++) { 1156 unsigned long tmp_rate; 1157 1158 tmp_rate = clk_hw_round_rate(parent, rate * curdiv); 1159 tmp_rate /= curdiv; 1160 if (curdiv == mindiv || 1161 (tmp_rate > best_rate && tmp_rate <= rate)) 1162 best_rate = tmp_rate; 1163 1164 if (best_rate == rate) 1165 break; 1166 } 1167 1168 *div = curdiv << CM_DIV_FRAC_BITS; 1169 *prate = curdiv * best_rate; 1170 1171 return best_rate; 1172 } 1173 1174 static int bcm2835_clock_determine_rate(struct clk_hw *hw, 1175 struct clk_rate_request *req) 1176 { 1177 struct clk_hw *parent, *best_parent = NULL; 1178 bool current_parent_is_pllc; 1179 unsigned long rate, best_rate = 0; 1180 unsigned long prate, best_prate = 0; 1181 size_t i; 1182 u32 div; 1183 1184 current_parent_is_pllc = bcm2835_clk_is_pllc(clk_hw_get_parent(hw)); 1185 1186 /* 1187 * Select parent clock that results in the closest but lower rate 1188 */ 1189 for (i = 0; i < clk_hw_get_num_parents(hw); ++i) { 1190 parent = clk_hw_get_parent_by_index(hw, i); 1191 if (!parent) 1192 continue; 1193 1194 /* 1195 * Don't choose a PLLC-derived clock as our parent 1196 * unless it had been manually set that way. PLLC's 1197 * frequency gets adjusted by the firmware due to 1198 * over-temp or under-voltage conditions, without 1199 * prior notification to our clock consumer. 1200 */ 1201 if (bcm2835_clk_is_pllc(parent) && !current_parent_is_pllc) 1202 continue; 1203 1204 rate = bcm2835_clock_choose_div_and_prate(hw, i, req->rate, 1205 &div, &prate); 1206 if (rate > best_rate && rate <= req->rate) { 1207 best_parent = parent; 1208 best_prate = prate; 1209 best_rate = rate; 1210 } 1211 } 1212 1213 if (!best_parent) 1214 return -EINVAL; 1215 1216 req->best_parent_hw = best_parent; 1217 req->best_parent_rate = best_prate; 1218 1219 req->rate = best_rate; 1220 1221 return 0; 1222 } 1223 1224 static int bcm2835_clock_set_parent(struct clk_hw *hw, u8 index) 1225 { 1226 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 1227 struct bcm2835_cprman *cprman = clock->cprman; 1228 const struct bcm2835_clock_data *data = clock->data; 1229 u8 src = (index << CM_SRC_SHIFT) & CM_SRC_MASK; 1230 1231 cprman_write(cprman, data->ctl_reg, src); 1232 return 0; 1233 } 1234 1235 static u8 bcm2835_clock_get_parent(struct clk_hw *hw) 1236 { 1237 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 1238 struct bcm2835_cprman *cprman = clock->cprman; 1239 const struct bcm2835_clock_data *data = clock->data; 1240 u32 src = cprman_read(cprman, data->ctl_reg); 1241 1242 return (src & CM_SRC_MASK) >> CM_SRC_SHIFT; 1243 } 1244 1245 static struct debugfs_reg32 bcm2835_debugfs_clock_reg32[] = { 1246 { 1247 .name = "ctl", 1248 .offset = 0, 1249 }, 1250 { 1251 .name = "div", 1252 .offset = 4, 1253 }, 1254 }; 1255 1256 static int bcm2835_clock_debug_init(struct clk_hw *hw, 1257 struct dentry *dentry) 1258 { 1259 struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); 1260 struct bcm2835_cprman *cprman = clock->cprman; 1261 const struct bcm2835_clock_data *data = clock->data; 1262 1263 return bcm2835_debugfs_regset( 1264 cprman, data->ctl_reg, 1265 bcm2835_debugfs_clock_reg32, 1266 ARRAY_SIZE(bcm2835_debugfs_clock_reg32), 1267 dentry); 1268 } 1269 1270 static const struct clk_ops bcm2835_clock_clk_ops = { 1271 .is_prepared = bcm2835_clock_is_on, 1272 .prepare = bcm2835_clock_on, 1273 .unprepare = bcm2835_clock_off, 1274 .recalc_rate = bcm2835_clock_get_rate, 1275 .set_rate = bcm2835_clock_set_rate, 1276 .determine_rate = bcm2835_clock_determine_rate, 1277 .set_parent = bcm2835_clock_set_parent, 1278 .get_parent = bcm2835_clock_get_parent, 1279 .debug_init = bcm2835_clock_debug_init, 1280 }; 1281 1282 static int bcm2835_vpu_clock_is_on(struct clk_hw *hw) 1283 { 1284 return true; 1285 } 1286 1287 /* 1288 * The VPU clock can never be disabled (it doesn't have an ENABLE 1289 * bit), so it gets its own set of clock ops. 1290 */ 1291 static const struct clk_ops bcm2835_vpu_clock_clk_ops = { 1292 .is_prepared = bcm2835_vpu_clock_is_on, 1293 .recalc_rate = bcm2835_clock_get_rate, 1294 .set_rate = bcm2835_clock_set_rate, 1295 .determine_rate = bcm2835_clock_determine_rate, 1296 .set_parent = bcm2835_clock_set_parent, 1297 .get_parent = bcm2835_clock_get_parent, 1298 .debug_init = bcm2835_clock_debug_init, 1299 }; 1300 1301 static struct clk_hw *bcm2835_register_pll(struct bcm2835_cprman *cprman, 1302 const struct bcm2835_pll_data *data) 1303 { 1304 struct bcm2835_pll *pll; 1305 struct clk_init_data init; 1306 int ret; 1307 1308 memset(&init, 0, sizeof(init)); 1309 1310 /* All of the PLLs derive from the external oscillator. */ 1311 init.parent_names = &cprman->real_parent_names[0]; 1312 init.num_parents = 1; 1313 init.name = data->name; 1314 init.ops = &bcm2835_pll_clk_ops; 1315 init.flags = CLK_IGNORE_UNUSED; 1316 1317 pll = kzalloc(sizeof(*pll), GFP_KERNEL); 1318 if (!pll) 1319 return NULL; 1320 1321 pll->cprman = cprman; 1322 pll->data = data; 1323 pll->hw.init = &init; 1324 1325 ret = devm_clk_hw_register(cprman->dev, &pll->hw); 1326 if (ret) 1327 return NULL; 1328 return &pll->hw; 1329 } 1330 1331 static struct clk_hw * 1332 bcm2835_register_pll_divider(struct bcm2835_cprman *cprman, 1333 const struct bcm2835_pll_divider_data *data) 1334 { 1335 struct bcm2835_pll_divider *divider; 1336 struct clk_init_data init; 1337 const char *divider_name; 1338 int ret; 1339 1340 if (data->fixed_divider != 1) { 1341 divider_name = devm_kasprintf(cprman->dev, GFP_KERNEL, 1342 "%s_prediv", data->name); 1343 if (!divider_name) 1344 return NULL; 1345 } else { 1346 divider_name = data->name; 1347 } 1348 1349 memset(&init, 0, sizeof(init)); 1350 1351 init.parent_names = &data->source_pll; 1352 init.num_parents = 1; 1353 init.name = divider_name; 1354 init.ops = &bcm2835_pll_divider_clk_ops; 1355 init.flags = data->flags | CLK_IGNORE_UNUSED; 1356 1357 divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL); 1358 if (!divider) 1359 return NULL; 1360 1361 divider->div.reg = cprman->regs + data->a2w_reg; 1362 divider->div.shift = A2W_PLL_DIV_SHIFT; 1363 divider->div.width = A2W_PLL_DIV_BITS; 1364 divider->div.flags = CLK_DIVIDER_MAX_AT_ZERO; 1365 divider->div.lock = &cprman->regs_lock; 1366 divider->div.hw.init = &init; 1367 divider->div.table = NULL; 1368 1369 divider->cprman = cprman; 1370 divider->data = data; 1371 1372 ret = devm_clk_hw_register(cprman->dev, ÷r->div.hw); 1373 if (ret) 1374 return ERR_PTR(ret); 1375 1376 /* 1377 * PLLH's channels have a fixed divide by 10 afterwards, which 1378 * is what our consumers are actually using. 1379 */ 1380 if (data->fixed_divider != 1) { 1381 return clk_hw_register_fixed_factor(cprman->dev, data->name, 1382 divider_name, 1383 CLK_SET_RATE_PARENT, 1384 1, 1385 data->fixed_divider); 1386 } 1387 1388 return ÷r->div.hw; 1389 } 1390 1391 static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman, 1392 const struct bcm2835_clock_data *data) 1393 { 1394 struct bcm2835_clock *clock; 1395 struct clk_init_data init; 1396 const char *parents[1 << CM_SRC_BITS]; 1397 size_t i, j; 1398 int ret; 1399 1400 /* 1401 * Replace our strings referencing parent clocks with the 1402 * actual clock-output-name of the parent. 1403 */ 1404 for (i = 0; i < data->num_mux_parents; i++) { 1405 parents[i] = data->parents[i]; 1406 1407 for (j = 0; j < ARRAY_SIZE(cprman_parent_names); j++) { 1408 if (strcmp(parents[i], cprman_parent_names[j]) == 0) { 1409 parents[i] = cprman->real_parent_names[j]; 1410 break; 1411 } 1412 } 1413 } 1414 1415 memset(&init, 0, sizeof(init)); 1416 init.parent_names = parents; 1417 init.num_parents = data->num_mux_parents; 1418 init.name = data->name; 1419 init.flags = data->flags | CLK_IGNORE_UNUSED; 1420 1421 /* 1422 * Pass the CLK_SET_RATE_PARENT flag if we are allowed to propagate 1423 * rate changes on at least of the parents. 1424 */ 1425 if (data->set_rate_parent) 1426 init.flags |= CLK_SET_RATE_PARENT; 1427 1428 if (data->is_vpu_clock) { 1429 init.ops = &bcm2835_vpu_clock_clk_ops; 1430 } else { 1431 init.ops = &bcm2835_clock_clk_ops; 1432 init.flags |= CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; 1433 1434 /* If the clock wasn't actually enabled at boot, it's not 1435 * critical. 1436 */ 1437 if (!(cprman_read(cprman, data->ctl_reg) & CM_ENABLE)) 1438 init.flags &= ~CLK_IS_CRITICAL; 1439 } 1440 1441 clock = devm_kzalloc(cprman->dev, sizeof(*clock), GFP_KERNEL); 1442 if (!clock) 1443 return NULL; 1444 1445 clock->cprman = cprman; 1446 clock->data = data; 1447 clock->hw.init = &init; 1448 1449 ret = devm_clk_hw_register(cprman->dev, &clock->hw); 1450 if (ret) 1451 return ERR_PTR(ret); 1452 return &clock->hw; 1453 } 1454 1455 static struct clk *bcm2835_register_gate(struct bcm2835_cprman *cprman, 1456 const struct bcm2835_gate_data *data) 1457 { 1458 return clk_register_gate(cprman->dev, data->name, data->parent, 1459 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE, 1460 cprman->regs + data->ctl_reg, 1461 CM_GATE_BIT, 0, &cprman->regs_lock); 1462 } 1463 1464 typedef struct clk_hw *(*bcm2835_clk_register)(struct bcm2835_cprman *cprman, 1465 const void *data); 1466 struct bcm2835_clk_desc { 1467 bcm2835_clk_register clk_register; 1468 const void *data; 1469 }; 1470 1471 /* assignment helper macros for different clock types */ 1472 #define _REGISTER(f, ...) { .clk_register = (bcm2835_clk_register)f, \ 1473 .data = __VA_ARGS__ } 1474 #define REGISTER_PLL(...) _REGISTER(&bcm2835_register_pll, \ 1475 &(struct bcm2835_pll_data) \ 1476 {__VA_ARGS__}) 1477 #define REGISTER_PLL_DIV(...) _REGISTER(&bcm2835_register_pll_divider, \ 1478 &(struct bcm2835_pll_divider_data) \ 1479 {__VA_ARGS__}) 1480 #define REGISTER_CLK(...) _REGISTER(&bcm2835_register_clock, \ 1481 &(struct bcm2835_clock_data) \ 1482 {__VA_ARGS__}) 1483 #define REGISTER_GATE(...) _REGISTER(&bcm2835_register_gate, \ 1484 &(struct bcm2835_gate_data) \ 1485 {__VA_ARGS__}) 1486 1487 /* parent mux arrays plus helper macros */ 1488 1489 /* main oscillator parent mux */ 1490 static const char *const bcm2835_clock_osc_parents[] = { 1491 "gnd", 1492 "xosc", 1493 "testdebug0", 1494 "testdebug1" 1495 }; 1496 1497 #define REGISTER_OSC_CLK(...) REGISTER_CLK( \ 1498 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents), \ 1499 .parents = bcm2835_clock_osc_parents, \ 1500 __VA_ARGS__) 1501 1502 /* main peripherial parent mux */ 1503 static const char *const bcm2835_clock_per_parents[] = { 1504 "gnd", 1505 "xosc", 1506 "testdebug0", 1507 "testdebug1", 1508 "plla_per", 1509 "pllc_per", 1510 "plld_per", 1511 "pllh_aux", 1512 }; 1513 1514 #define REGISTER_PER_CLK(...) REGISTER_CLK( \ 1515 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), \ 1516 .parents = bcm2835_clock_per_parents, \ 1517 __VA_ARGS__) 1518 1519 /* main vpu parent mux */ 1520 static const char *const bcm2835_clock_vpu_parents[] = { 1521 "gnd", 1522 "xosc", 1523 "testdebug0", 1524 "testdebug1", 1525 "plla_core", 1526 "pllc_core0", 1527 "plld_core", 1528 "pllh_aux", 1529 "pllc_core1", 1530 "pllc_core2", 1531 }; 1532 1533 #define REGISTER_VPU_CLK(...) REGISTER_CLK( \ 1534 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), \ 1535 .parents = bcm2835_clock_vpu_parents, \ 1536 __VA_ARGS__) 1537 1538 /* 1539 * DSI parent clocks. The DSI byte/DDR/DDR2 clocks come from the DSI 1540 * analog PHY. The _inv variants are generated internally to cprman, 1541 * but we don't use them so they aren't hooked up. 1542 */ 1543 static const char *const bcm2835_clock_dsi0_parents[] = { 1544 "gnd", 1545 "xosc", 1546 "testdebug0", 1547 "testdebug1", 1548 "dsi0_ddr", 1549 "dsi0_ddr_inv", 1550 "dsi0_ddr2", 1551 "dsi0_ddr2_inv", 1552 "dsi0_byte", 1553 "dsi0_byte_inv", 1554 }; 1555 1556 static const char *const bcm2835_clock_dsi1_parents[] = { 1557 "gnd", 1558 "xosc", 1559 "testdebug0", 1560 "testdebug1", 1561 "dsi1_ddr", 1562 "dsi1_ddr_inv", 1563 "dsi1_ddr2", 1564 "dsi1_ddr2_inv", 1565 "dsi1_byte", 1566 "dsi1_byte_inv", 1567 }; 1568 1569 #define REGISTER_DSI0_CLK(...) REGISTER_CLK( \ 1570 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi0_parents), \ 1571 .parents = bcm2835_clock_dsi0_parents, \ 1572 __VA_ARGS__) 1573 1574 #define REGISTER_DSI1_CLK(...) REGISTER_CLK( \ 1575 .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi1_parents), \ 1576 .parents = bcm2835_clock_dsi1_parents, \ 1577 __VA_ARGS__) 1578 1579 /* 1580 * the real definition of all the pll, pll_dividers and clocks 1581 * these make use of the above REGISTER_* macros 1582 */ 1583 static const struct bcm2835_clk_desc clk_desc_array[] = { 1584 /* the PLL + PLL dividers */ 1585 1586 /* 1587 * PLLA is the auxiliary PLL, used to drive the CCP2 1588 * (Compact Camera Port 2) transmitter clock. 1589 * 1590 * It is in the PX LDO power domain, which is on when the 1591 * AUDIO domain is on. 1592 */ 1593 [BCM2835_PLLA] = REGISTER_PLL( 1594 .name = "plla", 1595 .cm_ctrl_reg = CM_PLLA, 1596 .a2w_ctrl_reg = A2W_PLLA_CTRL, 1597 .frac_reg = A2W_PLLA_FRAC, 1598 .ana_reg_base = A2W_PLLA_ANA0, 1599 .reference_enable_mask = A2W_XOSC_CTRL_PLLA_ENABLE, 1600 .lock_mask = CM_LOCK_FLOCKA, 1601 1602 .ana = &bcm2835_ana_default, 1603 1604 .min_rate = 600000000u, 1605 .max_rate = 2400000000u, 1606 .max_fb_rate = BCM2835_MAX_FB_RATE), 1607 [BCM2835_PLLA_CORE] = REGISTER_PLL_DIV( 1608 .name = "plla_core", 1609 .source_pll = "plla", 1610 .cm_reg = CM_PLLA, 1611 .a2w_reg = A2W_PLLA_CORE, 1612 .load_mask = CM_PLLA_LOADCORE, 1613 .hold_mask = CM_PLLA_HOLDCORE, 1614 .fixed_divider = 1, 1615 .flags = CLK_SET_RATE_PARENT), 1616 [BCM2835_PLLA_PER] = REGISTER_PLL_DIV( 1617 .name = "plla_per", 1618 .source_pll = "plla", 1619 .cm_reg = CM_PLLA, 1620 .a2w_reg = A2W_PLLA_PER, 1621 .load_mask = CM_PLLA_LOADPER, 1622 .hold_mask = CM_PLLA_HOLDPER, 1623 .fixed_divider = 1, 1624 .flags = CLK_SET_RATE_PARENT), 1625 [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV( 1626 .name = "plla_dsi0", 1627 .source_pll = "plla", 1628 .cm_reg = CM_PLLA, 1629 .a2w_reg = A2W_PLLA_DSI0, 1630 .load_mask = CM_PLLA_LOADDSI0, 1631 .hold_mask = CM_PLLA_HOLDDSI0, 1632 .fixed_divider = 1), 1633 [BCM2835_PLLA_CCP2] = REGISTER_PLL_DIV( 1634 .name = "plla_ccp2", 1635 .source_pll = "plla", 1636 .cm_reg = CM_PLLA, 1637 .a2w_reg = A2W_PLLA_CCP2, 1638 .load_mask = CM_PLLA_LOADCCP2, 1639 .hold_mask = CM_PLLA_HOLDCCP2, 1640 .fixed_divider = 1, 1641 .flags = CLK_SET_RATE_PARENT), 1642 1643 /* PLLB is used for the ARM's clock. */ 1644 [BCM2835_PLLB] = REGISTER_PLL( 1645 .name = "pllb", 1646 .cm_ctrl_reg = CM_PLLB, 1647 .a2w_ctrl_reg = A2W_PLLB_CTRL, 1648 .frac_reg = A2W_PLLB_FRAC, 1649 .ana_reg_base = A2W_PLLB_ANA0, 1650 .reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE, 1651 .lock_mask = CM_LOCK_FLOCKB, 1652 1653 .ana = &bcm2835_ana_default, 1654 1655 .min_rate = 600000000u, 1656 .max_rate = 3000000000u, 1657 .max_fb_rate = BCM2835_MAX_FB_RATE), 1658 [BCM2835_PLLB_ARM] = REGISTER_PLL_DIV( 1659 .name = "pllb_arm", 1660 .source_pll = "pllb", 1661 .cm_reg = CM_PLLB, 1662 .a2w_reg = A2W_PLLB_ARM, 1663 .load_mask = CM_PLLB_LOADARM, 1664 .hold_mask = CM_PLLB_HOLDARM, 1665 .fixed_divider = 1, 1666 .flags = CLK_SET_RATE_PARENT), 1667 1668 /* 1669 * PLLC is the core PLL, used to drive the core VPU clock. 1670 * 1671 * It is in the PX LDO power domain, which is on when the 1672 * AUDIO domain is on. 1673 */ 1674 [BCM2835_PLLC] = REGISTER_PLL( 1675 .name = "pllc", 1676 .cm_ctrl_reg = CM_PLLC, 1677 .a2w_ctrl_reg = A2W_PLLC_CTRL, 1678 .frac_reg = A2W_PLLC_FRAC, 1679 .ana_reg_base = A2W_PLLC_ANA0, 1680 .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE, 1681 .lock_mask = CM_LOCK_FLOCKC, 1682 1683 .ana = &bcm2835_ana_default, 1684 1685 .min_rate = 600000000u, 1686 .max_rate = 3000000000u, 1687 .max_fb_rate = BCM2835_MAX_FB_RATE), 1688 [BCM2835_PLLC_CORE0] = REGISTER_PLL_DIV( 1689 .name = "pllc_core0", 1690 .source_pll = "pllc", 1691 .cm_reg = CM_PLLC, 1692 .a2w_reg = A2W_PLLC_CORE0, 1693 .load_mask = CM_PLLC_LOADCORE0, 1694 .hold_mask = CM_PLLC_HOLDCORE0, 1695 .fixed_divider = 1, 1696 .flags = CLK_SET_RATE_PARENT), 1697 [BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV( 1698 .name = "pllc_core1", 1699 .source_pll = "pllc", 1700 .cm_reg = CM_PLLC, 1701 .a2w_reg = A2W_PLLC_CORE1, 1702 .load_mask = CM_PLLC_LOADCORE1, 1703 .hold_mask = CM_PLLC_HOLDCORE1, 1704 .fixed_divider = 1, 1705 .flags = CLK_SET_RATE_PARENT), 1706 [BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV( 1707 .name = "pllc_core2", 1708 .source_pll = "pllc", 1709 .cm_reg = CM_PLLC, 1710 .a2w_reg = A2W_PLLC_CORE2, 1711 .load_mask = CM_PLLC_LOADCORE2, 1712 .hold_mask = CM_PLLC_HOLDCORE2, 1713 .fixed_divider = 1, 1714 .flags = CLK_SET_RATE_PARENT), 1715 [BCM2835_PLLC_PER] = REGISTER_PLL_DIV( 1716 .name = "pllc_per", 1717 .source_pll = "pllc", 1718 .cm_reg = CM_PLLC, 1719 .a2w_reg = A2W_PLLC_PER, 1720 .load_mask = CM_PLLC_LOADPER, 1721 .hold_mask = CM_PLLC_HOLDPER, 1722 .fixed_divider = 1, 1723 .flags = CLK_SET_RATE_PARENT), 1724 1725 /* 1726 * PLLD is the display PLL, used to drive DSI display panels. 1727 * 1728 * It is in the PX LDO power domain, which is on when the 1729 * AUDIO domain is on. 1730 */ 1731 [BCM2835_PLLD] = REGISTER_PLL( 1732 .name = "plld", 1733 .cm_ctrl_reg = CM_PLLD, 1734 .a2w_ctrl_reg = A2W_PLLD_CTRL, 1735 .frac_reg = A2W_PLLD_FRAC, 1736 .ana_reg_base = A2W_PLLD_ANA0, 1737 .reference_enable_mask = A2W_XOSC_CTRL_DDR_ENABLE, 1738 .lock_mask = CM_LOCK_FLOCKD, 1739 1740 .ana = &bcm2835_ana_default, 1741 1742 .min_rate = 600000000u, 1743 .max_rate = 2400000000u, 1744 .max_fb_rate = BCM2835_MAX_FB_RATE), 1745 [BCM2835_PLLD_CORE] = REGISTER_PLL_DIV( 1746 .name = "plld_core", 1747 .source_pll = "plld", 1748 .cm_reg = CM_PLLD, 1749 .a2w_reg = A2W_PLLD_CORE, 1750 .load_mask = CM_PLLD_LOADCORE, 1751 .hold_mask = CM_PLLD_HOLDCORE, 1752 .fixed_divider = 1, 1753 .flags = CLK_SET_RATE_PARENT), 1754 [BCM2835_PLLD_PER] = REGISTER_PLL_DIV( 1755 .name = "plld_per", 1756 .source_pll = "plld", 1757 .cm_reg = CM_PLLD, 1758 .a2w_reg = A2W_PLLD_PER, 1759 .load_mask = CM_PLLD_LOADPER, 1760 .hold_mask = CM_PLLD_HOLDPER, 1761 .fixed_divider = 1, 1762 .flags = CLK_SET_RATE_PARENT), 1763 [BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV( 1764 .name = "plld_dsi0", 1765 .source_pll = "plld", 1766 .cm_reg = CM_PLLD, 1767 .a2w_reg = A2W_PLLD_DSI0, 1768 .load_mask = CM_PLLD_LOADDSI0, 1769 .hold_mask = CM_PLLD_HOLDDSI0, 1770 .fixed_divider = 1), 1771 [BCM2835_PLLD_DSI1] = REGISTER_PLL_DIV( 1772 .name = "plld_dsi1", 1773 .source_pll = "plld", 1774 .cm_reg = CM_PLLD, 1775 .a2w_reg = A2W_PLLD_DSI1, 1776 .load_mask = CM_PLLD_LOADDSI1, 1777 .hold_mask = CM_PLLD_HOLDDSI1, 1778 .fixed_divider = 1), 1779 1780 /* 1781 * PLLH is used to supply the pixel clock or the AUX clock for the 1782 * TV encoder. 1783 * 1784 * It is in the HDMI power domain. 1785 */ 1786 [BCM2835_PLLH] = REGISTER_PLL( 1787 "pllh", 1788 .cm_ctrl_reg = CM_PLLH, 1789 .a2w_ctrl_reg = A2W_PLLH_CTRL, 1790 .frac_reg = A2W_PLLH_FRAC, 1791 .ana_reg_base = A2W_PLLH_ANA0, 1792 .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE, 1793 .lock_mask = CM_LOCK_FLOCKH, 1794 1795 .ana = &bcm2835_ana_pllh, 1796 1797 .min_rate = 600000000u, 1798 .max_rate = 3000000000u, 1799 .max_fb_rate = BCM2835_MAX_FB_RATE), 1800 [BCM2835_PLLH_RCAL] = REGISTER_PLL_DIV( 1801 .name = "pllh_rcal", 1802 .source_pll = "pllh", 1803 .cm_reg = CM_PLLH, 1804 .a2w_reg = A2W_PLLH_RCAL, 1805 .load_mask = CM_PLLH_LOADRCAL, 1806 .hold_mask = 0, 1807 .fixed_divider = 10, 1808 .flags = CLK_SET_RATE_PARENT), 1809 [BCM2835_PLLH_AUX] = REGISTER_PLL_DIV( 1810 .name = "pllh_aux", 1811 .source_pll = "pllh", 1812 .cm_reg = CM_PLLH, 1813 .a2w_reg = A2W_PLLH_AUX, 1814 .load_mask = CM_PLLH_LOADAUX, 1815 .hold_mask = 0, 1816 .fixed_divider = 1, 1817 .flags = CLK_SET_RATE_PARENT), 1818 [BCM2835_PLLH_PIX] = REGISTER_PLL_DIV( 1819 .name = "pllh_pix", 1820 .source_pll = "pllh", 1821 .cm_reg = CM_PLLH, 1822 .a2w_reg = A2W_PLLH_PIX, 1823 .load_mask = CM_PLLH_LOADPIX, 1824 .hold_mask = 0, 1825 .fixed_divider = 10, 1826 .flags = CLK_SET_RATE_PARENT), 1827 1828 /* the clocks */ 1829 1830 /* clocks with oscillator parent mux */ 1831 1832 /* One Time Programmable Memory clock. Maximum 10Mhz. */ 1833 [BCM2835_CLOCK_OTP] = REGISTER_OSC_CLK( 1834 .name = "otp", 1835 .ctl_reg = CM_OTPCTL, 1836 .div_reg = CM_OTPDIV, 1837 .int_bits = 4, 1838 .frac_bits = 0, 1839 .tcnt_mux = 6), 1840 /* 1841 * Used for a 1Mhz clock for the system clocksource, and also used 1842 * bythe watchdog timer and the camera pulse generator. 1843 */ 1844 [BCM2835_CLOCK_TIMER] = REGISTER_OSC_CLK( 1845 .name = "timer", 1846 .ctl_reg = CM_TIMERCTL, 1847 .div_reg = CM_TIMERDIV, 1848 .int_bits = 6, 1849 .frac_bits = 12), 1850 /* 1851 * Clock for the temperature sensor. 1852 * Generally run at 2Mhz, max 5Mhz. 1853 */ 1854 [BCM2835_CLOCK_TSENS] = REGISTER_OSC_CLK( 1855 .name = "tsens", 1856 .ctl_reg = CM_TSENSCTL, 1857 .div_reg = CM_TSENSDIV, 1858 .int_bits = 5, 1859 .frac_bits = 0), 1860 [BCM2835_CLOCK_TEC] = REGISTER_OSC_CLK( 1861 .name = "tec", 1862 .ctl_reg = CM_TECCTL, 1863 .div_reg = CM_TECDIV, 1864 .int_bits = 6, 1865 .frac_bits = 0), 1866 1867 /* clocks with vpu parent mux */ 1868 [BCM2835_CLOCK_H264] = REGISTER_VPU_CLK( 1869 .name = "h264", 1870 .ctl_reg = CM_H264CTL, 1871 .div_reg = CM_H264DIV, 1872 .int_bits = 4, 1873 .frac_bits = 8, 1874 .tcnt_mux = 1), 1875 [BCM2835_CLOCK_ISP] = REGISTER_VPU_CLK( 1876 .name = "isp", 1877 .ctl_reg = CM_ISPCTL, 1878 .div_reg = CM_ISPDIV, 1879 .int_bits = 4, 1880 .frac_bits = 8, 1881 .tcnt_mux = 2), 1882 1883 /* 1884 * Secondary SDRAM clock. Used for low-voltage modes when the PLL 1885 * in the SDRAM controller can't be used. 1886 */ 1887 [BCM2835_CLOCK_SDRAM] = REGISTER_VPU_CLK( 1888 .name = "sdram", 1889 .ctl_reg = CM_SDCCTL, 1890 .div_reg = CM_SDCDIV, 1891 .int_bits = 6, 1892 .frac_bits = 0, 1893 .tcnt_mux = 3), 1894 [BCM2835_CLOCK_V3D] = REGISTER_VPU_CLK( 1895 .name = "v3d", 1896 .ctl_reg = CM_V3DCTL, 1897 .div_reg = CM_V3DDIV, 1898 .int_bits = 4, 1899 .frac_bits = 8, 1900 .tcnt_mux = 4), 1901 /* 1902 * VPU clock. This doesn't have an enable bit, since it drives 1903 * the bus for everything else, and is special so it doesn't need 1904 * to be gated for rate changes. It is also known as "clk_audio" 1905 * in various hardware documentation. 1906 */ 1907 [BCM2835_CLOCK_VPU] = REGISTER_VPU_CLK( 1908 .name = "vpu", 1909 .ctl_reg = CM_VPUCTL, 1910 .div_reg = CM_VPUDIV, 1911 .int_bits = 12, 1912 .frac_bits = 8, 1913 .flags = CLK_IS_CRITICAL, 1914 .is_vpu_clock = true, 1915 .tcnt_mux = 5), 1916 1917 /* clocks with per parent mux */ 1918 [BCM2835_CLOCK_AVEO] = REGISTER_PER_CLK( 1919 .name = "aveo", 1920 .ctl_reg = CM_AVEOCTL, 1921 .div_reg = CM_AVEODIV, 1922 .int_bits = 4, 1923 .frac_bits = 0, 1924 .tcnt_mux = 38), 1925 [BCM2835_CLOCK_CAM0] = REGISTER_PER_CLK( 1926 .name = "cam0", 1927 .ctl_reg = CM_CAM0CTL, 1928 .div_reg = CM_CAM0DIV, 1929 .int_bits = 4, 1930 .frac_bits = 8, 1931 .tcnt_mux = 14), 1932 [BCM2835_CLOCK_CAM1] = REGISTER_PER_CLK( 1933 .name = "cam1", 1934 .ctl_reg = CM_CAM1CTL, 1935 .div_reg = CM_CAM1DIV, 1936 .int_bits = 4, 1937 .frac_bits = 8, 1938 .tcnt_mux = 15), 1939 [BCM2835_CLOCK_DFT] = REGISTER_PER_CLK( 1940 .name = "dft", 1941 .ctl_reg = CM_DFTCTL, 1942 .div_reg = CM_DFTDIV, 1943 .int_bits = 5, 1944 .frac_bits = 0), 1945 [BCM2835_CLOCK_DPI] = REGISTER_PER_CLK( 1946 .name = "dpi", 1947 .ctl_reg = CM_DPICTL, 1948 .div_reg = CM_DPIDIV, 1949 .int_bits = 4, 1950 .frac_bits = 8, 1951 .tcnt_mux = 17), 1952 1953 /* Arasan EMMC clock */ 1954 [BCM2835_CLOCK_EMMC] = REGISTER_PER_CLK( 1955 .name = "emmc", 1956 .ctl_reg = CM_EMMCCTL, 1957 .div_reg = CM_EMMCDIV, 1958 .int_bits = 4, 1959 .frac_bits = 8, 1960 .tcnt_mux = 39), 1961 1962 /* General purpose (GPIO) clocks */ 1963 [BCM2835_CLOCK_GP0] = REGISTER_PER_CLK( 1964 .name = "gp0", 1965 .ctl_reg = CM_GP0CTL, 1966 .div_reg = CM_GP0DIV, 1967 .int_bits = 12, 1968 .frac_bits = 12, 1969 .is_mash_clock = true, 1970 .tcnt_mux = 20), 1971 [BCM2835_CLOCK_GP1] = REGISTER_PER_CLK( 1972 .name = "gp1", 1973 .ctl_reg = CM_GP1CTL, 1974 .div_reg = CM_GP1DIV, 1975 .int_bits = 12, 1976 .frac_bits = 12, 1977 .flags = CLK_IS_CRITICAL, 1978 .is_mash_clock = true, 1979 .tcnt_mux = 21), 1980 [BCM2835_CLOCK_GP2] = REGISTER_PER_CLK( 1981 .name = "gp2", 1982 .ctl_reg = CM_GP2CTL, 1983 .div_reg = CM_GP2DIV, 1984 .int_bits = 12, 1985 .frac_bits = 12, 1986 .flags = CLK_IS_CRITICAL), 1987 1988 /* HDMI state machine */ 1989 [BCM2835_CLOCK_HSM] = REGISTER_PER_CLK( 1990 .name = "hsm", 1991 .ctl_reg = CM_HSMCTL, 1992 .div_reg = CM_HSMDIV, 1993 .int_bits = 4, 1994 .frac_bits = 8, 1995 .tcnt_mux = 22), 1996 [BCM2835_CLOCK_PCM] = REGISTER_PER_CLK( 1997 .name = "pcm", 1998 .ctl_reg = CM_PCMCTL, 1999 .div_reg = CM_PCMDIV, 2000 .int_bits = 12, 2001 .frac_bits = 12, 2002 .is_mash_clock = true, 2003 .tcnt_mux = 23), 2004 [BCM2835_CLOCK_PWM] = REGISTER_PER_CLK( 2005 .name = "pwm", 2006 .ctl_reg = CM_PWMCTL, 2007 .div_reg = CM_PWMDIV, 2008 .int_bits = 12, 2009 .frac_bits = 12, 2010 .is_mash_clock = true, 2011 .tcnt_mux = 24), 2012 [BCM2835_CLOCK_SLIM] = REGISTER_PER_CLK( 2013 .name = "slim", 2014 .ctl_reg = CM_SLIMCTL, 2015 .div_reg = CM_SLIMDIV, 2016 .int_bits = 12, 2017 .frac_bits = 12, 2018 .is_mash_clock = true, 2019 .tcnt_mux = 25), 2020 [BCM2835_CLOCK_SMI] = REGISTER_PER_CLK( 2021 .name = "smi", 2022 .ctl_reg = CM_SMICTL, 2023 .div_reg = CM_SMIDIV, 2024 .int_bits = 4, 2025 .frac_bits = 8, 2026 .tcnt_mux = 27), 2027 [BCM2835_CLOCK_UART] = REGISTER_PER_CLK( 2028 .name = "uart", 2029 .ctl_reg = CM_UARTCTL, 2030 .div_reg = CM_UARTDIV, 2031 .int_bits = 10, 2032 .frac_bits = 12, 2033 .tcnt_mux = 28), 2034 2035 /* TV encoder clock. Only operating frequency is 108Mhz. */ 2036 [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK( 2037 .name = "vec", 2038 .ctl_reg = CM_VECCTL, 2039 .div_reg = CM_VECDIV, 2040 .int_bits = 4, 2041 .frac_bits = 0, 2042 /* 2043 * Allow rate change propagation only on PLLH_AUX which is 2044 * assigned index 7 in the parent array. 2045 */ 2046 .set_rate_parent = BIT(7), 2047 .tcnt_mux = 29), 2048 2049 /* dsi clocks */ 2050 [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK( 2051 .name = "dsi0e", 2052 .ctl_reg = CM_DSI0ECTL, 2053 .div_reg = CM_DSI0EDIV, 2054 .int_bits = 4, 2055 .frac_bits = 8, 2056 .tcnt_mux = 18), 2057 [BCM2835_CLOCK_DSI1E] = REGISTER_PER_CLK( 2058 .name = "dsi1e", 2059 .ctl_reg = CM_DSI1ECTL, 2060 .div_reg = CM_DSI1EDIV, 2061 .int_bits = 4, 2062 .frac_bits = 8, 2063 .tcnt_mux = 19), 2064 [BCM2835_CLOCK_DSI0P] = REGISTER_DSI0_CLK( 2065 .name = "dsi0p", 2066 .ctl_reg = CM_DSI0PCTL, 2067 .div_reg = CM_DSI0PDIV, 2068 .int_bits = 0, 2069 .frac_bits = 0, 2070 .tcnt_mux = 12), 2071 [BCM2835_CLOCK_DSI1P] = REGISTER_DSI1_CLK( 2072 .name = "dsi1p", 2073 .ctl_reg = CM_DSI1PCTL, 2074 .div_reg = CM_DSI1PDIV, 2075 .int_bits = 0, 2076 .frac_bits = 0, 2077 .tcnt_mux = 13), 2078 2079 /* the gates */ 2080 2081 /* 2082 * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if 2083 * you have the debug bit set in the power manager, which we 2084 * don't bother exposing) are individual gates off of the 2085 * non-stop vpu clock. 2086 */ 2087 [BCM2835_CLOCK_PERI_IMAGE] = REGISTER_GATE( 2088 .name = "peri_image", 2089 .parent = "vpu", 2090 .ctl_reg = CM_PERIICTL), 2091 }; 2092 2093 /* 2094 * Permanently take a reference on the parent of the SDRAM clock. 2095 * 2096 * While the SDRAM is being driven by its dedicated PLL most of the 2097 * time, there is a little loop running in the firmware that 2098 * periodically switches the SDRAM to using our CM clock to do PVT 2099 * recalibration, with the assumption that the previously configured 2100 * SDRAM parent is still enabled and running. 2101 */ 2102 static int bcm2835_mark_sdc_parent_critical(struct clk *sdc) 2103 { 2104 struct clk *parent = clk_get_parent(sdc); 2105 2106 if (IS_ERR(parent)) 2107 return PTR_ERR(parent); 2108 2109 return clk_prepare_enable(parent); 2110 } 2111 2112 static int bcm2835_clk_probe(struct platform_device *pdev) 2113 { 2114 struct device *dev = &pdev->dev; 2115 struct clk_hw **hws; 2116 struct bcm2835_cprman *cprman; 2117 struct resource *res; 2118 const struct bcm2835_clk_desc *desc; 2119 const size_t asize = ARRAY_SIZE(clk_desc_array); 2120 size_t i; 2121 int ret; 2122 2123 cprman = devm_kzalloc(dev, sizeof(*cprman) + 2124 sizeof(*cprman->onecell.hws) * asize, 2125 GFP_KERNEL); 2126 if (!cprman) 2127 return -ENOMEM; 2128 2129 spin_lock_init(&cprman->regs_lock); 2130 cprman->dev = dev; 2131 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2132 cprman->regs = devm_ioremap_resource(dev, res); 2133 if (IS_ERR(cprman->regs)) 2134 return PTR_ERR(cprman->regs); 2135 2136 memcpy(cprman->real_parent_names, cprman_parent_names, 2137 sizeof(cprman_parent_names)); 2138 of_clk_parent_fill(dev->of_node, cprman->real_parent_names, 2139 ARRAY_SIZE(cprman_parent_names)); 2140 2141 /* 2142 * Make sure the external oscillator has been registered. 2143 * 2144 * The other (DSI) clocks are not present on older device 2145 * trees, which we still need to support for backwards 2146 * compatibility. 2147 */ 2148 if (!cprman->real_parent_names[0]) 2149 return -ENODEV; 2150 2151 platform_set_drvdata(pdev, cprman); 2152 2153 cprman->onecell.num = asize; 2154 hws = cprman->onecell.hws; 2155 2156 for (i = 0; i < asize; i++) { 2157 desc = &clk_desc_array[i]; 2158 if (desc->clk_register && desc->data) 2159 hws[i] = desc->clk_register(cprman, desc->data); 2160 } 2161 2162 ret = bcm2835_mark_sdc_parent_critical(hws[BCM2835_CLOCK_SDRAM]->clk); 2163 if (ret) 2164 return ret; 2165 2166 return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, 2167 &cprman->onecell); 2168 } 2169 2170 static const struct of_device_id bcm2835_clk_of_match[] = { 2171 { .compatible = "brcm,bcm2835-cprman", }, 2172 {} 2173 }; 2174 MODULE_DEVICE_TABLE(of, bcm2835_clk_of_match); 2175 2176 static struct platform_driver bcm2835_clk_driver = { 2177 .driver = { 2178 .name = "bcm2835-clk", 2179 .of_match_table = bcm2835_clk_of_match, 2180 }, 2181 .probe = bcm2835_clk_probe, 2182 }; 2183 2184 builtin_platform_driver(bcm2835_clk_driver); 2185 2186 MODULE_AUTHOR("Eric Anholt <eric@anholt.net>"); 2187 MODULE_DESCRIPTION("BCM2835 clock driver"); 2188 MODULE_LICENSE("GPL v2"); 2189