xref: /openbmc/linux/drivers/clk/axs10x/pll_clock.c (revision 9fb29c73)
1 /*
2  * Synopsys AXS10X SDP Generic PLL clock driver
3  *
4  * Copyright (C) 2017 Synopsys
5  *
6  * This file is licensed under the terms of the GNU General Public
7  * License version 2. This program is licensed "as is" without any
8  * warranty of any kind, whether express or implied.
9  */
10 
11 #include <linux/platform_device.h>
12 #include <linux/module.h>
13 #include <linux/clk-provider.h>
14 #include <linux/delay.h>
15 #include <linux/err.h>
16 #include <linux/device.h>
17 #include <linux/of_address.h>
18 #include <linux/of_device.h>
19 #include <linux/slab.h>
20 #include <linux/of.h>
21 
22 /* PLL registers addresses */
23 #define PLL_REG_IDIV	0x0
24 #define PLL_REG_FBDIV	0x4
25 #define PLL_REG_ODIV	0x8
26 
27 /*
28  * Bit fields of the PLL IDIV/FBDIV/ODIV registers:
29  *  ________________________________________________________________________
30  * |31                15|    14    |   13   |  12  |11         6|5         0|
31  * |-------RESRVED------|-NOUPDATE-|-BYPASS-|-EDGE-|--HIGHTIME--|--LOWTIME--|
32  * |____________________|__________|________|______|____________|___________|
33  *
34  * Following macros determine the way of access to these registers
35  * They should be set up only using the macros.
36  * reg should be an u32 variable.
37  */
38 
39 #define PLL_REG_GET_LOW(reg)			\
40 	(((reg) & (0x3F << 0)) >> 0)
41 #define PLL_REG_GET_HIGH(reg)			\
42 	(((reg) & (0x3F << 6)) >> 6)
43 #define PLL_REG_GET_EDGE(reg)			\
44 	(((reg) & (BIT(12))) ? 1 : 0)
45 #define PLL_REG_GET_BYPASS(reg)			\
46 	(((reg) & (BIT(13))) ? 1 : 0)
47 #define PLL_REG_GET_NOUPD(reg)			\
48 	(((reg) & (BIT(14))) ? 1 : 0)
49 #define PLL_REG_GET_PAD(reg)			\
50 	(((reg) & (0x1FFFF << 15)) >> 15)
51 
52 #define PLL_REG_SET_LOW(reg, value)		\
53 	{ reg |= (((value) & 0x3F) << 0); }
54 #define PLL_REG_SET_HIGH(reg, value)		\
55 	{ reg |= (((value) & 0x3F) << 6); }
56 #define PLL_REG_SET_EDGE(reg, value)		\
57 	{ reg |= (((value) & 0x01) << 12); }
58 #define PLL_REG_SET_BYPASS(reg, value)		\
59 	{ reg |= (((value) & 0x01) << 13); }
60 #define PLL_REG_SET_NOUPD(reg, value)		\
61 	{ reg |= (((value) & 0x01) << 14); }
62 #define PLL_REG_SET_PAD(reg, value)		\
63 	{ reg |= (((value) & 0x1FFFF) << 15); }
64 
65 #define PLL_LOCK	BIT(0)
66 #define PLL_ERROR	BIT(1)
67 #define PLL_MAX_LOCK_TIME 100 /* 100 us */
68 
69 struct axs10x_pll_cfg {
70 	u32 rate;
71 	u32 idiv;
72 	u32 fbdiv;
73 	u32 odiv;
74 };
75 
76 static const struct axs10x_pll_cfg arc_pll_cfg[] = {
77 	{ 33333333,  1, 1,  1 },
78 	{ 50000000,  1, 30, 20 },
79 	{ 75000000,  2, 45, 10 },
80 	{ 90000000,  2, 54, 10 },
81 	{ 100000000, 1, 30, 10 },
82 	{ 125000000, 2, 45, 6 },
83 	{}
84 };
85 
86 static const struct axs10x_pll_cfg pgu_pll_cfg[] = {
87 	{ 25200000, 1, 84, 90 },
88 	{ 50000000, 1, 100, 54 },
89 	{ 74250000, 1, 44, 16 },
90 	{}
91 };
92 
93 struct axs10x_pll_clk {
94 	struct clk_hw hw;
95 	void __iomem *base;
96 	void __iomem *lock;
97 	const struct axs10x_pll_cfg *pll_cfg;
98 	struct device *dev;
99 };
100 
101 static inline void axs10x_pll_write(struct axs10x_pll_clk *clk, u32 reg,
102 				    u32 val)
103 {
104 	iowrite32(val, clk->base + reg);
105 }
106 
107 static inline u32 axs10x_pll_read(struct axs10x_pll_clk *clk, u32 reg)
108 {
109 	return ioread32(clk->base + reg);
110 }
111 
112 static inline struct axs10x_pll_clk *to_axs10x_pll_clk(struct clk_hw *hw)
113 {
114 	return container_of(hw, struct axs10x_pll_clk, hw);
115 }
116 
117 static inline u32 axs10x_div_get_value(u32 reg)
118 {
119 	if (PLL_REG_GET_BYPASS(reg))
120 		return 1;
121 
122 	return PLL_REG_GET_HIGH(reg) + PLL_REG_GET_LOW(reg);
123 }
124 
125 static inline u32 axs10x_encode_div(unsigned int id, int upd)
126 {
127 	u32 div = 0;
128 
129 	PLL_REG_SET_LOW(div, (id % 2 == 0) ? id >> 1 : (id >> 1) + 1);
130 	PLL_REG_SET_HIGH(div, id >> 1);
131 	PLL_REG_SET_EDGE(div, id % 2);
132 	PLL_REG_SET_BYPASS(div, id == 1 ? 1 : 0);
133 	PLL_REG_SET_NOUPD(div, upd == 0 ? 1 : 0);
134 
135 	return div;
136 }
137 
138 static unsigned long axs10x_pll_recalc_rate(struct clk_hw *hw,
139 					    unsigned long parent_rate)
140 {
141 	u64 rate;
142 	u32 idiv, fbdiv, odiv;
143 	struct axs10x_pll_clk *clk = to_axs10x_pll_clk(hw);
144 
145 	idiv = axs10x_div_get_value(axs10x_pll_read(clk, PLL_REG_IDIV));
146 	fbdiv = axs10x_div_get_value(axs10x_pll_read(clk, PLL_REG_FBDIV));
147 	odiv = axs10x_div_get_value(axs10x_pll_read(clk, PLL_REG_ODIV));
148 
149 	rate = (u64)parent_rate * fbdiv;
150 	do_div(rate, idiv * odiv);
151 
152 	return rate;
153 }
154 
155 static long axs10x_pll_round_rate(struct clk_hw *hw, unsigned long rate,
156 				  unsigned long *prate)
157 {
158 	int i;
159 	long best_rate;
160 	struct axs10x_pll_clk *clk = to_axs10x_pll_clk(hw);
161 	const struct axs10x_pll_cfg *pll_cfg = clk->pll_cfg;
162 
163 	if (pll_cfg[0].rate == 0)
164 		return -EINVAL;
165 
166 	best_rate = pll_cfg[0].rate;
167 
168 	for (i = 1; pll_cfg[i].rate != 0; i++) {
169 		if (abs(rate - pll_cfg[i].rate) < abs(rate - best_rate))
170 			best_rate = pll_cfg[i].rate;
171 	}
172 
173 	return best_rate;
174 }
175 
176 static int axs10x_pll_set_rate(struct clk_hw *hw, unsigned long rate,
177 			       unsigned long parent_rate)
178 {
179 	int i;
180 	struct axs10x_pll_clk *clk = to_axs10x_pll_clk(hw);
181 	const struct axs10x_pll_cfg *pll_cfg = clk->pll_cfg;
182 
183 	for (i = 0; pll_cfg[i].rate != 0; i++) {
184 		if (pll_cfg[i].rate == rate) {
185 			axs10x_pll_write(clk, PLL_REG_IDIV,
186 					 axs10x_encode_div(pll_cfg[i].idiv, 0));
187 			axs10x_pll_write(clk, PLL_REG_FBDIV,
188 					 axs10x_encode_div(pll_cfg[i].fbdiv, 0));
189 			axs10x_pll_write(clk, PLL_REG_ODIV,
190 					 axs10x_encode_div(pll_cfg[i].odiv, 1));
191 
192 			/*
193 			 * Wait until CGU relocks and check error status.
194 			 * If after timeout CGU is unlocked yet return error
195 			 */
196 			udelay(PLL_MAX_LOCK_TIME);
197 			if (!(ioread32(clk->lock) & PLL_LOCK))
198 				return -ETIMEDOUT;
199 
200 			if (ioread32(clk->lock) & PLL_ERROR)
201 				return -EINVAL;
202 
203 			return 0;
204 		}
205 	}
206 
207 	dev_err(clk->dev, "invalid rate=%ld, parent_rate=%ld\n", rate,
208 			parent_rate);
209 	return -EINVAL;
210 }
211 
212 static const struct clk_ops axs10x_pll_ops = {
213 	.recalc_rate = axs10x_pll_recalc_rate,
214 	.round_rate = axs10x_pll_round_rate,
215 	.set_rate = axs10x_pll_set_rate,
216 };
217 
218 static int axs10x_pll_clk_probe(struct platform_device *pdev)
219 {
220 	struct device *dev = &pdev->dev;
221 	const char *parent_name;
222 	struct axs10x_pll_clk *pll_clk;
223 	struct resource *mem;
224 	struct clk_init_data init = { };
225 	int ret;
226 
227 	pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL);
228 	if (!pll_clk)
229 		return -ENOMEM;
230 
231 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
232 	pll_clk->base = devm_ioremap_resource(dev, mem);
233 	if (IS_ERR(pll_clk->base))
234 		return PTR_ERR(pll_clk->base);
235 
236 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
237 	pll_clk->lock = devm_ioremap_resource(dev, mem);
238 	if (IS_ERR(pll_clk->lock))
239 		return PTR_ERR(pll_clk->lock);
240 
241 	init.name = dev->of_node->name;
242 	init.ops = &axs10x_pll_ops;
243 	parent_name = of_clk_get_parent_name(dev->of_node, 0);
244 	init.parent_names = &parent_name;
245 	init.num_parents = 1;
246 	pll_clk->hw.init = &init;
247 	pll_clk->dev = dev;
248 	pll_clk->pll_cfg = of_device_get_match_data(dev);
249 
250 	if (!pll_clk->pll_cfg) {
251 		dev_err(dev, "No OF match data provided\n");
252 		return -EINVAL;
253 	}
254 
255 	ret = devm_clk_hw_register(dev, &pll_clk->hw);
256 	if (ret) {
257 		dev_err(dev, "failed to register %s clock\n", init.name);
258 		return ret;
259 	}
260 
261 	return of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get,
262 			&pll_clk->hw);
263 }
264 
265 static int axs10x_pll_clk_remove(struct platform_device *pdev)
266 {
267 	of_clk_del_provider(pdev->dev.of_node);
268 	return 0;
269 }
270 
271 static void __init of_axs10x_pll_clk_setup(struct device_node *node)
272 {
273 	const char *parent_name;
274 	struct axs10x_pll_clk *pll_clk;
275 	struct clk_init_data init = { };
276 	int ret;
277 
278 	pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
279 	if (!pll_clk)
280 		return;
281 
282 	pll_clk->base = of_iomap(node, 0);
283 	if (!pll_clk->base) {
284 		pr_err("failed to map pll div registers\n");
285 		goto err_free_pll_clk;
286 	}
287 
288 	pll_clk->lock = of_iomap(node, 1);
289 	if (!pll_clk->lock) {
290 		pr_err("failed to map pll lock register\n");
291 		goto err_unmap_base;
292 	}
293 
294 	init.name = node->name;
295 	init.ops = &axs10x_pll_ops;
296 	parent_name = of_clk_get_parent_name(node, 0);
297 	init.parent_names = &parent_name;
298 	init.num_parents = parent_name ? 1 : 0;
299 	pll_clk->hw.init = &init;
300 	pll_clk->pll_cfg = arc_pll_cfg;
301 
302 	ret = clk_hw_register(NULL, &pll_clk->hw);
303 	if (ret) {
304 		pr_err("failed to register %pOFn clock\n", node);
305 		goto err_unmap_lock;
306 	}
307 
308 	ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll_clk->hw);
309 	if (ret) {
310 		pr_err("failed to add hw provider for %pOFn clock\n", node);
311 		goto err_unregister_clk;
312 	}
313 
314 	return;
315 
316 err_unregister_clk:
317 	clk_hw_unregister(&pll_clk->hw);
318 err_unmap_lock:
319 	iounmap(pll_clk->lock);
320 err_unmap_base:
321 	iounmap(pll_clk->base);
322 err_free_pll_clk:
323 	kfree(pll_clk);
324 }
325 CLK_OF_DECLARE(axs10x_pll_clock, "snps,axs10x-arc-pll-clock",
326 	       of_axs10x_pll_clk_setup);
327 
328 static const struct of_device_id axs10x_pll_clk_id[] = {
329 	{ .compatible = "snps,axs10x-pgu-pll-clock", .data = &pgu_pll_cfg},
330 	{ }
331 };
332 MODULE_DEVICE_TABLE(of, axs10x_pll_clk_id);
333 
334 static struct platform_driver axs10x_pll_clk_driver = {
335 	.driver = {
336 		.name = "axs10x-pll-clock",
337 		.of_match_table = axs10x_pll_clk_id,
338 	},
339 	.probe = axs10x_pll_clk_probe,
340 	.remove = axs10x_pll_clk_remove,
341 };
342 builtin_platform_driver(axs10x_pll_clk_driver);
343 
344 MODULE_AUTHOR("Vlad Zakharov <vzakhar@synopsys.com>");
345 MODULE_DESCRIPTION("Synopsys AXS10X SDP Generic PLL Clock Driver");
346 MODULE_LICENSE("GPL v2");
347