xref: /openbmc/linux/drivers/clk/at91/sckc.c (revision d35ac6ac) 
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * drivers/clk/at91/sckc.c
4  *
5  *  Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
6  */
7 
8 #include <linux/clk-provider.h>
9 #include <linux/clkdev.h>
10 #include <linux/delay.h>
11 #include <linux/of.h>
12 #include <linux/of_address.h>
13 #include <linux/io.h>
14 
15 #define SLOW_CLOCK_FREQ		32768
16 #define SLOWCK_SW_CYCLES	5
17 #define SLOWCK_SW_TIME_USEC	((SLOWCK_SW_CYCLES * USEC_PER_SEC) / \
18 				 SLOW_CLOCK_FREQ)
19 
20 #define	AT91_SCKC_CR			0x00
21 
22 struct clk_slow_bits {
23 	u32 cr_rcen;
24 	u32 cr_osc32en;
25 	u32 cr_osc32byp;
26 	u32 cr_oscsel;
27 };
28 
29 struct clk_slow_osc {
30 	struct clk_hw hw;
31 	void __iomem *sckcr;
32 	const struct clk_slow_bits *bits;
33 	unsigned long startup_usec;
34 };
35 
36 #define to_clk_slow_osc(hw) container_of(hw, struct clk_slow_osc, hw)
37 
38 struct clk_sama5d4_slow_osc {
39 	struct clk_hw hw;
40 	void __iomem *sckcr;
41 	const struct clk_slow_bits *bits;
42 	unsigned long startup_usec;
43 	bool prepared;
44 };
45 
46 #define to_clk_sama5d4_slow_osc(hw) container_of(hw, struct clk_sama5d4_slow_osc, hw)
47 
48 struct clk_slow_rc_osc {
49 	struct clk_hw hw;
50 	void __iomem *sckcr;
51 	const struct clk_slow_bits *bits;
52 	unsigned long frequency;
53 	unsigned long accuracy;
54 	unsigned long startup_usec;
55 };
56 
57 #define to_clk_slow_rc_osc(hw) container_of(hw, struct clk_slow_rc_osc, hw)
58 
59 struct clk_sam9x5_slow {
60 	struct clk_hw hw;
61 	void __iomem *sckcr;
62 	const struct clk_slow_bits *bits;
63 	u8 parent;
64 };
65 
66 #define to_clk_sam9x5_slow(hw) container_of(hw, struct clk_sam9x5_slow, hw)
67 
68 static int clk_slow_osc_prepare(struct clk_hw *hw)
69 {
70 	struct clk_slow_osc *osc = to_clk_slow_osc(hw);
71 	void __iomem *sckcr = osc->sckcr;
72 	u32 tmp = readl(sckcr);
73 
74 	if (tmp & (osc->bits->cr_osc32byp | osc->bits->cr_osc32en))
75 		return 0;
76 
77 	writel(tmp | osc->bits->cr_osc32en, sckcr);
78 
79 	if (system_state < SYSTEM_RUNNING)
80 		udelay(osc->startup_usec);
81 	else
82 		usleep_range(osc->startup_usec, osc->startup_usec + 1);
83 
84 	return 0;
85 }
86 
87 static void clk_slow_osc_unprepare(struct clk_hw *hw)
88 {
89 	struct clk_slow_osc *osc = to_clk_slow_osc(hw);
90 	void __iomem *sckcr = osc->sckcr;
91 	u32 tmp = readl(sckcr);
92 
93 	if (tmp & osc->bits->cr_osc32byp)
94 		return;
95 
96 	writel(tmp & ~osc->bits->cr_osc32en, sckcr);
97 }
98 
99 static int clk_slow_osc_is_prepared(struct clk_hw *hw)
100 {
101 	struct clk_slow_osc *osc = to_clk_slow_osc(hw);
102 	void __iomem *sckcr = osc->sckcr;
103 	u32 tmp = readl(sckcr);
104 
105 	if (tmp & osc->bits->cr_osc32byp)
106 		return 1;
107 
108 	return !!(tmp & osc->bits->cr_osc32en);
109 }
110 
111 static const struct clk_ops slow_osc_ops = {
112 	.prepare = clk_slow_osc_prepare,
113 	.unprepare = clk_slow_osc_unprepare,
114 	.is_prepared = clk_slow_osc_is_prepared,
115 };
116 
117 static struct clk_hw * __init
118 at91_clk_register_slow_osc(void __iomem *sckcr,
119 			   const char *name,
120 			   const char *parent_name,
121 			   unsigned long startup,
122 			   bool bypass,
123 			   const struct clk_slow_bits *bits)
124 {
125 	struct clk_slow_osc *osc;
126 	struct clk_hw *hw;
127 	struct clk_init_data init;
128 	int ret;
129 
130 	if (!sckcr || !name || !parent_name)
131 		return ERR_PTR(-EINVAL);
132 
133 	osc = kzalloc(sizeof(*osc), GFP_KERNEL);
134 	if (!osc)
135 		return ERR_PTR(-ENOMEM);
136 
137 	init.name = name;
138 	init.ops = &slow_osc_ops;
139 	init.parent_names = &parent_name;
140 	init.num_parents = 1;
141 	init.flags = CLK_IGNORE_UNUSED;
142 
143 	osc->hw.init = &init;
144 	osc->sckcr = sckcr;
145 	osc->startup_usec = startup;
146 	osc->bits = bits;
147 
148 	if (bypass)
149 		writel((readl(sckcr) & ~osc->bits->cr_osc32en) |
150 					osc->bits->cr_osc32byp, sckcr);
151 
152 	hw = &osc->hw;
153 	ret = clk_hw_register(NULL, &osc->hw);
154 	if (ret) {
155 		kfree(osc);
156 		hw = ERR_PTR(ret);
157 	}
158 
159 	return hw;
160 }
161 
162 static void at91_clk_unregister_slow_osc(struct clk_hw *hw)
163 {
164 	struct clk_slow_osc *osc = to_clk_slow_osc(hw);
165 
166 	clk_hw_unregister(hw);
167 	kfree(osc);
168 }
169 
170 static unsigned long clk_slow_rc_osc_recalc_rate(struct clk_hw *hw,
171 						 unsigned long parent_rate)
172 {
173 	struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
174 
175 	return osc->frequency;
176 }
177 
178 static unsigned long clk_slow_rc_osc_recalc_accuracy(struct clk_hw *hw,
179 						     unsigned long parent_acc)
180 {
181 	struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
182 
183 	return osc->accuracy;
184 }
185 
186 static int clk_slow_rc_osc_prepare(struct clk_hw *hw)
187 {
188 	struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
189 	void __iomem *sckcr = osc->sckcr;
190 
191 	writel(readl(sckcr) | osc->bits->cr_rcen, sckcr);
192 
193 	if (system_state < SYSTEM_RUNNING)
194 		udelay(osc->startup_usec);
195 	else
196 		usleep_range(osc->startup_usec, osc->startup_usec + 1);
197 
198 	return 0;
199 }
200 
201 static void clk_slow_rc_osc_unprepare(struct clk_hw *hw)
202 {
203 	struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
204 	void __iomem *sckcr = osc->sckcr;
205 
206 	writel(readl(sckcr) & ~osc->bits->cr_rcen, sckcr);
207 }
208 
209 static int clk_slow_rc_osc_is_prepared(struct clk_hw *hw)
210 {
211 	struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
212 
213 	return !!(readl(osc->sckcr) & osc->bits->cr_rcen);
214 }
215 
216 static const struct clk_ops slow_rc_osc_ops = {
217 	.prepare = clk_slow_rc_osc_prepare,
218 	.unprepare = clk_slow_rc_osc_unprepare,
219 	.is_prepared = clk_slow_rc_osc_is_prepared,
220 	.recalc_rate = clk_slow_rc_osc_recalc_rate,
221 	.recalc_accuracy = clk_slow_rc_osc_recalc_accuracy,
222 };
223 
224 static struct clk_hw * __init
225 at91_clk_register_slow_rc_osc(void __iomem *sckcr,
226 			      const char *name,
227 			      unsigned long frequency,
228 			      unsigned long accuracy,
229 			      unsigned long startup,
230 			      const struct clk_slow_bits *bits)
231 {
232 	struct clk_slow_rc_osc *osc;
233 	struct clk_hw *hw;
234 	struct clk_init_data init;
235 	int ret;
236 
237 	if (!sckcr || !name)
238 		return ERR_PTR(-EINVAL);
239 
240 	osc = kzalloc(sizeof(*osc), GFP_KERNEL);
241 	if (!osc)
242 		return ERR_PTR(-ENOMEM);
243 
244 	init.name = name;
245 	init.ops = &slow_rc_osc_ops;
246 	init.parent_names = NULL;
247 	init.num_parents = 0;
248 	init.flags = CLK_IGNORE_UNUSED;
249 
250 	osc->hw.init = &init;
251 	osc->sckcr = sckcr;
252 	osc->bits = bits;
253 	osc->frequency = frequency;
254 	osc->accuracy = accuracy;
255 	osc->startup_usec = startup;
256 
257 	hw = &osc->hw;
258 	ret = clk_hw_register(NULL, &osc->hw);
259 	if (ret) {
260 		kfree(osc);
261 		hw = ERR_PTR(ret);
262 	}
263 
264 	return hw;
265 }
266 
267 static void at91_clk_unregister_slow_rc_osc(struct clk_hw *hw)
268 {
269 	struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
270 
271 	clk_hw_unregister(hw);
272 	kfree(osc);
273 }
274 
275 static int clk_sam9x5_slow_set_parent(struct clk_hw *hw, u8 index)
276 {
277 	struct clk_sam9x5_slow *slowck = to_clk_sam9x5_slow(hw);
278 	void __iomem *sckcr = slowck->sckcr;
279 	u32 tmp;
280 
281 	if (index > 1)
282 		return -EINVAL;
283 
284 	tmp = readl(sckcr);
285 
286 	if ((!index && !(tmp & slowck->bits->cr_oscsel)) ||
287 	    (index && (tmp & slowck->bits->cr_oscsel)))
288 		return 0;
289 
290 	if (index)
291 		tmp |= slowck->bits->cr_oscsel;
292 	else
293 		tmp &= ~slowck->bits->cr_oscsel;
294 
295 	writel(tmp, sckcr);
296 
297 	if (system_state < SYSTEM_RUNNING)
298 		udelay(SLOWCK_SW_TIME_USEC);
299 	else
300 		usleep_range(SLOWCK_SW_TIME_USEC, SLOWCK_SW_TIME_USEC + 1);
301 
302 	return 0;
303 }
304 
305 static u8 clk_sam9x5_slow_get_parent(struct clk_hw *hw)
306 {
307 	struct clk_sam9x5_slow *slowck = to_clk_sam9x5_slow(hw);
308 
309 	return !!(readl(slowck->sckcr) & slowck->bits->cr_oscsel);
310 }
311 
312 static const struct clk_ops sam9x5_slow_ops = {
313 	.determine_rate = clk_hw_determine_rate_no_reparent,
314 	.set_parent = clk_sam9x5_slow_set_parent,
315 	.get_parent = clk_sam9x5_slow_get_parent,
316 };
317 
318 static struct clk_hw * __init
319 at91_clk_register_sam9x5_slow(void __iomem *sckcr,
320 			      const char *name,
321 			      const char **parent_names,
322 			      int num_parents,
323 			      const struct clk_slow_bits *bits)
324 {
325 	struct clk_sam9x5_slow *slowck;
326 	struct clk_hw *hw;
327 	struct clk_init_data init;
328 	int ret;
329 
330 	if (!sckcr || !name || !parent_names || !num_parents)
331 		return ERR_PTR(-EINVAL);
332 
333 	slowck = kzalloc(sizeof(*slowck), GFP_KERNEL);
334 	if (!slowck)
335 		return ERR_PTR(-ENOMEM);
336 
337 	init.name = name;
338 	init.ops = &sam9x5_slow_ops;
339 	init.parent_names = parent_names;
340 	init.num_parents = num_parents;
341 	init.flags = 0;
342 
343 	slowck->hw.init = &init;
344 	slowck->sckcr = sckcr;
345 	slowck->bits = bits;
346 	slowck->parent = !!(readl(sckcr) & slowck->bits->cr_oscsel);
347 
348 	hw = &slowck->hw;
349 	ret = clk_hw_register(NULL, &slowck->hw);
350 	if (ret) {
351 		kfree(slowck);
352 		hw = ERR_PTR(ret);
353 	}
354 
355 	return hw;
356 }
357 
358 static void at91_clk_unregister_sam9x5_slow(struct clk_hw *hw)
359 {
360 	struct clk_sam9x5_slow *slowck = to_clk_sam9x5_slow(hw);
361 
362 	clk_hw_unregister(hw);
363 	kfree(slowck);
364 }
365 
366 static void __init at91sam9x5_sckc_register(struct device_node *np,
367 					    unsigned int rc_osc_startup_us,
368 					    const struct clk_slow_bits *bits)
369 {
370 	const char *parent_names[2] = { "slow_rc_osc", "slow_osc" };
371 	void __iomem *regbase = of_iomap(np, 0);
372 	struct device_node *child = NULL;
373 	const char *xtal_name;
374 	struct clk_hw *slow_rc, *slow_osc, *slowck;
375 	bool bypass;
376 	int ret;
377 
378 	if (!regbase)
379 		return;
380 
381 	slow_rc = at91_clk_register_slow_rc_osc(regbase, parent_names[0],
382 						32768, 50000000,
383 						rc_osc_startup_us, bits);
384 	if (IS_ERR(slow_rc))
385 		return;
386 
387 	xtal_name = of_clk_get_parent_name(np, 0);
388 	if (!xtal_name) {
389 		/* DT backward compatibility */
390 		child = of_get_compatible_child(np, "atmel,at91sam9x5-clk-slow-osc");
391 		if (!child)
392 			goto unregister_slow_rc;
393 
394 		xtal_name = of_clk_get_parent_name(child, 0);
395 		bypass = of_property_read_bool(child, "atmel,osc-bypass");
396 
397 		child =  of_get_compatible_child(np, "atmel,at91sam9x5-clk-slow");
398 	} else {
399 		bypass = of_property_read_bool(np, "atmel,osc-bypass");
400 	}
401 
402 	if (!xtal_name)
403 		goto unregister_slow_rc;
404 
405 	slow_osc = at91_clk_register_slow_osc(regbase, parent_names[1],
406 					      xtal_name, 1200000, bypass, bits);
407 	if (IS_ERR(slow_osc))
408 		goto unregister_slow_rc;
409 
410 	slowck = at91_clk_register_sam9x5_slow(regbase, "slowck", parent_names,
411 					       2, bits);
412 	if (IS_ERR(slowck))
413 		goto unregister_slow_osc;
414 
415 	/* DT backward compatibility */
416 	if (child)
417 		ret = of_clk_add_hw_provider(child, of_clk_hw_simple_get,
418 					     slowck);
419 	else
420 		ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, slowck);
421 
422 	if (WARN_ON(ret))
423 		goto unregister_slowck;
424 
425 	return;
426 
427 unregister_slowck:
428 	at91_clk_unregister_sam9x5_slow(slowck);
429 unregister_slow_osc:
430 	at91_clk_unregister_slow_osc(slow_osc);
431 unregister_slow_rc:
432 	at91_clk_unregister_slow_rc_osc(slow_rc);
433 }
434 
435 static const struct clk_slow_bits at91sam9x5_bits = {
436 	.cr_rcen = BIT(0),
437 	.cr_osc32en = BIT(1),
438 	.cr_osc32byp = BIT(2),
439 	.cr_oscsel = BIT(3),
440 };
441 
442 static void __init of_at91sam9x5_sckc_setup(struct device_node *np)
443 {
444 	at91sam9x5_sckc_register(np, 75, &at91sam9x5_bits);
445 }
446 CLK_OF_DECLARE(at91sam9x5_clk_sckc, "atmel,at91sam9x5-sckc",
447 	       of_at91sam9x5_sckc_setup);
448 
449 static void __init of_sama5d3_sckc_setup(struct device_node *np)
450 {
451 	at91sam9x5_sckc_register(np, 500, &at91sam9x5_bits);
452 }
453 CLK_OF_DECLARE(sama5d3_clk_sckc, "atmel,sama5d3-sckc",
454 	       of_sama5d3_sckc_setup);
455 
456 static const struct clk_slow_bits at91sam9x60_bits = {
457 	.cr_osc32en = BIT(1),
458 	.cr_osc32byp = BIT(2),
459 	.cr_oscsel = BIT(24),
460 };
461 
462 static void __init of_sam9x60_sckc_setup(struct device_node *np)
463 {
464 	void __iomem *regbase = of_iomap(np, 0);
465 	struct clk_hw_onecell_data *clk_data;
466 	struct clk_hw *slow_rc, *slow_osc;
467 	const char *xtal_name;
468 	const char *parent_names[2] = { "slow_rc_osc", "slow_osc" };
469 	bool bypass;
470 	int ret;
471 
472 	if (!regbase)
473 		return;
474 
475 	slow_rc = clk_hw_register_fixed_rate_with_accuracy(NULL, parent_names[0],
476 							   NULL, 0, 32768,
477 							   93750000);
478 	if (IS_ERR(slow_rc))
479 		return;
480 
481 	xtal_name = of_clk_get_parent_name(np, 0);
482 	if (!xtal_name)
483 		goto unregister_slow_rc;
484 
485 	bypass = of_property_read_bool(np, "atmel,osc-bypass");
486 	slow_osc = at91_clk_register_slow_osc(regbase, parent_names[1],
487 					      xtal_name, 5000000, bypass,
488 					      &at91sam9x60_bits);
489 	if (IS_ERR(slow_osc))
490 		goto unregister_slow_rc;
491 
492 	clk_data = kzalloc(struct_size(clk_data, hws, 2), GFP_KERNEL);
493 	if (!clk_data)
494 		goto unregister_slow_osc;
495 
496 	/* MD_SLCK and TD_SLCK. */
497 	clk_data->num = 2;
498 	clk_data->hws[0] = clk_hw_register_fixed_rate(NULL, "md_slck",
499 						      parent_names[0],
500 						      0, 32768);
501 	if (IS_ERR(clk_data->hws[0]))
502 		goto clk_data_free;
503 
504 	clk_data->hws[1] = at91_clk_register_sam9x5_slow(regbase, "td_slck",
505 							 parent_names, 2,
506 							 &at91sam9x60_bits);
507 	if (IS_ERR(clk_data->hws[1]))
508 		goto unregister_md_slck;
509 
510 	ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
511 	if (WARN_ON(ret))
512 		goto unregister_td_slck;
513 
514 	return;
515 
516 unregister_td_slck:
517 	at91_clk_unregister_sam9x5_slow(clk_data->hws[1]);
518 unregister_md_slck:
519 	clk_hw_unregister(clk_data->hws[0]);
520 clk_data_free:
521 	kfree(clk_data);
522 unregister_slow_osc:
523 	at91_clk_unregister_slow_osc(slow_osc);
524 unregister_slow_rc:
525 	clk_hw_unregister(slow_rc);
526 }
527 CLK_OF_DECLARE(sam9x60_clk_sckc, "microchip,sam9x60-sckc",
528 	       of_sam9x60_sckc_setup);
529 
530 static int clk_sama5d4_slow_osc_prepare(struct clk_hw *hw)
531 {
532 	struct clk_sama5d4_slow_osc *osc = to_clk_sama5d4_slow_osc(hw);
533 
534 	if (osc->prepared)
535 		return 0;
536 
537 	/*
538 	 * Assume that if it has already been selected (for example by the
539 	 * bootloader), enough time has already passed.
540 	 */
541 	if ((readl(osc->sckcr) & osc->bits->cr_oscsel)) {
542 		osc->prepared = true;
543 		return 0;
544 	}
545 
546 	if (system_state < SYSTEM_RUNNING)
547 		udelay(osc->startup_usec);
548 	else
549 		usleep_range(osc->startup_usec, osc->startup_usec + 1);
550 	osc->prepared = true;
551 
552 	return 0;
553 }
554 
555 static int clk_sama5d4_slow_osc_is_prepared(struct clk_hw *hw)
556 {
557 	struct clk_sama5d4_slow_osc *osc = to_clk_sama5d4_slow_osc(hw);
558 
559 	return osc->prepared;
560 }
561 
562 static const struct clk_ops sama5d4_slow_osc_ops = {
563 	.prepare = clk_sama5d4_slow_osc_prepare,
564 	.is_prepared = clk_sama5d4_slow_osc_is_prepared,
565 };
566 
567 static const struct clk_slow_bits at91sama5d4_bits = {
568 	.cr_oscsel = BIT(3),
569 };
570 
571 static void __init of_sama5d4_sckc_setup(struct device_node *np)
572 {
573 	void __iomem *regbase = of_iomap(np, 0);
574 	struct clk_hw *slow_rc, *slowck;
575 	struct clk_sama5d4_slow_osc *osc;
576 	struct clk_init_data init;
577 	const char *xtal_name;
578 	const char *parent_names[2] = { "slow_rc_osc", "slow_osc" };
579 	int ret;
580 
581 	if (!regbase)
582 		return;
583 
584 	slow_rc = clk_hw_register_fixed_rate_with_accuracy(NULL,
585 							   parent_names[0],
586 							   NULL, 0, 32768,
587 							   250000000);
588 	if (IS_ERR(slow_rc))
589 		return;
590 
591 	xtal_name = of_clk_get_parent_name(np, 0);
592 
593 	osc = kzalloc(sizeof(*osc), GFP_KERNEL);
594 	if (!osc)
595 		goto unregister_slow_rc;
596 
597 	init.name = parent_names[1];
598 	init.ops = &sama5d4_slow_osc_ops;
599 	init.parent_names = &xtal_name;
600 	init.num_parents = 1;
601 	init.flags = CLK_IGNORE_UNUSED;
602 
603 	osc->hw.init = &init;
604 	osc->sckcr = regbase;
605 	osc->startup_usec = 1200000;
606 	osc->bits = &at91sama5d4_bits;
607 
608 	ret = clk_hw_register(NULL, &osc->hw);
609 	if (ret)
610 		goto free_slow_osc_data;
611 
612 	slowck = at91_clk_register_sam9x5_slow(regbase, "slowck",
613 					       parent_names, 2,
614 					       &at91sama5d4_bits);
615 	if (IS_ERR(slowck))
616 		goto unregister_slow_osc;
617 
618 	ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, slowck);
619 	if (WARN_ON(ret))
620 		goto unregister_slowck;
621 
622 	return;
623 
624 unregister_slowck:
625 	at91_clk_unregister_sam9x5_slow(slowck);
626 unregister_slow_osc:
627 	clk_hw_unregister(&osc->hw);
628 free_slow_osc_data:
629 	kfree(osc);
630 unregister_slow_rc:
631 	clk_hw_unregister(slow_rc);
632 }
633 CLK_OF_DECLARE(sama5d4_clk_sckc, "atmel,sama5d4-sckc",
634 	       of_sama5d4_sckc_setup);
635