1cb783bbbSClaudiu Beznea // SPDX-License-Identifier: GPL-2.0 2cb783bbbSClaudiu Beznea /* 3cb783bbbSClaudiu Beznea * SAMA7G5 PMC code. 4cb783bbbSClaudiu Beznea * 5cb783bbbSClaudiu Beznea * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries 6cb783bbbSClaudiu Beznea * 7cb783bbbSClaudiu Beznea * Author: Claudiu Beznea <claudiu.beznea@microchip.com> 8cb783bbbSClaudiu Beznea * 9cb783bbbSClaudiu Beznea */ 10cb783bbbSClaudiu Beznea #include <linux/clk.h> 11cb783bbbSClaudiu Beznea #include <linux/clk-provider.h> 12cb783bbbSClaudiu Beznea #include <linux/mfd/syscon.h> 13cb783bbbSClaudiu Beznea #include <linux/slab.h> 14cb783bbbSClaudiu Beznea 15cb783bbbSClaudiu Beznea #include <dt-bindings/clock/at91.h> 16cb783bbbSClaudiu Beznea 17cb783bbbSClaudiu Beznea #include "pmc.h" 18cb783bbbSClaudiu Beznea 19cb783bbbSClaudiu Beznea #define SAMA7G5_INIT_TABLE(_table, _count) \ 20cb783bbbSClaudiu Beznea do { \ 21cb783bbbSClaudiu Beznea u8 _i; \ 22cb783bbbSClaudiu Beznea for (_i = 0; _i < (_count); _i++) \ 23cb783bbbSClaudiu Beznea (_table)[_i] = _i; \ 24cb783bbbSClaudiu Beznea } while (0) 25cb783bbbSClaudiu Beznea 26cb783bbbSClaudiu Beznea #define SAMA7G5_FILL_TABLE(_to, _from, _count) \ 27cb783bbbSClaudiu Beznea do { \ 28cb783bbbSClaudiu Beznea u8 _i; \ 29cb783bbbSClaudiu Beznea for (_i = 0; _i < (_count); _i++) { \ 30cb783bbbSClaudiu Beznea (_to)[_i] = (_from)[_i]; \ 31cb783bbbSClaudiu Beznea } \ 32cb783bbbSClaudiu Beznea } while (0) 33cb783bbbSClaudiu Beznea 34cb783bbbSClaudiu Beznea static DEFINE_SPINLOCK(pmc_pll_lock); 357a110b91SClaudiu Beznea static DEFINE_SPINLOCK(pmc_mck0_lock); 36cb783bbbSClaudiu Beznea static DEFINE_SPINLOCK(pmc_mckX_lock); 37cb783bbbSClaudiu Beznea 38a3ef91f5SRandy Dunlap /* 39cb783bbbSClaudiu Beznea * PLL clocks identifiers 40cb783bbbSClaudiu Beznea * @PLL_ID_CPU: CPU PLL identifier 41cb783bbbSClaudiu Beznea * @PLL_ID_SYS: System PLL identifier 42cb783bbbSClaudiu Beznea * @PLL_ID_DDR: DDR PLL identifier 43cb783bbbSClaudiu Beznea * @PLL_ID_IMG: Image subsystem PLL identifier 44cb783bbbSClaudiu Beznea * @PLL_ID_BAUD: Baud PLL identifier 45cb783bbbSClaudiu Beznea * @PLL_ID_AUDIO: Audio PLL identifier 46cb783bbbSClaudiu Beznea * @PLL_ID_ETH: Ethernet PLL identifier 47cb783bbbSClaudiu Beznea */ 48cb783bbbSClaudiu Beznea enum pll_ids { 49cb783bbbSClaudiu Beznea PLL_ID_CPU, 50cb783bbbSClaudiu Beznea PLL_ID_SYS, 51cb783bbbSClaudiu Beznea PLL_ID_DDR, 52cb783bbbSClaudiu Beznea PLL_ID_IMG, 53cb783bbbSClaudiu Beznea PLL_ID_BAUD, 54cb783bbbSClaudiu Beznea PLL_ID_AUDIO, 55cb783bbbSClaudiu Beznea PLL_ID_ETH, 56cb783bbbSClaudiu Beznea PLL_ID_MAX, 57cb783bbbSClaudiu Beznea }; 58cb783bbbSClaudiu Beznea 59a3ef91f5SRandy Dunlap /* 60cb783bbbSClaudiu Beznea * PLL type identifiers 61cb783bbbSClaudiu Beznea * @PLL_TYPE_FRAC: fractional PLL identifier 62cb783bbbSClaudiu Beznea * @PLL_TYPE_DIV: divider PLL identifier 63cb783bbbSClaudiu Beznea */ 64cb783bbbSClaudiu Beznea enum pll_type { 65cb783bbbSClaudiu Beznea PLL_TYPE_FRAC, 66cb783bbbSClaudiu Beznea PLL_TYPE_DIV, 67cb783bbbSClaudiu Beznea }; 68cb783bbbSClaudiu Beznea 69cb783bbbSClaudiu Beznea /* Layout for fractional PLLs. */ 70cb783bbbSClaudiu Beznea static const struct clk_pll_layout pll_layout_frac = { 71cb783bbbSClaudiu Beznea .mul_mask = GENMASK(31, 24), 72cb783bbbSClaudiu Beznea .frac_mask = GENMASK(21, 0), 73cb783bbbSClaudiu Beznea .mul_shift = 24, 74cb783bbbSClaudiu Beznea .frac_shift = 0, 75cb783bbbSClaudiu Beznea }; 76cb783bbbSClaudiu Beznea 77cb783bbbSClaudiu Beznea /* Layout for DIVPMC dividers. */ 78cb783bbbSClaudiu Beznea static const struct clk_pll_layout pll_layout_divpmc = { 79cb783bbbSClaudiu Beznea .div_mask = GENMASK(7, 0), 80cb783bbbSClaudiu Beznea .endiv_mask = BIT(29), 81cb783bbbSClaudiu Beznea .div_shift = 0, 82cb783bbbSClaudiu Beznea .endiv_shift = 29, 83cb783bbbSClaudiu Beznea }; 84cb783bbbSClaudiu Beznea 85cb783bbbSClaudiu Beznea /* Layout for DIVIO dividers. */ 86cb783bbbSClaudiu Beznea static const struct clk_pll_layout pll_layout_divio = { 87cb783bbbSClaudiu Beznea .div_mask = GENMASK(19, 12), 88cb783bbbSClaudiu Beznea .endiv_mask = BIT(30), 89cb783bbbSClaudiu Beznea .div_shift = 12, 90cb783bbbSClaudiu Beznea .endiv_shift = 30, 91cb783bbbSClaudiu Beznea }; 92cb783bbbSClaudiu Beznea 93120d5d8bSClaudiu Beznea /* 94120d5d8bSClaudiu Beznea * CPU PLL output range. 95120d5d8bSClaudiu Beznea * Notice: The upper limit has been setup to 1000000002 due to hardware 96120d5d8bSClaudiu Beznea * block which cannot output exactly 1GHz. 97120d5d8bSClaudiu Beznea */ 98120d5d8bSClaudiu Beznea static const struct clk_range cpu_pll_outputs[] = { 99120d5d8bSClaudiu Beznea { .min = 2343750, .max = 1000000002 }, 100120d5d8bSClaudiu Beznea }; 101120d5d8bSClaudiu Beznea 102120d5d8bSClaudiu Beznea /* PLL output range. */ 103120d5d8bSClaudiu Beznea static const struct clk_range pll_outputs[] = { 104120d5d8bSClaudiu Beznea { .min = 2343750, .max = 1200000000 }, 105120d5d8bSClaudiu Beznea }; 106120d5d8bSClaudiu Beznea 107120d5d8bSClaudiu Beznea /* CPU PLL characteristics. */ 108120d5d8bSClaudiu Beznea static const struct clk_pll_characteristics cpu_pll_characteristics = { 109120d5d8bSClaudiu Beznea .input = { .min = 12000000, .max = 50000000 }, 110120d5d8bSClaudiu Beznea .num_output = ARRAY_SIZE(cpu_pll_outputs), 111120d5d8bSClaudiu Beznea .output = cpu_pll_outputs, 112120d5d8bSClaudiu Beznea }; 113120d5d8bSClaudiu Beznea 114120d5d8bSClaudiu Beznea /* PLL characteristics. */ 115120d5d8bSClaudiu Beznea static const struct clk_pll_characteristics pll_characteristics = { 116120d5d8bSClaudiu Beznea .input = { .min = 12000000, .max = 50000000 }, 117120d5d8bSClaudiu Beznea .num_output = ARRAY_SIZE(pll_outputs), 118120d5d8bSClaudiu Beznea .output = pll_outputs, 119120d5d8bSClaudiu Beznea }; 120120d5d8bSClaudiu Beznea 121a3ef91f5SRandy Dunlap /* 122cb783bbbSClaudiu Beznea * PLL clocks description 123cb783bbbSClaudiu Beznea * @n: clock name 124cb783bbbSClaudiu Beznea * @p: clock parent 125cb783bbbSClaudiu Beznea * @l: clock layout 126120d5d8bSClaudiu Beznea * @c: clock characteristics 127cb783bbbSClaudiu Beznea * @t: clock type 1288dc4af8bSClaudiu Beznea * @f: clock flags 129cb783bbbSClaudiu Beznea * @eid: export index in sama7g5->chws[] array 1301e229c21SClaudiu Beznea * @safe_div: intermediate divider need to be set on PRE_RATE_CHANGE 1311e229c21SClaudiu Beznea * notification 132cb783bbbSClaudiu Beznea */ 133cb783bbbSClaudiu Beznea static const struct { 134cb783bbbSClaudiu Beznea const char *n; 135cb783bbbSClaudiu Beznea const char *p; 136cb783bbbSClaudiu Beznea const struct clk_pll_layout *l; 137120d5d8bSClaudiu Beznea const struct clk_pll_characteristics *c; 1388dc4af8bSClaudiu Beznea unsigned long f; 139cb783bbbSClaudiu Beznea u8 t; 140cb783bbbSClaudiu Beznea u8 eid; 1411e229c21SClaudiu Beznea u8 safe_div; 142cb783bbbSClaudiu Beznea } sama7g5_plls[][PLL_ID_MAX] = { 143cb783bbbSClaudiu Beznea [PLL_ID_CPU] = { 144cb783bbbSClaudiu Beznea { .n = "cpupll_fracck", 145cb783bbbSClaudiu Beznea .p = "mainck", 146cb783bbbSClaudiu Beznea .l = &pll_layout_frac, 147120d5d8bSClaudiu Beznea .c = &cpu_pll_characteristics, 148cb783bbbSClaudiu Beznea .t = PLL_TYPE_FRAC, 1498dc4af8bSClaudiu Beznea /* 1508dc4af8bSClaudiu Beznea * This feeds cpupll_divpmcck which feeds CPU. It should 1518dc4af8bSClaudiu Beznea * not be disabled. 1528dc4af8bSClaudiu Beznea */ 1538dc4af8bSClaudiu Beznea .f = CLK_IS_CRITICAL, }, 154cb783bbbSClaudiu Beznea 155cb783bbbSClaudiu Beznea { .n = "cpupll_divpmcck", 156cb783bbbSClaudiu Beznea .p = "cpupll_fracck", 157cb783bbbSClaudiu Beznea .l = &pll_layout_divpmc, 158120d5d8bSClaudiu Beznea .c = &cpu_pll_characteristics, 159cb783bbbSClaudiu Beznea .t = PLL_TYPE_DIV, 1608dc4af8bSClaudiu Beznea /* This feeds CPU. It should not be disabled. */ 1618dc4af8bSClaudiu Beznea .f = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 1621e229c21SClaudiu Beznea .eid = PMC_CPUPLL, 1631e229c21SClaudiu Beznea /* 1641e229c21SClaudiu Beznea * Safe div=15 should be safe even for switching b/w 1GHz and 1651e229c21SClaudiu Beznea * 90MHz (frac pll might go up to 1.2GHz). 1661e229c21SClaudiu Beznea */ 1671e229c21SClaudiu Beznea .safe_div = 15, }, 168cb783bbbSClaudiu Beznea }, 169cb783bbbSClaudiu Beznea 170cb783bbbSClaudiu Beznea [PLL_ID_SYS] = { 171cb783bbbSClaudiu Beznea { .n = "syspll_fracck", 172cb783bbbSClaudiu Beznea .p = "mainck", 173cb783bbbSClaudiu Beznea .l = &pll_layout_frac, 174120d5d8bSClaudiu Beznea .c = &pll_characteristics, 175cb783bbbSClaudiu Beznea .t = PLL_TYPE_FRAC, 1768dc4af8bSClaudiu Beznea /* 1777996dfd6SBhaskar Chowdhury * This feeds syspll_divpmcck which may feed critical parts 1788dc4af8bSClaudiu Beznea * of the systems like timers. Therefore it should not be 1798dc4af8bSClaudiu Beznea * disabled. 1808dc4af8bSClaudiu Beznea */ 1818dc4af8bSClaudiu Beznea .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, }, 182cb783bbbSClaudiu Beznea 183cb783bbbSClaudiu Beznea { .n = "syspll_divpmcck", 184cb783bbbSClaudiu Beznea .p = "syspll_fracck", 185cb783bbbSClaudiu Beznea .l = &pll_layout_divpmc, 186120d5d8bSClaudiu Beznea .c = &pll_characteristics, 187cb783bbbSClaudiu Beznea .t = PLL_TYPE_DIV, 1888dc4af8bSClaudiu Beznea /* 1897996dfd6SBhaskar Chowdhury * This may feed critical parts of the systems like timers. 1908dc4af8bSClaudiu Beznea * Therefore it should not be disabled. 1918dc4af8bSClaudiu Beznea */ 1928dc4af8bSClaudiu Beznea .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, 19383d00287SEugen Hristev .eid = PMC_SYSPLL, }, 194cb783bbbSClaudiu Beznea }, 195cb783bbbSClaudiu Beznea 196cb783bbbSClaudiu Beznea [PLL_ID_DDR] = { 197cb783bbbSClaudiu Beznea { .n = "ddrpll_fracck", 198cb783bbbSClaudiu Beznea .p = "mainck", 199cb783bbbSClaudiu Beznea .l = &pll_layout_frac, 200120d5d8bSClaudiu Beznea .c = &pll_characteristics, 201cb783bbbSClaudiu Beznea .t = PLL_TYPE_FRAC, 2028dc4af8bSClaudiu Beznea /* 2038dc4af8bSClaudiu Beznea * This feeds ddrpll_divpmcck which feeds DDR. It should not 2048dc4af8bSClaudiu Beznea * be disabled. 2058dc4af8bSClaudiu Beznea */ 2068dc4af8bSClaudiu Beznea .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, }, 207cb783bbbSClaudiu Beznea 208cb783bbbSClaudiu Beznea { .n = "ddrpll_divpmcck", 209cb783bbbSClaudiu Beznea .p = "ddrpll_fracck", 210cb783bbbSClaudiu Beznea .l = &pll_layout_divpmc, 211120d5d8bSClaudiu Beznea .c = &pll_characteristics, 212cb783bbbSClaudiu Beznea .t = PLL_TYPE_DIV, 2138dc4af8bSClaudiu Beznea /* This feeds DDR. It should not be disabled. */ 2148dc4af8bSClaudiu Beznea .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, }, 215cb783bbbSClaudiu Beznea }, 216cb783bbbSClaudiu Beznea 217cb783bbbSClaudiu Beznea [PLL_ID_IMG] = { 218cb783bbbSClaudiu Beznea { .n = "imgpll_fracck", 219cb783bbbSClaudiu Beznea .p = "mainck", 220cb783bbbSClaudiu Beznea .l = &pll_layout_frac, 221120d5d8bSClaudiu Beznea .c = &pll_characteristics, 2228dc4af8bSClaudiu Beznea .t = PLL_TYPE_FRAC, 2238dc4af8bSClaudiu Beznea .f = CLK_SET_RATE_GATE, }, 224cb783bbbSClaudiu Beznea 225cb783bbbSClaudiu Beznea { .n = "imgpll_divpmcck", 226cb783bbbSClaudiu Beznea .p = "imgpll_fracck", 227cb783bbbSClaudiu Beznea .l = &pll_layout_divpmc, 228120d5d8bSClaudiu Beznea .c = &pll_characteristics, 2298dc4af8bSClaudiu Beznea .t = PLL_TYPE_DIV, 2308dc4af8bSClaudiu Beznea .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | 2318dc4af8bSClaudiu Beznea CLK_SET_RATE_PARENT, }, 232cb783bbbSClaudiu Beznea }, 233cb783bbbSClaudiu Beznea 234cb783bbbSClaudiu Beznea [PLL_ID_BAUD] = { 235cb783bbbSClaudiu Beznea { .n = "baudpll_fracck", 236cb783bbbSClaudiu Beznea .p = "mainck", 237cb783bbbSClaudiu Beznea .l = &pll_layout_frac, 238120d5d8bSClaudiu Beznea .c = &pll_characteristics, 2398dc4af8bSClaudiu Beznea .t = PLL_TYPE_FRAC, 2408dc4af8bSClaudiu Beznea .f = CLK_SET_RATE_GATE, }, 241cb783bbbSClaudiu Beznea 242cb783bbbSClaudiu Beznea { .n = "baudpll_divpmcck", 243cb783bbbSClaudiu Beznea .p = "baudpll_fracck", 244cb783bbbSClaudiu Beznea .l = &pll_layout_divpmc, 245120d5d8bSClaudiu Beznea .c = &pll_characteristics, 2468dc4af8bSClaudiu Beznea .t = PLL_TYPE_DIV, 2478dc4af8bSClaudiu Beznea .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | 2488dc4af8bSClaudiu Beznea CLK_SET_RATE_PARENT, }, 249cb783bbbSClaudiu Beznea }, 250cb783bbbSClaudiu Beznea 251cb783bbbSClaudiu Beznea [PLL_ID_AUDIO] = { 252cb783bbbSClaudiu Beznea { .n = "audiopll_fracck", 253cb783bbbSClaudiu Beznea .p = "main_xtal", 254cb783bbbSClaudiu Beznea .l = &pll_layout_frac, 255120d5d8bSClaudiu Beznea .c = &pll_characteristics, 2568dc4af8bSClaudiu Beznea .t = PLL_TYPE_FRAC, 2578dc4af8bSClaudiu Beznea .f = CLK_SET_RATE_GATE, }, 258cb783bbbSClaudiu Beznea 259cb783bbbSClaudiu Beznea { .n = "audiopll_divpmcck", 260cb783bbbSClaudiu Beznea .p = "audiopll_fracck", 261cb783bbbSClaudiu Beznea .l = &pll_layout_divpmc, 262120d5d8bSClaudiu Beznea .c = &pll_characteristics, 263cb783bbbSClaudiu Beznea .t = PLL_TYPE_DIV, 2648dc4af8bSClaudiu Beznea .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | 2658dc4af8bSClaudiu Beznea CLK_SET_RATE_PARENT, 2663d86ee17SEugen Hristev .eid = PMC_AUDIOPMCPLL, }, 267cb783bbbSClaudiu Beznea 268cb783bbbSClaudiu Beznea { .n = "audiopll_diviock", 269cb783bbbSClaudiu Beznea .p = "audiopll_fracck", 270cb783bbbSClaudiu Beznea .l = &pll_layout_divio, 271120d5d8bSClaudiu Beznea .c = &pll_characteristics, 272cb783bbbSClaudiu Beznea .t = PLL_TYPE_DIV, 2738dc4af8bSClaudiu Beznea .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | 2748dc4af8bSClaudiu Beznea CLK_SET_RATE_PARENT, 2753d86ee17SEugen Hristev .eid = PMC_AUDIOIOPLL, }, 276cb783bbbSClaudiu Beznea }, 277cb783bbbSClaudiu Beznea 278cb783bbbSClaudiu Beznea [PLL_ID_ETH] = { 279cb783bbbSClaudiu Beznea { .n = "ethpll_fracck", 280cb783bbbSClaudiu Beznea .p = "main_xtal", 281cb783bbbSClaudiu Beznea .l = &pll_layout_frac, 282120d5d8bSClaudiu Beznea .c = &pll_characteristics, 2838dc4af8bSClaudiu Beznea .t = PLL_TYPE_FRAC, 2848dc4af8bSClaudiu Beznea .f = CLK_SET_RATE_GATE, }, 285cb783bbbSClaudiu Beznea 286cb783bbbSClaudiu Beznea { .n = "ethpll_divpmcck", 287cb783bbbSClaudiu Beznea .p = "ethpll_fracck", 288cb783bbbSClaudiu Beznea .l = &pll_layout_divpmc, 289120d5d8bSClaudiu Beznea .c = &pll_characteristics, 2908dc4af8bSClaudiu Beznea .t = PLL_TYPE_DIV, 2918dc4af8bSClaudiu Beznea .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | 2928dc4af8bSClaudiu Beznea CLK_SET_RATE_PARENT, }, 293cb783bbbSClaudiu Beznea }, 294cb783bbbSClaudiu Beznea }; 295cb783bbbSClaudiu Beznea 296a3ef91f5SRandy Dunlap /* 297cb783bbbSClaudiu Beznea * Master clock (MCK[1..4]) description 298cb783bbbSClaudiu Beznea * @n: clock name 299cb783bbbSClaudiu Beznea * @ep: extra parents names array 300cb783bbbSClaudiu Beznea * @ep_chg_chg_id: index in parents array that specifies the changeable 301cb783bbbSClaudiu Beznea * parent 302cb783bbbSClaudiu Beznea * @ep_count: extra parents count 303cb783bbbSClaudiu Beznea * @ep_mux_table: mux table for extra parents 304cb783bbbSClaudiu Beznea * @id: clock id 305cb783bbbSClaudiu Beznea * @c: true if clock is critical and cannot be disabled 306cb783bbbSClaudiu Beznea */ 307cb783bbbSClaudiu Beznea static const struct { 308cb783bbbSClaudiu Beznea const char *n; 309cb783bbbSClaudiu Beznea const char *ep[4]; 310cb783bbbSClaudiu Beznea int ep_chg_id; 311cb783bbbSClaudiu Beznea u8 ep_count; 312cb783bbbSClaudiu Beznea u8 ep_mux_table[4]; 313cb783bbbSClaudiu Beznea u8 id; 314cb783bbbSClaudiu Beznea u8 c; 315cb783bbbSClaudiu Beznea } sama7g5_mckx[] = { 316cb783bbbSClaudiu Beznea { .n = "mck1", 317cb783bbbSClaudiu Beznea .id = 1, 318cb783bbbSClaudiu Beznea .ep = { "syspll_divpmcck", }, 319cb783bbbSClaudiu Beznea .ep_mux_table = { 5, }, 320cb783bbbSClaudiu Beznea .ep_count = 1, 321cb783bbbSClaudiu Beznea .ep_chg_id = INT_MIN, 322cb783bbbSClaudiu Beznea .c = 1, }, 323cb783bbbSClaudiu Beznea 324cb783bbbSClaudiu Beznea { .n = "mck2", 325cb783bbbSClaudiu Beznea .id = 2, 326cb783bbbSClaudiu Beznea .ep = { "ddrpll_divpmcck", }, 327cb783bbbSClaudiu Beznea .ep_mux_table = { 6, }, 328cb783bbbSClaudiu Beznea .ep_count = 1, 329cb783bbbSClaudiu Beznea .ep_chg_id = INT_MIN, 330cb783bbbSClaudiu Beznea .c = 1, }, 331cb783bbbSClaudiu Beznea 332cb783bbbSClaudiu Beznea { .n = "mck3", 333cb783bbbSClaudiu Beznea .id = 3, 334cb783bbbSClaudiu Beznea .ep = { "syspll_divpmcck", "ddrpll_divpmcck", "imgpll_divpmcck", }, 335cb783bbbSClaudiu Beznea .ep_mux_table = { 5, 6, 7, }, 336cb783bbbSClaudiu Beznea .ep_count = 3, 3374011f03eSClaudiu Beznea .ep_chg_id = 5, }, 338cb783bbbSClaudiu Beznea 339cb783bbbSClaudiu Beznea { .n = "mck4", 340cb783bbbSClaudiu Beznea .id = 4, 341cb783bbbSClaudiu Beznea .ep = { "syspll_divpmcck", }, 342cb783bbbSClaudiu Beznea .ep_mux_table = { 5, }, 343cb783bbbSClaudiu Beznea .ep_count = 1, 344cb783bbbSClaudiu Beznea .ep_chg_id = INT_MIN, 345cb783bbbSClaudiu Beznea .c = 1, }, 346cb783bbbSClaudiu Beznea }; 347cb783bbbSClaudiu Beznea 348a3ef91f5SRandy Dunlap /* 349cb783bbbSClaudiu Beznea * System clock description 350cb783bbbSClaudiu Beznea * @n: clock name 351cb783bbbSClaudiu Beznea * @p: clock parent name 352cb783bbbSClaudiu Beznea * @id: clock id 353cb783bbbSClaudiu Beznea */ 354cb783bbbSClaudiu Beznea static const struct { 355cb783bbbSClaudiu Beznea const char *n; 356cb783bbbSClaudiu Beznea const char *p; 357cb783bbbSClaudiu Beznea u8 id; 358cb783bbbSClaudiu Beznea } sama7g5_systemck[] = { 359cb783bbbSClaudiu Beznea { .n = "pck0", .p = "prog0", .id = 8, }, 360cb783bbbSClaudiu Beznea { .n = "pck1", .p = "prog1", .id = 9, }, 361cb783bbbSClaudiu Beznea { .n = "pck2", .p = "prog2", .id = 10, }, 362cb783bbbSClaudiu Beznea { .n = "pck3", .p = "prog3", .id = 11, }, 363cb783bbbSClaudiu Beznea { .n = "pck4", .p = "prog4", .id = 12, }, 364cb783bbbSClaudiu Beznea { .n = "pck5", .p = "prog5", .id = 13, }, 365cb783bbbSClaudiu Beznea { .n = "pck6", .p = "prog6", .id = 14, }, 366cb783bbbSClaudiu Beznea { .n = "pck7", .p = "prog7", .id = 15, }, 367cb783bbbSClaudiu Beznea }; 368cb783bbbSClaudiu Beznea 369cb783bbbSClaudiu Beznea /* Mux table for programmable clocks. */ 3704011f03eSClaudiu Beznea static u32 sama7g5_prog_mux_table[] = { 0, 1, 2, 5, 6, 7, 8, 9, 10, }; 371cb783bbbSClaudiu Beznea 372a3ef91f5SRandy Dunlap /* 373cb783bbbSClaudiu Beznea * Peripheral clock description 374cb783bbbSClaudiu Beznea * @n: clock name 375cb783bbbSClaudiu Beznea * @p: clock parent name 376cb783bbbSClaudiu Beznea * @r: clock range values 377cb783bbbSClaudiu Beznea * @id: clock id 378cb783bbbSClaudiu Beznea * @chgp: index in parent array of the changeable parent 379cb783bbbSClaudiu Beznea */ 380cb783bbbSClaudiu Beznea static const struct { 381cb783bbbSClaudiu Beznea const char *n; 382cb783bbbSClaudiu Beznea const char *p; 383cb783bbbSClaudiu Beznea struct clk_range r; 384cb783bbbSClaudiu Beznea u8 chgp; 385cb783bbbSClaudiu Beznea u8 id; 386cb783bbbSClaudiu Beznea } sama7g5_periphck[] = { 387cb783bbbSClaudiu Beznea { .n = "pioA_clk", .p = "mck0", .id = 11, }, 388c884c7a0SClaudiu Beznea { .n = "securam_clk", .p = "mck0", .id = 18, }, 389cb783bbbSClaudiu Beznea { .n = "sfr_clk", .p = "mck1", .id = 19, }, 390cb783bbbSClaudiu Beznea { .n = "hsmc_clk", .p = "mck1", .id = 21, }, 391cb783bbbSClaudiu Beznea { .n = "xdmac0_clk", .p = "mck1", .id = 22, }, 392cb783bbbSClaudiu Beznea { .n = "xdmac1_clk", .p = "mck1", .id = 23, }, 393cb783bbbSClaudiu Beznea { .n = "xdmac2_clk", .p = "mck1", .id = 24, }, 394cb783bbbSClaudiu Beznea { .n = "acc_clk", .p = "mck1", .id = 25, }, 395cb783bbbSClaudiu Beznea { .n = "aes_clk", .p = "mck1", .id = 27, }, 396cb783bbbSClaudiu Beznea { .n = "tzaesbasc_clk", .p = "mck1", .id = 28, }, 397cb783bbbSClaudiu Beznea { .n = "asrc_clk", .p = "mck1", .id = 30, .r = { .max = 200000000, }, }, 398cb783bbbSClaudiu Beznea { .n = "cpkcc_clk", .p = "mck0", .id = 32, }, 399cb783bbbSClaudiu Beznea { .n = "csi_clk", .p = "mck3", .id = 33, .r = { .max = 266000000, }, .chgp = 1, }, 400cb783bbbSClaudiu Beznea { .n = "csi2dc_clk", .p = "mck3", .id = 34, .r = { .max = 266000000, }, .chgp = 1, }, 401cb783bbbSClaudiu Beznea { .n = "eic_clk", .p = "mck1", .id = 37, }, 402cb783bbbSClaudiu Beznea { .n = "flex0_clk", .p = "mck1", .id = 38, }, 403cb783bbbSClaudiu Beznea { .n = "flex1_clk", .p = "mck1", .id = 39, }, 404cb783bbbSClaudiu Beznea { .n = "flex2_clk", .p = "mck1", .id = 40, }, 405cb783bbbSClaudiu Beznea { .n = "flex3_clk", .p = "mck1", .id = 41, }, 406cb783bbbSClaudiu Beznea { .n = "flex4_clk", .p = "mck1", .id = 42, }, 407cb783bbbSClaudiu Beznea { .n = "flex5_clk", .p = "mck1", .id = 43, }, 408cb783bbbSClaudiu Beznea { .n = "flex6_clk", .p = "mck1", .id = 44, }, 409cb783bbbSClaudiu Beznea { .n = "flex7_clk", .p = "mck1", .id = 45, }, 410cb783bbbSClaudiu Beznea { .n = "flex8_clk", .p = "mck1", .id = 46, }, 411cb783bbbSClaudiu Beznea { .n = "flex9_clk", .p = "mck1", .id = 47, }, 412cb783bbbSClaudiu Beznea { .n = "flex10_clk", .p = "mck1", .id = 48, }, 413cb783bbbSClaudiu Beznea { .n = "flex11_clk", .p = "mck1", .id = 49, }, 414cb783bbbSClaudiu Beznea { .n = "gmac0_clk", .p = "mck1", .id = 51, }, 415cb783bbbSClaudiu Beznea { .n = "gmac1_clk", .p = "mck1", .id = 52, }, 416cb783bbbSClaudiu Beznea { .n = "icm_clk", .p = "mck1", .id = 55, }, 417cb783bbbSClaudiu Beznea { .n = "isc_clk", .p = "mck3", .id = 56, .r = { .max = 266000000, }, .chgp = 1, }, 418cb783bbbSClaudiu Beznea { .n = "i2smcc0_clk", .p = "mck1", .id = 57, .r = { .max = 200000000, }, }, 419cb783bbbSClaudiu Beznea { .n = "i2smcc1_clk", .p = "mck1", .id = 58, .r = { .max = 200000000, }, }, 420cb783bbbSClaudiu Beznea { .n = "matrix_clk", .p = "mck1", .id = 60, }, 421cb783bbbSClaudiu Beznea { .n = "mcan0_clk", .p = "mck1", .id = 61, .r = { .max = 200000000, }, }, 422cb783bbbSClaudiu Beznea { .n = "mcan1_clk", .p = "mck1", .id = 62, .r = { .max = 200000000, }, }, 423cb783bbbSClaudiu Beznea { .n = "mcan2_clk", .p = "mck1", .id = 63, .r = { .max = 200000000, }, }, 424cb783bbbSClaudiu Beznea { .n = "mcan3_clk", .p = "mck1", .id = 64, .r = { .max = 200000000, }, }, 425cb783bbbSClaudiu Beznea { .n = "mcan4_clk", .p = "mck1", .id = 65, .r = { .max = 200000000, }, }, 426cb783bbbSClaudiu Beznea { .n = "mcan5_clk", .p = "mck1", .id = 66, .r = { .max = 200000000, }, }, 427cb783bbbSClaudiu Beznea { .n = "pdmc0_clk", .p = "mck1", .id = 68, .r = { .max = 200000000, }, }, 428cb783bbbSClaudiu Beznea { .n = "pdmc1_clk", .p = "mck1", .id = 69, .r = { .max = 200000000, }, }, 429cb783bbbSClaudiu Beznea { .n = "pit64b0_clk", .p = "mck1", .id = 70, }, 430cb783bbbSClaudiu Beznea { .n = "pit64b1_clk", .p = "mck1", .id = 71, }, 431cb783bbbSClaudiu Beznea { .n = "pit64b2_clk", .p = "mck1", .id = 72, }, 432cb783bbbSClaudiu Beznea { .n = "pit64b3_clk", .p = "mck1", .id = 73, }, 433cb783bbbSClaudiu Beznea { .n = "pit64b4_clk", .p = "mck1", .id = 74, }, 434cb783bbbSClaudiu Beznea { .n = "pit64b5_clk", .p = "mck1", .id = 75, }, 435cb783bbbSClaudiu Beznea { .n = "pwm_clk", .p = "mck1", .id = 77, }, 436cb783bbbSClaudiu Beznea { .n = "qspi0_clk", .p = "mck1", .id = 78, }, 437cb783bbbSClaudiu Beznea { .n = "qspi1_clk", .p = "mck1", .id = 79, }, 438cb783bbbSClaudiu Beznea { .n = "sdmmc0_clk", .p = "mck1", .id = 80, }, 439cb783bbbSClaudiu Beznea { .n = "sdmmc1_clk", .p = "mck1", .id = 81, }, 440cb783bbbSClaudiu Beznea { .n = "sdmmc2_clk", .p = "mck1", .id = 82, }, 441cb783bbbSClaudiu Beznea { .n = "sha_clk", .p = "mck1", .id = 83, }, 442cb783bbbSClaudiu Beznea { .n = "spdifrx_clk", .p = "mck1", .id = 84, .r = { .max = 200000000, }, }, 443cb783bbbSClaudiu Beznea { .n = "spdiftx_clk", .p = "mck1", .id = 85, .r = { .max = 200000000, }, }, 444cb783bbbSClaudiu Beznea { .n = "ssc0_clk", .p = "mck1", .id = 86, .r = { .max = 200000000, }, }, 445cb783bbbSClaudiu Beznea { .n = "ssc1_clk", .p = "mck1", .id = 87, .r = { .max = 200000000, }, }, 446cb783bbbSClaudiu Beznea { .n = "tcb0_ch0_clk", .p = "mck1", .id = 88, .r = { .max = 200000000, }, }, 447cb783bbbSClaudiu Beznea { .n = "tcb0_ch1_clk", .p = "mck1", .id = 89, .r = { .max = 200000000, }, }, 448cb783bbbSClaudiu Beznea { .n = "tcb0_ch2_clk", .p = "mck1", .id = 90, .r = { .max = 200000000, }, }, 449cb783bbbSClaudiu Beznea { .n = "tcb1_ch0_clk", .p = "mck1", .id = 91, .r = { .max = 200000000, }, }, 450cb783bbbSClaudiu Beznea { .n = "tcb1_ch1_clk", .p = "mck1", .id = 92, .r = { .max = 200000000, }, }, 451cb783bbbSClaudiu Beznea { .n = "tcb1_ch2_clk", .p = "mck1", .id = 93, .r = { .max = 200000000, }, }, 452cb783bbbSClaudiu Beznea { .n = "tcpca_clk", .p = "mck1", .id = 94, }, 453cb783bbbSClaudiu Beznea { .n = "tcpcb_clk", .p = "mck1", .id = 95, }, 454cb783bbbSClaudiu Beznea { .n = "tdes_clk", .p = "mck1", .id = 96, }, 455cb783bbbSClaudiu Beznea { .n = "trng_clk", .p = "mck1", .id = 97, }, 456cb783bbbSClaudiu Beznea { .n = "udphsa_clk", .p = "mck1", .id = 104, }, 457cb783bbbSClaudiu Beznea { .n = "udphsb_clk", .p = "mck1", .id = 105, }, 458cb783bbbSClaudiu Beznea { .n = "uhphs_clk", .p = "mck1", .id = 106, }, 459cb783bbbSClaudiu Beznea }; 460cb783bbbSClaudiu Beznea 461a3ef91f5SRandy Dunlap /* 462cb783bbbSClaudiu Beznea * Generic clock description 463cb783bbbSClaudiu Beznea * @n: clock name 464cb783bbbSClaudiu Beznea * @pp: PLL parents 465cb783bbbSClaudiu Beznea * @pp_mux_table: PLL parents mux table 466cb783bbbSClaudiu Beznea * @r: clock output range 4677996dfd6SBhaskar Chowdhury * @pp_chg_id: id in parent array of changeable PLL parent 468cb783bbbSClaudiu Beznea * @pp_count: PLL parents count 469cb783bbbSClaudiu Beznea * @id: clock id 470cb783bbbSClaudiu Beznea */ 471cb783bbbSClaudiu Beznea static const struct { 472cb783bbbSClaudiu Beznea const char *n; 473cb783bbbSClaudiu Beznea const char *pp[8]; 474cb783bbbSClaudiu Beznea const char pp_mux_table[8]; 475cb783bbbSClaudiu Beznea struct clk_range r; 476cb783bbbSClaudiu Beznea int pp_chg_id; 477cb783bbbSClaudiu Beznea u8 pp_count; 478cb783bbbSClaudiu Beznea u8 id; 479cb783bbbSClaudiu Beznea } sama7g5_gck[] = { 480cb783bbbSClaudiu Beznea { .n = "adc_gclk", 481cb783bbbSClaudiu Beznea .id = 26, 482cb783bbbSClaudiu Beznea .r = { .max = 100000000, }, 483cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "imgpll_divpmcck", "audiopll_divpmcck", }, 484cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 7, 9, }, 485cb783bbbSClaudiu Beznea .pp_count = 3, 486cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 487cb783bbbSClaudiu Beznea 488cb783bbbSClaudiu Beznea { .n = "asrc_gclk", 489cb783bbbSClaudiu Beznea .id = 30, 490cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 491cb783bbbSClaudiu Beznea .pp = { "audiopll_divpmcck", }, 492cb783bbbSClaudiu Beznea .pp_mux_table = { 9, }, 493cb783bbbSClaudiu Beznea .pp_count = 1, 4944011f03eSClaudiu Beznea .pp_chg_id = 3, }, 495cb783bbbSClaudiu Beznea 496cb783bbbSClaudiu Beznea { .n = "csi_gclk", 497cb783bbbSClaudiu Beznea .id = 33, 498cb783bbbSClaudiu Beznea .r = { .max = 27000000 }, 499cb783bbbSClaudiu Beznea .pp = { "ddrpll_divpmcck", "imgpll_divpmcck", }, 500cb783bbbSClaudiu Beznea .pp_mux_table = { 6, 7, }, 501cb783bbbSClaudiu Beznea .pp_count = 2, 502cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 503cb783bbbSClaudiu Beznea 504cb783bbbSClaudiu Beznea { .n = "flex0_gclk", 505cb783bbbSClaudiu Beznea .id = 38, 506cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 507cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 508cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 509cb783bbbSClaudiu Beznea .pp_count = 2, 510cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 511cb783bbbSClaudiu Beznea 512cb783bbbSClaudiu Beznea { .n = "flex1_gclk", 513cb783bbbSClaudiu Beznea .id = 39, 514cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 515cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 516cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 517cb783bbbSClaudiu Beznea .pp_count = 2, 518cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 519cb783bbbSClaudiu Beznea 520cb783bbbSClaudiu Beznea { .n = "flex2_gclk", 521cb783bbbSClaudiu Beznea .id = 40, 522cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 523cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 524cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 525cb783bbbSClaudiu Beznea .pp_count = 2, 526cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 527cb783bbbSClaudiu Beznea 528cb783bbbSClaudiu Beznea { .n = "flex3_gclk", 529cb783bbbSClaudiu Beznea .id = 41, 530cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 531cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 532cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 533cb783bbbSClaudiu Beznea .pp_count = 2, 534cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 535cb783bbbSClaudiu Beznea 536cb783bbbSClaudiu Beznea { .n = "flex4_gclk", 537cb783bbbSClaudiu Beznea .id = 42, 538cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 539cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 540cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 541cb783bbbSClaudiu Beznea .pp_count = 2, 542cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 543cb783bbbSClaudiu Beznea 544cb783bbbSClaudiu Beznea { .n = "flex5_gclk", 545cb783bbbSClaudiu Beznea .id = 43, 546cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 547cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 548cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 549cb783bbbSClaudiu Beznea .pp_count = 2, 550cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 551cb783bbbSClaudiu Beznea 552cb783bbbSClaudiu Beznea { .n = "flex6_gclk", 553cb783bbbSClaudiu Beznea .id = 44, 554cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 555cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 556cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 557cb783bbbSClaudiu Beznea .pp_count = 2, 558cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 559cb783bbbSClaudiu Beznea 560cb783bbbSClaudiu Beznea { .n = "flex7_gclk", 561cb783bbbSClaudiu Beznea .id = 45, 562cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 563cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 564cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 565cb783bbbSClaudiu Beznea .pp_count = 2, 566cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 567cb783bbbSClaudiu Beznea 568cb783bbbSClaudiu Beznea { .n = "flex8_gclk", 569cb783bbbSClaudiu Beznea .id = 46, 570cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 571cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 572cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 573cb783bbbSClaudiu Beznea .pp_count = 2, 574cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 575cb783bbbSClaudiu Beznea 576cb783bbbSClaudiu Beznea { .n = "flex9_gclk", 577cb783bbbSClaudiu Beznea .id = 47, 578cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 579cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 580cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 581cb783bbbSClaudiu Beznea .pp_count = 2, 582cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 583cb783bbbSClaudiu Beznea 584cb783bbbSClaudiu Beznea { .n = "flex10_gclk", 585cb783bbbSClaudiu Beznea .id = 48, 586cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 587cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 588cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 589cb783bbbSClaudiu Beznea .pp_count = 2, 590cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 591cb783bbbSClaudiu Beznea 592cb783bbbSClaudiu Beznea { .n = "flex11_gclk", 593cb783bbbSClaudiu Beznea .id = 49, 594cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 595cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 596cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 597cb783bbbSClaudiu Beznea .pp_count = 2, 598cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 599cb783bbbSClaudiu Beznea 600cb783bbbSClaudiu Beznea { .n = "gmac0_gclk", 601cb783bbbSClaudiu Beznea .id = 51, 602cb783bbbSClaudiu Beznea .r = { .max = 125000000 }, 603cb783bbbSClaudiu Beznea .pp = { "ethpll_divpmcck", }, 604cb783bbbSClaudiu Beznea .pp_mux_table = { 10, }, 605cb783bbbSClaudiu Beznea .pp_count = 1, 6064011f03eSClaudiu Beznea .pp_chg_id = 3, }, 607cb783bbbSClaudiu Beznea 608cb783bbbSClaudiu Beznea { .n = "gmac1_gclk", 609cb783bbbSClaudiu Beznea .id = 52, 610cb783bbbSClaudiu Beznea .r = { .max = 50000000 }, 611cb783bbbSClaudiu Beznea .pp = { "ethpll_divpmcck", }, 612cb783bbbSClaudiu Beznea .pp_mux_table = { 10, }, 613cb783bbbSClaudiu Beznea .pp_count = 1, 614cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 615cb783bbbSClaudiu Beznea 616cb783bbbSClaudiu Beznea { .n = "gmac0_tsu_gclk", 617cb783bbbSClaudiu Beznea .id = 53, 618cb783bbbSClaudiu Beznea .r = { .max = 300000000 }, 619cb783bbbSClaudiu Beznea .pp = { "audiopll_divpmcck", "ethpll_divpmcck", }, 620cb783bbbSClaudiu Beznea .pp_mux_table = { 9, 10, }, 621cb783bbbSClaudiu Beznea .pp_count = 2, 622cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 623cb783bbbSClaudiu Beznea 624cb783bbbSClaudiu Beznea { .n = "gmac1_tsu_gclk", 625cb783bbbSClaudiu Beznea .id = 54, 626cb783bbbSClaudiu Beznea .r = { .max = 300000000 }, 627cb783bbbSClaudiu Beznea .pp = { "audiopll_divpmcck", "ethpll_divpmcck", }, 628cb783bbbSClaudiu Beznea .pp_mux_table = { 9, 10, }, 629cb783bbbSClaudiu Beznea .pp_count = 2, 630cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 631cb783bbbSClaudiu Beznea 632cb783bbbSClaudiu Beznea { .n = "i2smcc0_gclk", 633cb783bbbSClaudiu Beznea .id = 57, 634cb783bbbSClaudiu Beznea .r = { .max = 100000000 }, 635cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "audiopll_divpmcck", }, 636cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 9, }, 637cb783bbbSClaudiu Beznea .pp_count = 2, 6384011f03eSClaudiu Beznea .pp_chg_id = 4, }, 639cb783bbbSClaudiu Beznea 640cb783bbbSClaudiu Beznea { .n = "i2smcc1_gclk", 641cb783bbbSClaudiu Beznea .id = 58, 642cb783bbbSClaudiu Beznea .r = { .max = 100000000 }, 643cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "audiopll_divpmcck", }, 644cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 9, }, 645cb783bbbSClaudiu Beznea .pp_count = 2, 6464011f03eSClaudiu Beznea .pp_chg_id = 4, }, 647cb783bbbSClaudiu Beznea 648cb783bbbSClaudiu Beznea { .n = "mcan0_gclk", 649cb783bbbSClaudiu Beznea .id = 61, 650cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 651cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 652cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 653cb783bbbSClaudiu Beznea .pp_count = 2, 654cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 655cb783bbbSClaudiu Beznea 656cb783bbbSClaudiu Beznea { .n = "mcan1_gclk", 657cb783bbbSClaudiu Beznea .id = 62, 658cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 659cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 660cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 661cb783bbbSClaudiu Beznea .pp_count = 2, 662cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 663cb783bbbSClaudiu Beznea 664cb783bbbSClaudiu Beznea { .n = "mcan2_gclk", 665cb783bbbSClaudiu Beznea .id = 63, 666cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 667cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 668cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 669cb783bbbSClaudiu Beznea .pp_count = 2, 670cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 671cb783bbbSClaudiu Beznea 672cb783bbbSClaudiu Beznea { .n = "mcan3_gclk", 673cb783bbbSClaudiu Beznea .id = 64, 674cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 675cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 676cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 677cb783bbbSClaudiu Beznea .pp_count = 2, 678cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 679cb783bbbSClaudiu Beznea 680cb783bbbSClaudiu Beznea { .n = "mcan4_gclk", 681cb783bbbSClaudiu Beznea .id = 65, 682cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 683cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 684cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 685cb783bbbSClaudiu Beznea .pp_count = 2, 686cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 687cb783bbbSClaudiu Beznea 688cb783bbbSClaudiu Beznea { .n = "mcan5_gclk", 689cb783bbbSClaudiu Beznea .id = 66, 690cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 691cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 692cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 693cb783bbbSClaudiu Beznea .pp_count = 2, 694cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 695cb783bbbSClaudiu Beznea 696cb783bbbSClaudiu Beznea { .n = "pdmc0_gclk", 697cb783bbbSClaudiu Beznea .id = 68, 698cb783bbbSClaudiu Beznea .r = { .max = 50000000 }, 699cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 700cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 701cb783bbbSClaudiu Beznea .pp_count = 2, 702cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 703cb783bbbSClaudiu Beznea 704cb783bbbSClaudiu Beznea { .n = "pdmc1_gclk", 705cb783bbbSClaudiu Beznea .id = 69, 706cb783bbbSClaudiu Beznea .r = { .max = 50000000, }, 707cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 708cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 709cb783bbbSClaudiu Beznea .pp_count = 2, 710cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 711cb783bbbSClaudiu Beznea 712cb783bbbSClaudiu Beznea { .n = "pit64b0_gclk", 713cb783bbbSClaudiu Beznea .id = 70, 714cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 715cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck", 716cb783bbbSClaudiu Beznea "audiopll_divpmcck", "ethpll_divpmcck", }, 717cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 7, 8, 9, 10, }, 718cb783bbbSClaudiu Beznea .pp_count = 5, 719cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 720cb783bbbSClaudiu Beznea 721cb783bbbSClaudiu Beznea { .n = "pit64b1_gclk", 722cb783bbbSClaudiu Beznea .id = 71, 723cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 724cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck", 725cb783bbbSClaudiu Beznea "audiopll_divpmcck", "ethpll_divpmcck", }, 726cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 7, 8, 9, 10, }, 727cb783bbbSClaudiu Beznea .pp_count = 5, 728cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 729cb783bbbSClaudiu Beznea 730cb783bbbSClaudiu Beznea { .n = "pit64b2_gclk", 731cb783bbbSClaudiu Beznea .id = 72, 732cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 733cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck", 734cb783bbbSClaudiu Beznea "audiopll_divpmcck", "ethpll_divpmcck", }, 735cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 7, 8, 9, 10, }, 736cb783bbbSClaudiu Beznea .pp_count = 5, 737cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 738cb783bbbSClaudiu Beznea 739cb783bbbSClaudiu Beznea { .n = "pit64b3_gclk", 740cb783bbbSClaudiu Beznea .id = 73, 741cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 742cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck", 743cb783bbbSClaudiu Beznea "audiopll_divpmcck", "ethpll_divpmcck", }, 744cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 7, 8, 9, 10, }, 745cb783bbbSClaudiu Beznea .pp_count = 5, 746cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 747cb783bbbSClaudiu Beznea 748cb783bbbSClaudiu Beznea { .n = "pit64b4_gclk", 749cb783bbbSClaudiu Beznea .id = 74, 750cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 751cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck", 752cb783bbbSClaudiu Beznea "audiopll_divpmcck", "ethpll_divpmcck", }, 753cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 7, 8, 9, 10, }, 754cb783bbbSClaudiu Beznea .pp_count = 5, 755cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 756cb783bbbSClaudiu Beznea 757cb783bbbSClaudiu Beznea { .n = "pit64b5_gclk", 758cb783bbbSClaudiu Beznea .id = 75, 759cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 760cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck", 761cb783bbbSClaudiu Beznea "audiopll_divpmcck", "ethpll_divpmcck", }, 762cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 7, 8, 9, 10, }, 763cb783bbbSClaudiu Beznea .pp_count = 5, 764cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 765cb783bbbSClaudiu Beznea 766cb783bbbSClaudiu Beznea { .n = "qspi0_gclk", 767cb783bbbSClaudiu Beznea .id = 78, 768cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 769cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 770cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 771cb783bbbSClaudiu Beznea .pp_count = 2, 772cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 773cb783bbbSClaudiu Beznea 774cb783bbbSClaudiu Beznea { .n = "qspi1_gclk", 775cb783bbbSClaudiu Beznea .id = 79, 776cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 777cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 778cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 779cb783bbbSClaudiu Beznea .pp_count = 2, 780cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 781cb783bbbSClaudiu Beznea 782cb783bbbSClaudiu Beznea { .n = "sdmmc0_gclk", 783cb783bbbSClaudiu Beznea .id = 80, 784cb783bbbSClaudiu Beznea .r = { .max = 208000000 }, 785cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 786cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 787cb783bbbSClaudiu Beznea .pp_count = 2, 7884011f03eSClaudiu Beznea .pp_chg_id = 4, }, 789cb783bbbSClaudiu Beznea 790cb783bbbSClaudiu Beznea { .n = "sdmmc1_gclk", 791cb783bbbSClaudiu Beznea .id = 81, 792cb783bbbSClaudiu Beznea .r = { .max = 208000000 }, 793cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 794cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 795cb783bbbSClaudiu Beznea .pp_count = 2, 7964011f03eSClaudiu Beznea .pp_chg_id = 4, }, 797cb783bbbSClaudiu Beznea 798cb783bbbSClaudiu Beznea { .n = "sdmmc2_gclk", 799cb783bbbSClaudiu Beznea .id = 82, 800cb783bbbSClaudiu Beznea .r = { .max = 208000000 }, 801cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 802cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 803cb783bbbSClaudiu Beznea .pp_count = 2, 8044011f03eSClaudiu Beznea .pp_chg_id = 4, }, 805cb783bbbSClaudiu Beznea 806cb783bbbSClaudiu Beznea { .n = "spdifrx_gclk", 807cb783bbbSClaudiu Beznea .id = 84, 808cb783bbbSClaudiu Beznea .r = { .max = 150000000 }, 809cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "audiopll_divpmcck", }, 810cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 9, }, 811cb783bbbSClaudiu Beznea .pp_count = 2, 8124011f03eSClaudiu Beznea .pp_chg_id = 4, }, 813cb783bbbSClaudiu Beznea 814cb783bbbSClaudiu Beznea { .n = "spdiftx_gclk", 815cb783bbbSClaudiu Beznea .id = 85, 816cb783bbbSClaudiu Beznea .r = { .max = 25000000 }, 817cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "audiopll_divpmcck", }, 818cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 9, }, 819cb783bbbSClaudiu Beznea .pp_count = 2, 8204011f03eSClaudiu Beznea .pp_chg_id = 4, }, 821cb783bbbSClaudiu Beznea 822cb783bbbSClaudiu Beznea { .n = "tcb0_ch0_gclk", 823cb783bbbSClaudiu Beznea .id = 88, 824cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 825cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck", 826cb783bbbSClaudiu Beznea "audiopll_divpmcck", "ethpll_divpmcck", }, 827cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 7, 8, 9, 10, }, 828cb783bbbSClaudiu Beznea .pp_count = 5, 829cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 830cb783bbbSClaudiu Beznea 831cb783bbbSClaudiu Beznea { .n = "tcb1_ch0_gclk", 832cb783bbbSClaudiu Beznea .id = 91, 833cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 834cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck", 835cb783bbbSClaudiu Beznea "audiopll_divpmcck", "ethpll_divpmcck", }, 836cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 7, 8, 9, 10, }, 837cb783bbbSClaudiu Beznea .pp_count = 5, 838cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 839cb783bbbSClaudiu Beznea 840cb783bbbSClaudiu Beznea { .n = "tcpca_gclk", 841cb783bbbSClaudiu Beznea .id = 94, 842cb783bbbSClaudiu Beznea .r = { .max = 32768, }, 843cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 844cb783bbbSClaudiu Beznea 845cb783bbbSClaudiu Beznea { .n = "tcpcb_gclk", 846cb783bbbSClaudiu Beznea .id = 95, 847cb783bbbSClaudiu Beznea .r = { .max = 32768, }, 848cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 849cb783bbbSClaudiu Beznea }; 850cb783bbbSClaudiu Beznea 851cb783bbbSClaudiu Beznea /* MCK0 characteristics. */ 852cb783bbbSClaudiu Beznea static const struct clk_master_characteristics mck0_characteristics = { 853f803858aSClaudiu Beznea .output = { .min = 50000000, .max = 200000000 }, 8540bb4623fSEugen Hristev .divisors = { 1, 2, 4, 3, 5 }, 855cb783bbbSClaudiu Beznea .have_div3_pres = 1, 856cb783bbbSClaudiu Beznea }; 857cb783bbbSClaudiu Beznea 858cb783bbbSClaudiu Beznea /* MCK0 layout. */ 859cb783bbbSClaudiu Beznea static const struct clk_master_layout mck0_layout = { 8600bb4623fSEugen Hristev .mask = 0x773, 861cb783bbbSClaudiu Beznea .pres_shift = 4, 862cb783bbbSClaudiu Beznea .offset = 0x28, 863cb783bbbSClaudiu Beznea }; 864cb783bbbSClaudiu Beznea 865cb783bbbSClaudiu Beznea /* Programmable clock layout. */ 866cb783bbbSClaudiu Beznea static const struct clk_programmable_layout programmable_layout = { 867cb783bbbSClaudiu Beznea .pres_mask = 0xff, 868cb783bbbSClaudiu Beznea .pres_shift = 8, 869cb783bbbSClaudiu Beznea .css_mask = 0x1f, 870cb783bbbSClaudiu Beznea .have_slck_mck = 0, 871cb783bbbSClaudiu Beznea .is_pres_direct = 1, 872cb783bbbSClaudiu Beznea }; 873cb783bbbSClaudiu Beznea 874cb783bbbSClaudiu Beznea /* Peripheral clock layout. */ 875cb783bbbSClaudiu Beznea static const struct clk_pcr_layout sama7g5_pcr_layout = { 876cb783bbbSClaudiu Beznea .offset = 0x88, 877cb783bbbSClaudiu Beznea .cmd = BIT(31), 878cb783bbbSClaudiu Beznea .gckcss_mask = GENMASK(12, 8), 879cb783bbbSClaudiu Beznea .pid_mask = GENMASK(6, 0), 880cb783bbbSClaudiu Beznea }; 881cb783bbbSClaudiu Beznea 882cb783bbbSClaudiu Beznea static void __init sama7g5_pmc_setup(struct device_node *np) 883cb783bbbSClaudiu Beznea { 884cb783bbbSClaudiu Beznea const char *td_slck_name, *md_slck_name, *mainxtal_name; 885cb783bbbSClaudiu Beznea struct pmc_data *sama7g5_pmc; 886cb783bbbSClaudiu Beznea const char *parent_names[10]; 887cb783bbbSClaudiu Beznea void **alloc_mem = NULL; 888cb783bbbSClaudiu Beznea int alloc_mem_size = 0; 889cb783bbbSClaudiu Beznea struct regmap *regmap; 890cb783bbbSClaudiu Beznea struct clk_hw *hw; 891cb783bbbSClaudiu Beznea bool bypass; 892cb783bbbSClaudiu Beznea int i, j; 893cb783bbbSClaudiu Beznea 894cb783bbbSClaudiu Beznea i = of_property_match_string(np, "clock-names", "td_slck"); 895cb783bbbSClaudiu Beznea if (i < 0) 896cb783bbbSClaudiu Beznea return; 897cb783bbbSClaudiu Beznea 898cb783bbbSClaudiu Beznea td_slck_name = of_clk_get_parent_name(np, i); 899cb783bbbSClaudiu Beznea 900cb783bbbSClaudiu Beznea i = of_property_match_string(np, "clock-names", "md_slck"); 901cb783bbbSClaudiu Beznea if (i < 0) 902cb783bbbSClaudiu Beznea return; 903cb783bbbSClaudiu Beznea 904cb783bbbSClaudiu Beznea md_slck_name = of_clk_get_parent_name(np, i); 905cb783bbbSClaudiu Beznea 906cb783bbbSClaudiu Beznea i = of_property_match_string(np, "clock-names", "main_xtal"); 907cb783bbbSClaudiu Beznea if (i < 0) 908cb783bbbSClaudiu Beznea return; 909cb783bbbSClaudiu Beznea 910cb783bbbSClaudiu Beznea mainxtal_name = of_clk_get_parent_name(np, i); 911cb783bbbSClaudiu Beznea 912cb783bbbSClaudiu Beznea regmap = device_node_to_regmap(np); 913cb783bbbSClaudiu Beznea if (IS_ERR(regmap)) 914cb783bbbSClaudiu Beznea return; 915cb783bbbSClaudiu Beznea 91691f3bf0dSClaudiu Beznea sama7g5_pmc = pmc_data_allocate(PMC_CPU + 1, 917cb783bbbSClaudiu Beznea nck(sama7g5_systemck), 918cb783bbbSClaudiu Beznea nck(sama7g5_periphck), 91991274497SClaudiu Beznea nck(sama7g5_gck), 8); 920cb783bbbSClaudiu Beznea if (!sama7g5_pmc) 921cb783bbbSClaudiu Beznea return; 922cb783bbbSClaudiu Beznea 923cb783bbbSClaudiu Beznea alloc_mem = kmalloc(sizeof(void *) * 924cb783bbbSClaudiu Beznea (ARRAY_SIZE(sama7g5_mckx) + ARRAY_SIZE(sama7g5_gck)), 925cb783bbbSClaudiu Beznea GFP_KERNEL); 926cb783bbbSClaudiu Beznea if (!alloc_mem) 927cb783bbbSClaudiu Beznea goto err_free; 928cb783bbbSClaudiu Beznea 929cb783bbbSClaudiu Beznea hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, 930cb783bbbSClaudiu Beznea 50000000); 931cb783bbbSClaudiu Beznea if (IS_ERR(hw)) 932cb783bbbSClaudiu Beznea goto err_free; 933cb783bbbSClaudiu Beznea 934cb783bbbSClaudiu Beznea bypass = of_property_read_bool(np, "atmel,osc-bypass"); 935cb783bbbSClaudiu Beznea 936cb783bbbSClaudiu Beznea hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, 937cb783bbbSClaudiu Beznea bypass); 938cb783bbbSClaudiu Beznea if (IS_ERR(hw)) 939cb783bbbSClaudiu Beznea goto err_free; 940cb783bbbSClaudiu Beznea 941cb783bbbSClaudiu Beznea parent_names[0] = "main_rc_osc"; 942cb783bbbSClaudiu Beznea parent_names[1] = "main_osc"; 943cb783bbbSClaudiu Beznea hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2); 944cb783bbbSClaudiu Beznea if (IS_ERR(hw)) 945cb783bbbSClaudiu Beznea goto err_free; 946cb783bbbSClaudiu Beznea 947cb783bbbSClaudiu Beznea sama7g5_pmc->chws[PMC_MAIN] = hw; 948cb783bbbSClaudiu Beznea 949cb783bbbSClaudiu Beznea for (i = 0; i < PLL_ID_MAX; i++) { 950cb783bbbSClaudiu Beznea for (j = 0; j < 3; j++) { 951cb783bbbSClaudiu Beznea struct clk_hw *parent_hw; 952cb783bbbSClaudiu Beznea 953cb783bbbSClaudiu Beznea if (!sama7g5_plls[i][j].n) 954cb783bbbSClaudiu Beznea continue; 955cb783bbbSClaudiu Beznea 956cb783bbbSClaudiu Beznea switch (sama7g5_plls[i][j].t) { 957cb783bbbSClaudiu Beznea case PLL_TYPE_FRAC: 958cb783bbbSClaudiu Beznea if (!strcmp(sama7g5_plls[i][j].p, "mainck")) 959cb783bbbSClaudiu Beznea parent_hw = sama7g5_pmc->chws[PMC_MAIN]; 960cb783bbbSClaudiu Beznea else 961cb783bbbSClaudiu Beznea parent_hw = __clk_get_hw(of_clk_get_by_name(np, 962cb783bbbSClaudiu Beznea sama7g5_plls[i][j].p)); 963cb783bbbSClaudiu Beznea 964cb783bbbSClaudiu Beznea hw = sam9x60_clk_register_frac_pll(regmap, 965cb783bbbSClaudiu Beznea &pmc_pll_lock, sama7g5_plls[i][j].n, 966cb783bbbSClaudiu Beznea sama7g5_plls[i][j].p, parent_hw, i, 967120d5d8bSClaudiu Beznea sama7g5_plls[i][j].c, 968cb783bbbSClaudiu Beznea sama7g5_plls[i][j].l, 9698dc4af8bSClaudiu Beznea sama7g5_plls[i][j].f); 970cb783bbbSClaudiu Beznea break; 971cb783bbbSClaudiu Beznea 972cb783bbbSClaudiu Beznea case PLL_TYPE_DIV: 973cb783bbbSClaudiu Beznea hw = sam9x60_clk_register_div_pll(regmap, 974cb783bbbSClaudiu Beznea &pmc_pll_lock, sama7g5_plls[i][j].n, 975cb783bbbSClaudiu Beznea sama7g5_plls[i][j].p, i, 976120d5d8bSClaudiu Beznea sama7g5_plls[i][j].c, 977cb783bbbSClaudiu Beznea sama7g5_plls[i][j].l, 9781e229c21SClaudiu Beznea sama7g5_plls[i][j].f, 9791e229c21SClaudiu Beznea sama7g5_plls[i][j].safe_div); 980cb783bbbSClaudiu Beznea break; 981cb783bbbSClaudiu Beznea 982cb783bbbSClaudiu Beznea default: 983cb783bbbSClaudiu Beznea continue; 984cb783bbbSClaudiu Beznea } 985cb783bbbSClaudiu Beznea 986cb783bbbSClaudiu Beznea if (IS_ERR(hw)) 987cb783bbbSClaudiu Beznea goto err_free; 988cb783bbbSClaudiu Beznea 989cb783bbbSClaudiu Beznea if (sama7g5_plls[i][j].eid) 990cb783bbbSClaudiu Beznea sama7g5_pmc->chws[sama7g5_plls[i][j].eid] = hw; 991cb783bbbSClaudiu Beznea } 992cb783bbbSClaudiu Beznea } 993cb783bbbSClaudiu Beznea 99491f3bf0dSClaudiu Beznea parent_names[0] = "cpupll_divpmcck"; 995*facb87adSClaudiu Beznea hw = at91_clk_register_master_div(regmap, "mck0", "cpupll_divpmcck", 9967a110b91SClaudiu Beznea &mck0_layout, &mck0_characteristics, 9977029db09SClaudiu Beznea &pmc_mck0_lock, CLK_GET_RATE_NOCACHE, 5); 998cb783bbbSClaudiu Beznea if (IS_ERR(hw)) 999cb783bbbSClaudiu Beznea goto err_free; 1000cb783bbbSClaudiu Beznea 1001cb783bbbSClaudiu Beznea sama7g5_pmc->chws[PMC_MCK] = hw; 1002cb783bbbSClaudiu Beznea 1003cb783bbbSClaudiu Beznea parent_names[0] = md_slck_name; 1004cb783bbbSClaudiu Beznea parent_names[1] = td_slck_name; 1005cb783bbbSClaudiu Beznea parent_names[2] = "mainck"; 1006cb783bbbSClaudiu Beznea for (i = 0; i < ARRAY_SIZE(sama7g5_mckx); i++) { 10074011f03eSClaudiu Beznea u8 num_parents = 3 + sama7g5_mckx[i].ep_count; 1008cb783bbbSClaudiu Beznea u32 *mux_table; 1009cb783bbbSClaudiu Beznea 1010cb783bbbSClaudiu Beznea mux_table = kmalloc_array(num_parents, sizeof(*mux_table), 1011cb783bbbSClaudiu Beznea GFP_KERNEL); 1012cb783bbbSClaudiu Beznea if (!mux_table) 1013cb783bbbSClaudiu Beznea goto err_free; 1014cb783bbbSClaudiu Beznea 10154011f03eSClaudiu Beznea SAMA7G5_INIT_TABLE(mux_table, 3); 10164011f03eSClaudiu Beznea SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_mckx[i].ep_mux_table, 1017cb783bbbSClaudiu Beznea sama7g5_mckx[i].ep_count); 10184011f03eSClaudiu Beznea SAMA7G5_FILL_TABLE(&parent_names[3], sama7g5_mckx[i].ep, 1019cb783bbbSClaudiu Beznea sama7g5_mckx[i].ep_count); 1020cb783bbbSClaudiu Beznea 1021cb783bbbSClaudiu Beznea hw = at91_clk_sama7g5_register_master(regmap, sama7g5_mckx[i].n, 1022cb783bbbSClaudiu Beznea num_parents, parent_names, mux_table, 1023cb783bbbSClaudiu Beznea &pmc_mckX_lock, sama7g5_mckx[i].id, 1024cb783bbbSClaudiu Beznea sama7g5_mckx[i].c, 1025cb783bbbSClaudiu Beznea sama7g5_mckx[i].ep_chg_id); 1026cb783bbbSClaudiu Beznea if (IS_ERR(hw)) 1027cb783bbbSClaudiu Beznea goto err_free; 1028cb783bbbSClaudiu Beznea 1029cb783bbbSClaudiu Beznea alloc_mem[alloc_mem_size++] = mux_table; 1030cb783bbbSClaudiu Beznea } 1031cb783bbbSClaudiu Beznea 1032cb783bbbSClaudiu Beznea hw = at91_clk_sama7g5_register_utmi(regmap, "utmick", "main_xtal"); 1033cb783bbbSClaudiu Beznea if (IS_ERR(hw)) 1034cb783bbbSClaudiu Beznea goto err_free; 1035cb783bbbSClaudiu Beznea 1036cb783bbbSClaudiu Beznea sama7g5_pmc->chws[PMC_UTMI] = hw; 1037cb783bbbSClaudiu Beznea 1038cb783bbbSClaudiu Beznea parent_names[0] = md_slck_name; 1039cb783bbbSClaudiu Beznea parent_names[1] = td_slck_name; 1040cb783bbbSClaudiu Beznea parent_names[2] = "mainck"; 10414011f03eSClaudiu Beznea parent_names[3] = "syspll_divpmcck"; 10424011f03eSClaudiu Beznea parent_names[4] = "ddrpll_divpmcck"; 10434011f03eSClaudiu Beznea parent_names[5] = "imgpll_divpmcck"; 10444011f03eSClaudiu Beznea parent_names[6] = "baudpll_divpmcck"; 10454011f03eSClaudiu Beznea parent_names[7] = "audiopll_divpmcck"; 10464011f03eSClaudiu Beznea parent_names[8] = "ethpll_divpmcck"; 1047cb783bbbSClaudiu Beznea for (i = 0; i < 8; i++) { 1048cb783bbbSClaudiu Beznea char name[6]; 1049cb783bbbSClaudiu Beznea 1050cb783bbbSClaudiu Beznea snprintf(name, sizeof(name), "prog%d", i); 1051cb783bbbSClaudiu Beznea 1052cb783bbbSClaudiu Beznea hw = at91_clk_register_programmable(regmap, name, parent_names, 10534011f03eSClaudiu Beznea 9, i, 1054cb783bbbSClaudiu Beznea &programmable_layout, 1055cb783bbbSClaudiu Beznea sama7g5_prog_mux_table); 1056cb783bbbSClaudiu Beznea if (IS_ERR(hw)) 1057cb783bbbSClaudiu Beznea goto err_free; 105891274497SClaudiu Beznea 105991274497SClaudiu Beznea sama7g5_pmc->pchws[i] = hw; 1060cb783bbbSClaudiu Beznea } 1061cb783bbbSClaudiu Beznea 1062cb783bbbSClaudiu Beznea for (i = 0; i < ARRAY_SIZE(sama7g5_systemck); i++) { 1063cb783bbbSClaudiu Beznea hw = at91_clk_register_system(regmap, sama7g5_systemck[i].n, 1064cb783bbbSClaudiu Beznea sama7g5_systemck[i].p, 1065cb783bbbSClaudiu Beznea sama7g5_systemck[i].id); 1066cb783bbbSClaudiu Beznea if (IS_ERR(hw)) 1067cb783bbbSClaudiu Beznea goto err_free; 1068cb783bbbSClaudiu Beznea 1069cb783bbbSClaudiu Beznea sama7g5_pmc->shws[sama7g5_systemck[i].id] = hw; 1070cb783bbbSClaudiu Beznea } 1071cb783bbbSClaudiu Beznea 1072cb783bbbSClaudiu Beznea for (i = 0; i < ARRAY_SIZE(sama7g5_periphck); i++) { 1073cb783bbbSClaudiu Beznea hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, 1074cb783bbbSClaudiu Beznea &sama7g5_pcr_layout, 1075cb783bbbSClaudiu Beznea sama7g5_periphck[i].n, 1076cb783bbbSClaudiu Beznea sama7g5_periphck[i].p, 1077cb783bbbSClaudiu Beznea sama7g5_periphck[i].id, 1078cb783bbbSClaudiu Beznea &sama7g5_periphck[i].r, 1079cb783bbbSClaudiu Beznea sama7g5_periphck[i].chgp ? 0 : 1080cb783bbbSClaudiu Beznea INT_MIN); 1081cb783bbbSClaudiu Beznea if (IS_ERR(hw)) 1082cb783bbbSClaudiu Beznea goto err_free; 1083cb783bbbSClaudiu Beznea 1084cb783bbbSClaudiu Beznea sama7g5_pmc->phws[sama7g5_periphck[i].id] = hw; 1085cb783bbbSClaudiu Beznea } 1086cb783bbbSClaudiu Beznea 1087cb783bbbSClaudiu Beznea parent_names[0] = md_slck_name; 1088cb783bbbSClaudiu Beznea parent_names[1] = td_slck_name; 1089cb783bbbSClaudiu Beznea parent_names[2] = "mainck"; 1090cb783bbbSClaudiu Beznea for (i = 0; i < ARRAY_SIZE(sama7g5_gck); i++) { 10914011f03eSClaudiu Beznea u8 num_parents = 3 + sama7g5_gck[i].pp_count; 1092cb783bbbSClaudiu Beznea u32 *mux_table; 1093cb783bbbSClaudiu Beznea 1094cb783bbbSClaudiu Beznea mux_table = kmalloc_array(num_parents, sizeof(*mux_table), 1095cb783bbbSClaudiu Beznea GFP_KERNEL); 1096cb783bbbSClaudiu Beznea if (!mux_table) 1097cb783bbbSClaudiu Beznea goto err_free; 1098cb783bbbSClaudiu Beznea 10994011f03eSClaudiu Beznea SAMA7G5_INIT_TABLE(mux_table, 3); 11004011f03eSClaudiu Beznea SAMA7G5_FILL_TABLE(&mux_table[3], sama7g5_gck[i].pp_mux_table, 1101cb783bbbSClaudiu Beznea sama7g5_gck[i].pp_count); 11024011f03eSClaudiu Beznea SAMA7G5_FILL_TABLE(&parent_names[3], sama7g5_gck[i].pp, 1103cb783bbbSClaudiu Beznea sama7g5_gck[i].pp_count); 1104cb783bbbSClaudiu Beznea 1105cb783bbbSClaudiu Beznea hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, 1106cb783bbbSClaudiu Beznea &sama7g5_pcr_layout, 1107cb783bbbSClaudiu Beznea sama7g5_gck[i].n, 1108cb783bbbSClaudiu Beznea parent_names, mux_table, 1109cb783bbbSClaudiu Beznea num_parents, 1110cb783bbbSClaudiu Beznea sama7g5_gck[i].id, 1111cb783bbbSClaudiu Beznea &sama7g5_gck[i].r, 1112cb783bbbSClaudiu Beznea sama7g5_gck[i].pp_chg_id); 1113cb783bbbSClaudiu Beznea if (IS_ERR(hw)) 1114cb783bbbSClaudiu Beznea goto err_free; 1115cb783bbbSClaudiu Beznea 1116cb783bbbSClaudiu Beznea sama7g5_pmc->ghws[sama7g5_gck[i].id] = hw; 1117cb783bbbSClaudiu Beznea alloc_mem[alloc_mem_size++] = mux_table; 1118cb783bbbSClaudiu Beznea } 1119cb783bbbSClaudiu Beznea 1120cb783bbbSClaudiu Beznea of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sama7g5_pmc); 1121cb783bbbSClaudiu Beznea 1122cb783bbbSClaudiu Beznea return; 1123cb783bbbSClaudiu Beznea 1124cb783bbbSClaudiu Beznea err_free: 1125cb783bbbSClaudiu Beznea if (alloc_mem) { 1126cb783bbbSClaudiu Beznea for (i = 0; i < alloc_mem_size; i++) 1127cb783bbbSClaudiu Beznea kfree(alloc_mem[i]); 1128cb783bbbSClaudiu Beznea kfree(alloc_mem); 1129cb783bbbSClaudiu Beznea } 1130cb783bbbSClaudiu Beznea 113191274497SClaudiu Beznea kfree(sama7g5_pmc); 1132cb783bbbSClaudiu Beznea } 1133cb783bbbSClaudiu Beznea 1134cb783bbbSClaudiu Beznea /* Some clks are used for a clocksource */ 1135cb783bbbSClaudiu Beznea CLK_OF_DECLARE(sama7g5_pmc, "microchip,sama7g5-pmc", sama7g5_pmc_setup); 1136