1cb783bbbSClaudiu Beznea // SPDX-License-Identifier: GPL-2.0 2cb783bbbSClaudiu Beznea /* 3cb783bbbSClaudiu Beznea * SAMA7G5 PMC code. 4cb783bbbSClaudiu Beznea * 5cb783bbbSClaudiu Beznea * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries 6cb783bbbSClaudiu Beznea * 7cb783bbbSClaudiu Beznea * Author: Claudiu Beznea <claudiu.beznea@microchip.com> 8cb783bbbSClaudiu Beznea * 9cb783bbbSClaudiu Beznea */ 10cb783bbbSClaudiu Beznea #include <linux/clk.h> 11cb783bbbSClaudiu Beznea #include <linux/clk-provider.h> 12cb783bbbSClaudiu Beznea #include <linux/mfd/syscon.h> 13cb783bbbSClaudiu Beznea #include <linux/slab.h> 14cb783bbbSClaudiu Beznea 15cb783bbbSClaudiu Beznea #include <dt-bindings/clock/at91.h> 16cb783bbbSClaudiu Beznea 17cb783bbbSClaudiu Beznea #include "pmc.h" 18cb783bbbSClaudiu Beznea 19cb783bbbSClaudiu Beznea #define SAMA7G5_INIT_TABLE(_table, _count) \ 20cb783bbbSClaudiu Beznea do { \ 21cb783bbbSClaudiu Beznea u8 _i; \ 22cb783bbbSClaudiu Beznea for (_i = 0; _i < (_count); _i++) \ 23cb783bbbSClaudiu Beznea (_table)[_i] = _i; \ 24cb783bbbSClaudiu Beznea } while (0) 25cb783bbbSClaudiu Beznea 26cb783bbbSClaudiu Beznea #define SAMA7G5_FILL_TABLE(_to, _from, _count) \ 27cb783bbbSClaudiu Beznea do { \ 28cb783bbbSClaudiu Beznea u8 _i; \ 29cb783bbbSClaudiu Beznea for (_i = 0; _i < (_count); _i++) { \ 30cb783bbbSClaudiu Beznea (_to)[_i] = (_from)[_i]; \ 31cb783bbbSClaudiu Beznea } \ 32cb783bbbSClaudiu Beznea } while (0) 33cb783bbbSClaudiu Beznea 34cb783bbbSClaudiu Beznea static DEFINE_SPINLOCK(pmc_pll_lock); 35cb783bbbSClaudiu Beznea static DEFINE_SPINLOCK(pmc_mckX_lock); 36cb783bbbSClaudiu Beznea 37cb783bbbSClaudiu Beznea /** 38cb783bbbSClaudiu Beznea * PLL clocks identifiers 39cb783bbbSClaudiu Beznea * @PLL_ID_CPU: CPU PLL identifier 40cb783bbbSClaudiu Beznea * @PLL_ID_SYS: System PLL identifier 41cb783bbbSClaudiu Beznea * @PLL_ID_DDR: DDR PLL identifier 42cb783bbbSClaudiu Beznea * @PLL_ID_IMG: Image subsystem PLL identifier 43cb783bbbSClaudiu Beznea * @PLL_ID_BAUD: Baud PLL identifier 44cb783bbbSClaudiu Beznea * @PLL_ID_AUDIO: Audio PLL identifier 45cb783bbbSClaudiu Beznea * @PLL_ID_ETH: Ethernet PLL identifier 46cb783bbbSClaudiu Beznea */ 47cb783bbbSClaudiu Beznea enum pll_ids { 48cb783bbbSClaudiu Beznea PLL_ID_CPU, 49cb783bbbSClaudiu Beznea PLL_ID_SYS, 50cb783bbbSClaudiu Beznea PLL_ID_DDR, 51cb783bbbSClaudiu Beznea PLL_ID_IMG, 52cb783bbbSClaudiu Beznea PLL_ID_BAUD, 53cb783bbbSClaudiu Beznea PLL_ID_AUDIO, 54cb783bbbSClaudiu Beznea PLL_ID_ETH, 55cb783bbbSClaudiu Beznea PLL_ID_MAX, 56cb783bbbSClaudiu Beznea }; 57cb783bbbSClaudiu Beznea 58cb783bbbSClaudiu Beznea /** 59cb783bbbSClaudiu Beznea * PLL type identifiers 60cb783bbbSClaudiu Beznea * @PLL_TYPE_FRAC: fractional PLL identifier 61cb783bbbSClaudiu Beznea * @PLL_TYPE_DIV: divider PLL identifier 62cb783bbbSClaudiu Beznea */ 63cb783bbbSClaudiu Beznea enum pll_type { 64cb783bbbSClaudiu Beznea PLL_TYPE_FRAC, 65cb783bbbSClaudiu Beznea PLL_TYPE_DIV, 66cb783bbbSClaudiu Beznea }; 67cb783bbbSClaudiu Beznea 68cb783bbbSClaudiu Beznea /* Layout for fractional PLLs. */ 69cb783bbbSClaudiu Beznea static const struct clk_pll_layout pll_layout_frac = { 70cb783bbbSClaudiu Beznea .mul_mask = GENMASK(31, 24), 71cb783bbbSClaudiu Beznea .frac_mask = GENMASK(21, 0), 72cb783bbbSClaudiu Beznea .mul_shift = 24, 73cb783bbbSClaudiu Beznea .frac_shift = 0, 74cb783bbbSClaudiu Beznea }; 75cb783bbbSClaudiu Beznea 76cb783bbbSClaudiu Beznea /* Layout for DIVPMC dividers. */ 77cb783bbbSClaudiu Beznea static const struct clk_pll_layout pll_layout_divpmc = { 78cb783bbbSClaudiu Beznea .div_mask = GENMASK(7, 0), 79cb783bbbSClaudiu Beznea .endiv_mask = BIT(29), 80cb783bbbSClaudiu Beznea .div_shift = 0, 81cb783bbbSClaudiu Beznea .endiv_shift = 29, 82cb783bbbSClaudiu Beznea }; 83cb783bbbSClaudiu Beznea 84cb783bbbSClaudiu Beznea /* Layout for DIVIO dividers. */ 85cb783bbbSClaudiu Beznea static const struct clk_pll_layout pll_layout_divio = { 86cb783bbbSClaudiu Beznea .div_mask = GENMASK(19, 12), 87cb783bbbSClaudiu Beznea .endiv_mask = BIT(30), 88cb783bbbSClaudiu Beznea .div_shift = 12, 89cb783bbbSClaudiu Beznea .endiv_shift = 30, 90cb783bbbSClaudiu Beznea }; 91cb783bbbSClaudiu Beznea 92cb783bbbSClaudiu Beznea /** 93cb783bbbSClaudiu Beznea * PLL clocks description 94cb783bbbSClaudiu Beznea * @n: clock name 95cb783bbbSClaudiu Beznea * @p: clock parent 96cb783bbbSClaudiu Beznea * @l: clock layout 97cb783bbbSClaudiu Beznea * @t: clock type 98cb783bbbSClaudiu Beznea * @f: true if clock is critical and cannot be disabled 99cb783bbbSClaudiu Beznea * @eid: export index in sama7g5->chws[] array 100cb783bbbSClaudiu Beznea */ 101cb783bbbSClaudiu Beznea static const struct { 102cb783bbbSClaudiu Beznea const char *n; 103cb783bbbSClaudiu Beznea const char *p; 104cb783bbbSClaudiu Beznea const struct clk_pll_layout *l; 105cb783bbbSClaudiu Beznea u8 t; 106cb783bbbSClaudiu Beznea u8 c; 107cb783bbbSClaudiu Beznea u8 eid; 108cb783bbbSClaudiu Beznea } sama7g5_plls[][PLL_ID_MAX] = { 109cb783bbbSClaudiu Beznea [PLL_ID_CPU] = { 110cb783bbbSClaudiu Beznea { .n = "cpupll_fracck", 111cb783bbbSClaudiu Beznea .p = "mainck", 112cb783bbbSClaudiu Beznea .l = &pll_layout_frac, 113cb783bbbSClaudiu Beznea .t = PLL_TYPE_FRAC, 114cb783bbbSClaudiu Beznea .c = 1, }, 115cb783bbbSClaudiu Beznea 116cb783bbbSClaudiu Beznea { .n = "cpupll_divpmcck", 117cb783bbbSClaudiu Beznea .p = "cpupll_fracck", 118cb783bbbSClaudiu Beznea .l = &pll_layout_divpmc, 119cb783bbbSClaudiu Beznea .t = PLL_TYPE_DIV, 120cb783bbbSClaudiu Beznea .c = 1, }, 121cb783bbbSClaudiu Beznea }, 122cb783bbbSClaudiu Beznea 123cb783bbbSClaudiu Beznea [PLL_ID_SYS] = { 124cb783bbbSClaudiu Beznea { .n = "syspll_fracck", 125cb783bbbSClaudiu Beznea .p = "mainck", 126cb783bbbSClaudiu Beznea .l = &pll_layout_frac, 127cb783bbbSClaudiu Beznea .t = PLL_TYPE_FRAC, 128cb783bbbSClaudiu Beznea .c = 1, }, 129cb783bbbSClaudiu Beznea 130cb783bbbSClaudiu Beznea { .n = "syspll_divpmcck", 131cb783bbbSClaudiu Beznea .p = "syspll_fracck", 132cb783bbbSClaudiu Beznea .l = &pll_layout_divpmc, 133cb783bbbSClaudiu Beznea .t = PLL_TYPE_DIV, 134cb783bbbSClaudiu Beznea .c = 1, }, 135cb783bbbSClaudiu Beznea }, 136cb783bbbSClaudiu Beznea 137cb783bbbSClaudiu Beznea [PLL_ID_DDR] = { 138cb783bbbSClaudiu Beznea { .n = "ddrpll_fracck", 139cb783bbbSClaudiu Beznea .p = "mainck", 140cb783bbbSClaudiu Beznea .l = &pll_layout_frac, 141cb783bbbSClaudiu Beznea .t = PLL_TYPE_FRAC, 142cb783bbbSClaudiu Beznea .c = 1, }, 143cb783bbbSClaudiu Beznea 144cb783bbbSClaudiu Beznea { .n = "ddrpll_divpmcck", 145cb783bbbSClaudiu Beznea .p = "ddrpll_fracck", 146cb783bbbSClaudiu Beznea .l = &pll_layout_divpmc, 147cb783bbbSClaudiu Beznea .t = PLL_TYPE_DIV, 148cb783bbbSClaudiu Beznea .c = 1, }, 149cb783bbbSClaudiu Beznea }, 150cb783bbbSClaudiu Beznea 151cb783bbbSClaudiu Beznea [PLL_ID_IMG] = { 152cb783bbbSClaudiu Beznea { .n = "imgpll_fracck", 153cb783bbbSClaudiu Beznea .p = "mainck", 154cb783bbbSClaudiu Beznea .l = &pll_layout_frac, 155cb783bbbSClaudiu Beznea .t = PLL_TYPE_FRAC, }, 156cb783bbbSClaudiu Beznea 157cb783bbbSClaudiu Beznea { .n = "imgpll_divpmcck", 158cb783bbbSClaudiu Beznea .p = "imgpll_fracck", 159cb783bbbSClaudiu Beznea .l = &pll_layout_divpmc, 160cb783bbbSClaudiu Beznea .t = PLL_TYPE_DIV, }, 161cb783bbbSClaudiu Beznea }, 162cb783bbbSClaudiu Beznea 163cb783bbbSClaudiu Beznea [PLL_ID_BAUD] = { 164cb783bbbSClaudiu Beznea { .n = "baudpll_fracck", 165cb783bbbSClaudiu Beznea .p = "mainck", 166cb783bbbSClaudiu Beznea .l = &pll_layout_frac, 167cb783bbbSClaudiu Beznea .t = PLL_TYPE_FRAC, }, 168cb783bbbSClaudiu Beznea 169cb783bbbSClaudiu Beznea { .n = "baudpll_divpmcck", 170cb783bbbSClaudiu Beznea .p = "baudpll_fracck", 171cb783bbbSClaudiu Beznea .l = &pll_layout_divpmc, 172cb783bbbSClaudiu Beznea .t = PLL_TYPE_DIV, }, 173cb783bbbSClaudiu Beznea }, 174cb783bbbSClaudiu Beznea 175cb783bbbSClaudiu Beznea [PLL_ID_AUDIO] = { 176cb783bbbSClaudiu Beznea { .n = "audiopll_fracck", 177cb783bbbSClaudiu Beznea .p = "main_xtal", 178cb783bbbSClaudiu Beznea .l = &pll_layout_frac, 179cb783bbbSClaudiu Beznea .t = PLL_TYPE_FRAC, }, 180cb783bbbSClaudiu Beznea 181cb783bbbSClaudiu Beznea { .n = "audiopll_divpmcck", 182cb783bbbSClaudiu Beznea .p = "audiopll_fracck", 183cb783bbbSClaudiu Beznea .l = &pll_layout_divpmc, 184cb783bbbSClaudiu Beznea .t = PLL_TYPE_DIV, 185*3d86ee17SEugen Hristev .eid = PMC_AUDIOPMCPLL, }, 186cb783bbbSClaudiu Beznea 187cb783bbbSClaudiu Beznea { .n = "audiopll_diviock", 188cb783bbbSClaudiu Beznea .p = "audiopll_fracck", 189cb783bbbSClaudiu Beznea .l = &pll_layout_divio, 190cb783bbbSClaudiu Beznea .t = PLL_TYPE_DIV, 191*3d86ee17SEugen Hristev .eid = PMC_AUDIOIOPLL, }, 192cb783bbbSClaudiu Beznea }, 193cb783bbbSClaudiu Beznea 194cb783bbbSClaudiu Beznea [PLL_ID_ETH] = { 195cb783bbbSClaudiu Beznea { .n = "ethpll_fracck", 196cb783bbbSClaudiu Beznea .p = "main_xtal", 197cb783bbbSClaudiu Beznea .l = &pll_layout_frac, 198cb783bbbSClaudiu Beznea .t = PLL_TYPE_FRAC, }, 199cb783bbbSClaudiu Beznea 200cb783bbbSClaudiu Beznea { .n = "ethpll_divpmcck", 201cb783bbbSClaudiu Beznea .p = "ethpll_fracck", 202cb783bbbSClaudiu Beznea .l = &pll_layout_divpmc, 203cb783bbbSClaudiu Beznea .t = PLL_TYPE_DIV, }, 204cb783bbbSClaudiu Beznea }, 205cb783bbbSClaudiu Beznea }; 206cb783bbbSClaudiu Beznea 207cb783bbbSClaudiu Beznea /** 208cb783bbbSClaudiu Beznea * Master clock (MCK[1..4]) description 209cb783bbbSClaudiu Beznea * @n: clock name 210cb783bbbSClaudiu Beznea * @ep: extra parents names array 211cb783bbbSClaudiu Beznea * @ep_chg_chg_id: index in parents array that specifies the changeable 212cb783bbbSClaudiu Beznea * parent 213cb783bbbSClaudiu Beznea * @ep_count: extra parents count 214cb783bbbSClaudiu Beznea * @ep_mux_table: mux table for extra parents 215cb783bbbSClaudiu Beznea * @id: clock id 216cb783bbbSClaudiu Beznea * @c: true if clock is critical and cannot be disabled 217cb783bbbSClaudiu Beznea */ 218cb783bbbSClaudiu Beznea static const struct { 219cb783bbbSClaudiu Beznea const char *n; 220cb783bbbSClaudiu Beznea const char *ep[4]; 221cb783bbbSClaudiu Beznea int ep_chg_id; 222cb783bbbSClaudiu Beznea u8 ep_count; 223cb783bbbSClaudiu Beznea u8 ep_mux_table[4]; 224cb783bbbSClaudiu Beznea u8 id; 225cb783bbbSClaudiu Beznea u8 c; 226cb783bbbSClaudiu Beznea } sama7g5_mckx[] = { 227cb783bbbSClaudiu Beznea { .n = "mck1", 228cb783bbbSClaudiu Beznea .id = 1, 229cb783bbbSClaudiu Beznea .ep = { "syspll_divpmcck", }, 230cb783bbbSClaudiu Beznea .ep_mux_table = { 5, }, 231cb783bbbSClaudiu Beznea .ep_count = 1, 232cb783bbbSClaudiu Beznea .ep_chg_id = INT_MIN, 233cb783bbbSClaudiu Beznea .c = 1, }, 234cb783bbbSClaudiu Beznea 235cb783bbbSClaudiu Beznea { .n = "mck2", 236cb783bbbSClaudiu Beznea .id = 2, 237cb783bbbSClaudiu Beznea .ep = { "ddrpll_divpmcck", }, 238cb783bbbSClaudiu Beznea .ep_mux_table = { 6, }, 239cb783bbbSClaudiu Beznea .ep_count = 1, 240cb783bbbSClaudiu Beznea .ep_chg_id = INT_MIN, 241cb783bbbSClaudiu Beznea .c = 1, }, 242cb783bbbSClaudiu Beznea 243cb783bbbSClaudiu Beznea { .n = "mck3", 244cb783bbbSClaudiu Beznea .id = 3, 245cb783bbbSClaudiu Beznea .ep = { "syspll_divpmcck", "ddrpll_divpmcck", "imgpll_divpmcck", }, 246cb783bbbSClaudiu Beznea .ep_mux_table = { 5, 6, 7, }, 247cb783bbbSClaudiu Beznea .ep_count = 3, 248cb783bbbSClaudiu Beznea .ep_chg_id = 6, }, 249cb783bbbSClaudiu Beznea 250cb783bbbSClaudiu Beznea { .n = "mck4", 251cb783bbbSClaudiu Beznea .id = 4, 252cb783bbbSClaudiu Beznea .ep = { "syspll_divpmcck", }, 253cb783bbbSClaudiu Beznea .ep_mux_table = { 5, }, 254cb783bbbSClaudiu Beznea .ep_count = 1, 255cb783bbbSClaudiu Beznea .ep_chg_id = INT_MIN, 256cb783bbbSClaudiu Beznea .c = 1, }, 257cb783bbbSClaudiu Beznea }; 258cb783bbbSClaudiu Beznea 259cb783bbbSClaudiu Beznea /** 260cb783bbbSClaudiu Beznea * System clock description 261cb783bbbSClaudiu Beznea * @n: clock name 262cb783bbbSClaudiu Beznea * @p: clock parent name 263cb783bbbSClaudiu Beznea * @id: clock id 264cb783bbbSClaudiu Beznea */ 265cb783bbbSClaudiu Beznea static const struct { 266cb783bbbSClaudiu Beznea const char *n; 267cb783bbbSClaudiu Beznea const char *p; 268cb783bbbSClaudiu Beznea u8 id; 269cb783bbbSClaudiu Beznea } sama7g5_systemck[] = { 270cb783bbbSClaudiu Beznea { .n = "pck0", .p = "prog0", .id = 8, }, 271cb783bbbSClaudiu Beznea { .n = "pck1", .p = "prog1", .id = 9, }, 272cb783bbbSClaudiu Beznea { .n = "pck2", .p = "prog2", .id = 10, }, 273cb783bbbSClaudiu Beznea { .n = "pck3", .p = "prog3", .id = 11, }, 274cb783bbbSClaudiu Beznea { .n = "pck4", .p = "prog4", .id = 12, }, 275cb783bbbSClaudiu Beznea { .n = "pck5", .p = "prog5", .id = 13, }, 276cb783bbbSClaudiu Beznea { .n = "pck6", .p = "prog6", .id = 14, }, 277cb783bbbSClaudiu Beznea { .n = "pck7", .p = "prog7", .id = 15, }, 278cb783bbbSClaudiu Beznea }; 279cb783bbbSClaudiu Beznea 280cb783bbbSClaudiu Beznea /* Mux table for programmable clocks. */ 281cb783bbbSClaudiu Beznea static u32 sama7g5_prog_mux_table[] = { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, }; 282cb783bbbSClaudiu Beznea 283cb783bbbSClaudiu Beznea /** 284cb783bbbSClaudiu Beznea * Peripheral clock description 285cb783bbbSClaudiu Beznea * @n: clock name 286cb783bbbSClaudiu Beznea * @p: clock parent name 287cb783bbbSClaudiu Beznea * @r: clock range values 288cb783bbbSClaudiu Beznea * @id: clock id 289cb783bbbSClaudiu Beznea * @chgp: index in parent array of the changeable parent 290cb783bbbSClaudiu Beznea */ 291cb783bbbSClaudiu Beznea static const struct { 292cb783bbbSClaudiu Beznea const char *n; 293cb783bbbSClaudiu Beznea const char *p; 294cb783bbbSClaudiu Beznea struct clk_range r; 295cb783bbbSClaudiu Beznea u8 chgp; 296cb783bbbSClaudiu Beznea u8 id; 297cb783bbbSClaudiu Beznea } sama7g5_periphck[] = { 298cb783bbbSClaudiu Beznea { .n = "pioA_clk", .p = "mck0", .id = 11, }, 299cb783bbbSClaudiu Beznea { .n = "sfr_clk", .p = "mck1", .id = 19, }, 300cb783bbbSClaudiu Beznea { .n = "hsmc_clk", .p = "mck1", .id = 21, }, 301cb783bbbSClaudiu Beznea { .n = "xdmac0_clk", .p = "mck1", .id = 22, }, 302cb783bbbSClaudiu Beznea { .n = "xdmac1_clk", .p = "mck1", .id = 23, }, 303cb783bbbSClaudiu Beznea { .n = "xdmac2_clk", .p = "mck1", .id = 24, }, 304cb783bbbSClaudiu Beznea { .n = "acc_clk", .p = "mck1", .id = 25, }, 305cb783bbbSClaudiu Beznea { .n = "aes_clk", .p = "mck1", .id = 27, }, 306cb783bbbSClaudiu Beznea { .n = "tzaesbasc_clk", .p = "mck1", .id = 28, }, 307cb783bbbSClaudiu Beznea { .n = "asrc_clk", .p = "mck1", .id = 30, .r = { .max = 200000000, }, }, 308cb783bbbSClaudiu Beznea { .n = "cpkcc_clk", .p = "mck0", .id = 32, }, 309cb783bbbSClaudiu Beznea { .n = "csi_clk", .p = "mck3", .id = 33, .r = { .max = 266000000, }, .chgp = 1, }, 310cb783bbbSClaudiu Beznea { .n = "csi2dc_clk", .p = "mck3", .id = 34, .r = { .max = 266000000, }, .chgp = 1, }, 311cb783bbbSClaudiu Beznea { .n = "eic_clk", .p = "mck1", .id = 37, }, 312cb783bbbSClaudiu Beznea { .n = "flex0_clk", .p = "mck1", .id = 38, }, 313cb783bbbSClaudiu Beznea { .n = "flex1_clk", .p = "mck1", .id = 39, }, 314cb783bbbSClaudiu Beznea { .n = "flex2_clk", .p = "mck1", .id = 40, }, 315cb783bbbSClaudiu Beznea { .n = "flex3_clk", .p = "mck1", .id = 41, }, 316cb783bbbSClaudiu Beznea { .n = "flex4_clk", .p = "mck1", .id = 42, }, 317cb783bbbSClaudiu Beznea { .n = "flex5_clk", .p = "mck1", .id = 43, }, 318cb783bbbSClaudiu Beznea { .n = "flex6_clk", .p = "mck1", .id = 44, }, 319cb783bbbSClaudiu Beznea { .n = "flex7_clk", .p = "mck1", .id = 45, }, 320cb783bbbSClaudiu Beznea { .n = "flex8_clk", .p = "mck1", .id = 46, }, 321cb783bbbSClaudiu Beznea { .n = "flex9_clk", .p = "mck1", .id = 47, }, 322cb783bbbSClaudiu Beznea { .n = "flex10_clk", .p = "mck1", .id = 48, }, 323cb783bbbSClaudiu Beznea { .n = "flex11_clk", .p = "mck1", .id = 49, }, 324cb783bbbSClaudiu Beznea { .n = "gmac0_clk", .p = "mck1", .id = 51, }, 325cb783bbbSClaudiu Beznea { .n = "gmac1_clk", .p = "mck1", .id = 52, }, 326cb783bbbSClaudiu Beznea { .n = "icm_clk", .p = "mck1", .id = 55, }, 327cb783bbbSClaudiu Beznea { .n = "isc_clk", .p = "mck3", .id = 56, .r = { .max = 266000000, }, .chgp = 1, }, 328cb783bbbSClaudiu Beznea { .n = "i2smcc0_clk", .p = "mck1", .id = 57, .r = { .max = 200000000, }, }, 329cb783bbbSClaudiu Beznea { .n = "i2smcc1_clk", .p = "mck1", .id = 58, .r = { .max = 200000000, }, }, 330cb783bbbSClaudiu Beznea { .n = "matrix_clk", .p = "mck1", .id = 60, }, 331cb783bbbSClaudiu Beznea { .n = "mcan0_clk", .p = "mck1", .id = 61, .r = { .max = 200000000, }, }, 332cb783bbbSClaudiu Beznea { .n = "mcan1_clk", .p = "mck1", .id = 62, .r = { .max = 200000000, }, }, 333cb783bbbSClaudiu Beznea { .n = "mcan2_clk", .p = "mck1", .id = 63, .r = { .max = 200000000, }, }, 334cb783bbbSClaudiu Beznea { .n = "mcan3_clk", .p = "mck1", .id = 64, .r = { .max = 200000000, }, }, 335cb783bbbSClaudiu Beznea { .n = "mcan4_clk", .p = "mck1", .id = 65, .r = { .max = 200000000, }, }, 336cb783bbbSClaudiu Beznea { .n = "mcan5_clk", .p = "mck1", .id = 66, .r = { .max = 200000000, }, }, 337cb783bbbSClaudiu Beznea { .n = "pdmc0_clk", .p = "mck1", .id = 68, .r = { .max = 200000000, }, }, 338cb783bbbSClaudiu Beznea { .n = "pdmc1_clk", .p = "mck1", .id = 69, .r = { .max = 200000000, }, }, 339cb783bbbSClaudiu Beznea { .n = "pit64b0_clk", .p = "mck1", .id = 70, }, 340cb783bbbSClaudiu Beznea { .n = "pit64b1_clk", .p = "mck1", .id = 71, }, 341cb783bbbSClaudiu Beznea { .n = "pit64b2_clk", .p = "mck1", .id = 72, }, 342cb783bbbSClaudiu Beznea { .n = "pit64b3_clk", .p = "mck1", .id = 73, }, 343cb783bbbSClaudiu Beznea { .n = "pit64b4_clk", .p = "mck1", .id = 74, }, 344cb783bbbSClaudiu Beznea { .n = "pit64b5_clk", .p = "mck1", .id = 75, }, 345cb783bbbSClaudiu Beznea { .n = "pwm_clk", .p = "mck1", .id = 77, }, 346cb783bbbSClaudiu Beznea { .n = "qspi0_clk", .p = "mck1", .id = 78, }, 347cb783bbbSClaudiu Beznea { .n = "qspi1_clk", .p = "mck1", .id = 79, }, 348cb783bbbSClaudiu Beznea { .n = "sdmmc0_clk", .p = "mck1", .id = 80, }, 349cb783bbbSClaudiu Beznea { .n = "sdmmc1_clk", .p = "mck1", .id = 81, }, 350cb783bbbSClaudiu Beznea { .n = "sdmmc2_clk", .p = "mck1", .id = 82, }, 351cb783bbbSClaudiu Beznea { .n = "sha_clk", .p = "mck1", .id = 83, }, 352cb783bbbSClaudiu Beznea { .n = "spdifrx_clk", .p = "mck1", .id = 84, .r = { .max = 200000000, }, }, 353cb783bbbSClaudiu Beznea { .n = "spdiftx_clk", .p = "mck1", .id = 85, .r = { .max = 200000000, }, }, 354cb783bbbSClaudiu Beznea { .n = "ssc0_clk", .p = "mck1", .id = 86, .r = { .max = 200000000, }, }, 355cb783bbbSClaudiu Beznea { .n = "ssc1_clk", .p = "mck1", .id = 87, .r = { .max = 200000000, }, }, 356cb783bbbSClaudiu Beznea { .n = "tcb0_ch0_clk", .p = "mck1", .id = 88, .r = { .max = 200000000, }, }, 357cb783bbbSClaudiu Beznea { .n = "tcb0_ch1_clk", .p = "mck1", .id = 89, .r = { .max = 200000000, }, }, 358cb783bbbSClaudiu Beznea { .n = "tcb0_ch2_clk", .p = "mck1", .id = 90, .r = { .max = 200000000, }, }, 359cb783bbbSClaudiu Beznea { .n = "tcb1_ch0_clk", .p = "mck1", .id = 91, .r = { .max = 200000000, }, }, 360cb783bbbSClaudiu Beznea { .n = "tcb1_ch1_clk", .p = "mck1", .id = 92, .r = { .max = 200000000, }, }, 361cb783bbbSClaudiu Beznea { .n = "tcb1_ch2_clk", .p = "mck1", .id = 93, .r = { .max = 200000000, }, }, 362cb783bbbSClaudiu Beznea { .n = "tcpca_clk", .p = "mck1", .id = 94, }, 363cb783bbbSClaudiu Beznea { .n = "tcpcb_clk", .p = "mck1", .id = 95, }, 364cb783bbbSClaudiu Beznea { .n = "tdes_clk", .p = "mck1", .id = 96, }, 365cb783bbbSClaudiu Beznea { .n = "trng_clk", .p = "mck1", .id = 97, }, 366cb783bbbSClaudiu Beznea { .n = "udphsa_clk", .p = "mck1", .id = 104, }, 367cb783bbbSClaudiu Beznea { .n = "udphsb_clk", .p = "mck1", .id = 105, }, 368cb783bbbSClaudiu Beznea { .n = "uhphs_clk", .p = "mck1", .id = 106, }, 369cb783bbbSClaudiu Beznea }; 370cb783bbbSClaudiu Beznea 371cb783bbbSClaudiu Beznea /** 372cb783bbbSClaudiu Beznea * Generic clock description 373cb783bbbSClaudiu Beznea * @n: clock name 374cb783bbbSClaudiu Beznea * @pp: PLL parents 375cb783bbbSClaudiu Beznea * @pp_mux_table: PLL parents mux table 376cb783bbbSClaudiu Beznea * @r: clock output range 377cb783bbbSClaudiu Beznea * @pp_chg_id: id in parrent array of changeable PLL parent 378cb783bbbSClaudiu Beznea * @pp_count: PLL parents count 379cb783bbbSClaudiu Beznea * @id: clock id 380cb783bbbSClaudiu Beznea */ 381cb783bbbSClaudiu Beznea static const struct { 382cb783bbbSClaudiu Beznea const char *n; 383cb783bbbSClaudiu Beznea const char *pp[8]; 384cb783bbbSClaudiu Beznea const char pp_mux_table[8]; 385cb783bbbSClaudiu Beznea struct clk_range r; 386cb783bbbSClaudiu Beznea int pp_chg_id; 387cb783bbbSClaudiu Beznea u8 pp_count; 388cb783bbbSClaudiu Beznea u8 id; 389cb783bbbSClaudiu Beznea } sama7g5_gck[] = { 390cb783bbbSClaudiu Beznea { .n = "adc_gclk", 391cb783bbbSClaudiu Beznea .id = 26, 392cb783bbbSClaudiu Beznea .r = { .max = 100000000, }, 393cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "imgpll_divpmcck", "audiopll_divpmcck", }, 394cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 7, 9, }, 395cb783bbbSClaudiu Beznea .pp_count = 3, 396cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 397cb783bbbSClaudiu Beznea 398cb783bbbSClaudiu Beznea { .n = "asrc_gclk", 399cb783bbbSClaudiu Beznea .id = 30, 400cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 401cb783bbbSClaudiu Beznea .pp = { "audiopll_divpmcck", }, 402cb783bbbSClaudiu Beznea .pp_mux_table = { 9, }, 403cb783bbbSClaudiu Beznea .pp_count = 1, 404cb783bbbSClaudiu Beznea .pp_chg_id = 4, }, 405cb783bbbSClaudiu Beznea 406cb783bbbSClaudiu Beznea { .n = "csi_gclk", 407cb783bbbSClaudiu Beznea .id = 33, 408cb783bbbSClaudiu Beznea .r = { .max = 27000000 }, 409cb783bbbSClaudiu Beznea .pp = { "ddrpll_divpmcck", "imgpll_divpmcck", }, 410cb783bbbSClaudiu Beznea .pp_mux_table = { 6, 7, }, 411cb783bbbSClaudiu Beznea .pp_count = 2, 412cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 413cb783bbbSClaudiu Beznea 414cb783bbbSClaudiu Beznea { .n = "flex0_gclk", 415cb783bbbSClaudiu Beznea .id = 38, 416cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 417cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 418cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 419cb783bbbSClaudiu Beznea .pp_count = 2, 420cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 421cb783bbbSClaudiu Beznea 422cb783bbbSClaudiu Beznea { .n = "flex1_gclk", 423cb783bbbSClaudiu Beznea .id = 39, 424cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 425cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 426cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 427cb783bbbSClaudiu Beznea .pp_count = 2, 428cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 429cb783bbbSClaudiu Beznea 430cb783bbbSClaudiu Beznea { .n = "flex2_gclk", 431cb783bbbSClaudiu Beznea .id = 40, 432cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 433cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 434cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 435cb783bbbSClaudiu Beznea .pp_count = 2, 436cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 437cb783bbbSClaudiu Beznea 438cb783bbbSClaudiu Beznea { .n = "flex3_gclk", 439cb783bbbSClaudiu Beznea .id = 41, 440cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 441cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 442cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 443cb783bbbSClaudiu Beznea .pp_count = 2, 444cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 445cb783bbbSClaudiu Beznea 446cb783bbbSClaudiu Beznea { .n = "flex4_gclk", 447cb783bbbSClaudiu Beznea .id = 42, 448cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 449cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 450cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 451cb783bbbSClaudiu Beznea .pp_count = 2, 452cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 453cb783bbbSClaudiu Beznea 454cb783bbbSClaudiu Beznea { .n = "flex5_gclk", 455cb783bbbSClaudiu Beznea .id = 43, 456cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 457cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 458cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 459cb783bbbSClaudiu Beznea .pp_count = 2, 460cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 461cb783bbbSClaudiu Beznea 462cb783bbbSClaudiu Beznea { .n = "flex6_gclk", 463cb783bbbSClaudiu Beznea .id = 44, 464cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 465cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 466cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 467cb783bbbSClaudiu Beznea .pp_count = 2, 468cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 469cb783bbbSClaudiu Beznea 470cb783bbbSClaudiu Beznea { .n = "flex7_gclk", 471cb783bbbSClaudiu Beznea .id = 45, 472cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 473cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 474cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 475cb783bbbSClaudiu Beznea .pp_count = 2, 476cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 477cb783bbbSClaudiu Beznea 478cb783bbbSClaudiu Beznea { .n = "flex8_gclk", 479cb783bbbSClaudiu Beznea .id = 46, 480cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 481cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 482cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 483cb783bbbSClaudiu Beznea .pp_count = 2, 484cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 485cb783bbbSClaudiu Beznea 486cb783bbbSClaudiu Beznea { .n = "flex9_gclk", 487cb783bbbSClaudiu Beznea .id = 47, 488cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 489cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 490cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 491cb783bbbSClaudiu Beznea .pp_count = 2, 492cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 493cb783bbbSClaudiu Beznea 494cb783bbbSClaudiu Beznea { .n = "flex10_gclk", 495cb783bbbSClaudiu Beznea .id = 48, 496cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 497cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 498cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 499cb783bbbSClaudiu Beznea .pp_count = 2, 500cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 501cb783bbbSClaudiu Beznea 502cb783bbbSClaudiu Beznea { .n = "flex11_gclk", 503cb783bbbSClaudiu Beznea .id = 49, 504cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 505cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 506cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 507cb783bbbSClaudiu Beznea .pp_count = 2, 508cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 509cb783bbbSClaudiu Beznea 510cb783bbbSClaudiu Beznea { .n = "gmac0_gclk", 511cb783bbbSClaudiu Beznea .id = 51, 512cb783bbbSClaudiu Beznea .r = { .max = 125000000 }, 513cb783bbbSClaudiu Beznea .pp = { "ethpll_divpmcck", }, 514cb783bbbSClaudiu Beznea .pp_mux_table = { 10, }, 515cb783bbbSClaudiu Beznea .pp_count = 1, 516cb783bbbSClaudiu Beznea .pp_chg_id = 4, }, 517cb783bbbSClaudiu Beznea 518cb783bbbSClaudiu Beznea { .n = "gmac1_gclk", 519cb783bbbSClaudiu Beznea .id = 52, 520cb783bbbSClaudiu Beznea .r = { .max = 50000000 }, 521cb783bbbSClaudiu Beznea .pp = { "ethpll_divpmcck", }, 522cb783bbbSClaudiu Beznea .pp_mux_table = { 10, }, 523cb783bbbSClaudiu Beznea .pp_count = 1, 524cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 525cb783bbbSClaudiu Beznea 526cb783bbbSClaudiu Beznea { .n = "gmac0_tsu_gclk", 527cb783bbbSClaudiu Beznea .id = 53, 528cb783bbbSClaudiu Beznea .r = { .max = 300000000 }, 529cb783bbbSClaudiu Beznea .pp = { "audiopll_divpmcck", "ethpll_divpmcck", }, 530cb783bbbSClaudiu Beznea .pp_mux_table = { 9, 10, }, 531cb783bbbSClaudiu Beznea .pp_count = 2, 532cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 533cb783bbbSClaudiu Beznea 534cb783bbbSClaudiu Beznea { .n = "gmac1_tsu_gclk", 535cb783bbbSClaudiu Beznea .id = 54, 536cb783bbbSClaudiu Beznea .r = { .max = 300000000 }, 537cb783bbbSClaudiu Beznea .pp = { "audiopll_divpmcck", "ethpll_divpmcck", }, 538cb783bbbSClaudiu Beznea .pp_mux_table = { 9, 10, }, 539cb783bbbSClaudiu Beznea .pp_count = 2, 540cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 541cb783bbbSClaudiu Beznea 542cb783bbbSClaudiu Beznea { .n = "i2smcc0_gclk", 543cb783bbbSClaudiu Beznea .id = 57, 544cb783bbbSClaudiu Beznea .r = { .max = 100000000 }, 545cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "audiopll_divpmcck", }, 546cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 9, }, 547cb783bbbSClaudiu Beznea .pp_count = 2, 548cb783bbbSClaudiu Beznea .pp_chg_id = 5, }, 549cb783bbbSClaudiu Beznea 550cb783bbbSClaudiu Beznea { .n = "i2smcc1_gclk", 551cb783bbbSClaudiu Beznea .id = 58, 552cb783bbbSClaudiu Beznea .r = { .max = 100000000 }, 553cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "audiopll_divpmcck", }, 554cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 9, }, 555cb783bbbSClaudiu Beznea .pp_count = 2, 556cb783bbbSClaudiu Beznea .pp_chg_id = 5, }, 557cb783bbbSClaudiu Beznea 558cb783bbbSClaudiu Beznea { .n = "mcan0_gclk", 559cb783bbbSClaudiu Beznea .id = 61, 560cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 561cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 562cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 563cb783bbbSClaudiu Beznea .pp_count = 2, 564cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 565cb783bbbSClaudiu Beznea 566cb783bbbSClaudiu Beznea { .n = "mcan1_gclk", 567cb783bbbSClaudiu Beznea .id = 62, 568cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 569cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 570cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 571cb783bbbSClaudiu Beznea .pp_count = 2, 572cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 573cb783bbbSClaudiu Beznea 574cb783bbbSClaudiu Beznea { .n = "mcan2_gclk", 575cb783bbbSClaudiu Beznea .id = 63, 576cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 577cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 578cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 579cb783bbbSClaudiu Beznea .pp_count = 2, 580cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 581cb783bbbSClaudiu Beznea 582cb783bbbSClaudiu Beznea { .n = "mcan3_gclk", 583cb783bbbSClaudiu Beznea .id = 64, 584cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 585cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 586cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 587cb783bbbSClaudiu Beznea .pp_count = 2, 588cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 589cb783bbbSClaudiu Beznea 590cb783bbbSClaudiu Beznea { .n = "mcan4_gclk", 591cb783bbbSClaudiu Beznea .id = 65, 592cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 593cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 594cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 595cb783bbbSClaudiu Beznea .pp_count = 2, 596cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 597cb783bbbSClaudiu Beznea 598cb783bbbSClaudiu Beznea { .n = "mcan5_gclk", 599cb783bbbSClaudiu Beznea .id = 66, 600cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 601cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 602cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 603cb783bbbSClaudiu Beznea .pp_count = 2, 604cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 605cb783bbbSClaudiu Beznea 606cb783bbbSClaudiu Beznea { .n = "pdmc0_gclk", 607cb783bbbSClaudiu Beznea .id = 68, 608cb783bbbSClaudiu Beznea .r = { .max = 50000000 }, 609cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 610cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 611cb783bbbSClaudiu Beznea .pp_count = 2, 612cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 613cb783bbbSClaudiu Beznea 614cb783bbbSClaudiu Beznea { .n = "pdmc1_gclk", 615cb783bbbSClaudiu Beznea .id = 69, 616cb783bbbSClaudiu Beznea .r = { .max = 50000000, }, 617cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 618cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 619cb783bbbSClaudiu Beznea .pp_count = 2, 620cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 621cb783bbbSClaudiu Beznea 622cb783bbbSClaudiu Beznea { .n = "pit64b0_gclk", 623cb783bbbSClaudiu Beznea .id = 70, 624cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 625cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck", 626cb783bbbSClaudiu Beznea "audiopll_divpmcck", "ethpll_divpmcck", }, 627cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 7, 8, 9, 10, }, 628cb783bbbSClaudiu Beznea .pp_count = 5, 629cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 630cb783bbbSClaudiu Beznea 631cb783bbbSClaudiu Beznea { .n = "pit64b1_gclk", 632cb783bbbSClaudiu Beznea .id = 71, 633cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 634cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck", 635cb783bbbSClaudiu Beznea "audiopll_divpmcck", "ethpll_divpmcck", }, 636cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 7, 8, 9, 10, }, 637cb783bbbSClaudiu Beznea .pp_count = 5, 638cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 639cb783bbbSClaudiu Beznea 640cb783bbbSClaudiu Beznea { .n = "pit64b2_gclk", 641cb783bbbSClaudiu Beznea .id = 72, 642cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 643cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck", 644cb783bbbSClaudiu Beznea "audiopll_divpmcck", "ethpll_divpmcck", }, 645cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 7, 8, 9, 10, }, 646cb783bbbSClaudiu Beznea .pp_count = 5, 647cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 648cb783bbbSClaudiu Beznea 649cb783bbbSClaudiu Beznea { .n = "pit64b3_gclk", 650cb783bbbSClaudiu Beznea .id = 73, 651cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 652cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck", 653cb783bbbSClaudiu Beznea "audiopll_divpmcck", "ethpll_divpmcck", }, 654cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 7, 8, 9, 10, }, 655cb783bbbSClaudiu Beznea .pp_count = 5, 656cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 657cb783bbbSClaudiu Beznea 658cb783bbbSClaudiu Beznea { .n = "pit64b4_gclk", 659cb783bbbSClaudiu Beznea .id = 74, 660cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 661cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck", 662cb783bbbSClaudiu Beznea "audiopll_divpmcck", "ethpll_divpmcck", }, 663cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 7, 8, 9, 10, }, 664cb783bbbSClaudiu Beznea .pp_count = 5, 665cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 666cb783bbbSClaudiu Beznea 667cb783bbbSClaudiu Beznea { .n = "pit64b5_gclk", 668cb783bbbSClaudiu Beznea .id = 75, 669cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 670cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck", 671cb783bbbSClaudiu Beznea "audiopll_divpmcck", "ethpll_divpmcck", }, 672cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 7, 8, 9, 10, }, 673cb783bbbSClaudiu Beznea .pp_count = 5, 674cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 675cb783bbbSClaudiu Beznea 676cb783bbbSClaudiu Beznea { .n = "qspi0_gclk", 677cb783bbbSClaudiu Beznea .id = 78, 678cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 679cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 680cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 681cb783bbbSClaudiu Beznea .pp_count = 2, 682cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 683cb783bbbSClaudiu Beznea 684cb783bbbSClaudiu Beznea { .n = "qspi1_gclk", 685cb783bbbSClaudiu Beznea .id = 79, 686cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 687cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 688cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 689cb783bbbSClaudiu Beznea .pp_count = 2, 690cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 691cb783bbbSClaudiu Beznea 692cb783bbbSClaudiu Beznea { .n = "sdmmc0_gclk", 693cb783bbbSClaudiu Beznea .id = 80, 694cb783bbbSClaudiu Beznea .r = { .max = 208000000 }, 695cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 696cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 697cb783bbbSClaudiu Beznea .pp_count = 2, 698cb783bbbSClaudiu Beznea .pp_chg_id = 5, }, 699cb783bbbSClaudiu Beznea 700cb783bbbSClaudiu Beznea { .n = "sdmmc1_gclk", 701cb783bbbSClaudiu Beznea .id = 81, 702cb783bbbSClaudiu Beznea .r = { .max = 208000000 }, 703cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 704cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 705cb783bbbSClaudiu Beznea .pp_count = 2, 706cb783bbbSClaudiu Beznea .pp_chg_id = 5, }, 707cb783bbbSClaudiu Beznea 708cb783bbbSClaudiu Beznea { .n = "sdmmc2_gclk", 709cb783bbbSClaudiu Beznea .id = 82, 710cb783bbbSClaudiu Beznea .r = { .max = 208000000 }, 711cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "baudpll_divpmcck", }, 712cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 8, }, 713cb783bbbSClaudiu Beznea .pp_count = 2, 714cb783bbbSClaudiu Beznea .pp_chg_id = 5, }, 715cb783bbbSClaudiu Beznea 716cb783bbbSClaudiu Beznea { .n = "spdifrx_gclk", 717cb783bbbSClaudiu Beznea .id = 84, 718cb783bbbSClaudiu Beznea .r = { .max = 150000000 }, 719cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "audiopll_divpmcck", }, 720cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 9, }, 721cb783bbbSClaudiu Beznea .pp_count = 2, 722cb783bbbSClaudiu Beznea .pp_chg_id = 5, }, 723cb783bbbSClaudiu Beznea 724cb783bbbSClaudiu Beznea { .n = "spdiftx_gclk", 725cb783bbbSClaudiu Beznea .id = 85, 726cb783bbbSClaudiu Beznea .r = { .max = 25000000 }, 727cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "audiopll_divpmcck", }, 728cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 9, }, 729cb783bbbSClaudiu Beznea .pp_count = 2, 730cb783bbbSClaudiu Beznea .pp_chg_id = 5, }, 731cb783bbbSClaudiu Beznea 732cb783bbbSClaudiu Beznea { .n = "tcb0_ch0_gclk", 733cb783bbbSClaudiu Beznea .id = 88, 734cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 735cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck", 736cb783bbbSClaudiu Beznea "audiopll_divpmcck", "ethpll_divpmcck", }, 737cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 7, 8, 9, 10, }, 738cb783bbbSClaudiu Beznea .pp_count = 5, 739cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 740cb783bbbSClaudiu Beznea 741cb783bbbSClaudiu Beznea { .n = "tcb1_ch0_gclk", 742cb783bbbSClaudiu Beznea .id = 91, 743cb783bbbSClaudiu Beznea .r = { .max = 200000000 }, 744cb783bbbSClaudiu Beznea .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck", 745cb783bbbSClaudiu Beznea "audiopll_divpmcck", "ethpll_divpmcck", }, 746cb783bbbSClaudiu Beznea .pp_mux_table = { 5, 7, 8, 9, 10, }, 747cb783bbbSClaudiu Beznea .pp_count = 5, 748cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 749cb783bbbSClaudiu Beznea 750cb783bbbSClaudiu Beznea { .n = "tcpca_gclk", 751cb783bbbSClaudiu Beznea .id = 94, 752cb783bbbSClaudiu Beznea .r = { .max = 32768, }, 753cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 754cb783bbbSClaudiu Beznea 755cb783bbbSClaudiu Beznea { .n = "tcpcb_gclk", 756cb783bbbSClaudiu Beznea .id = 95, 757cb783bbbSClaudiu Beznea .r = { .max = 32768, }, 758cb783bbbSClaudiu Beznea .pp_chg_id = INT_MIN, }, 759cb783bbbSClaudiu Beznea }; 760cb783bbbSClaudiu Beznea 761cb783bbbSClaudiu Beznea /* PLL output range. */ 762cb783bbbSClaudiu Beznea static const struct clk_range pll_outputs[] = { 763cb783bbbSClaudiu Beznea { .min = 2343750, .max = 1200000000 }, 764cb783bbbSClaudiu Beznea }; 765cb783bbbSClaudiu Beznea 766cb783bbbSClaudiu Beznea /* PLL characteristics. */ 767cb783bbbSClaudiu Beznea static const struct clk_pll_characteristics pll_characteristics = { 768cb783bbbSClaudiu Beznea .input = { .min = 12000000, .max = 50000000 }, 769cb783bbbSClaudiu Beznea .num_output = ARRAY_SIZE(pll_outputs), 770cb783bbbSClaudiu Beznea .output = pll_outputs, 771cb783bbbSClaudiu Beznea }; 772cb783bbbSClaudiu Beznea 773cb783bbbSClaudiu Beznea /* MCK0 characteristics. */ 774cb783bbbSClaudiu Beznea static const struct clk_master_characteristics mck0_characteristics = { 775cb783bbbSClaudiu Beznea .output = { .min = 140000000, .max = 200000000 }, 776cb783bbbSClaudiu Beznea .divisors = { 1, 2, 4, 3 }, 777cb783bbbSClaudiu Beznea .have_div3_pres = 1, 778cb783bbbSClaudiu Beznea }; 779cb783bbbSClaudiu Beznea 780cb783bbbSClaudiu Beznea /* MCK0 layout. */ 781cb783bbbSClaudiu Beznea static const struct clk_master_layout mck0_layout = { 782cb783bbbSClaudiu Beznea .mask = 0x373, 783cb783bbbSClaudiu Beznea .pres_shift = 4, 784cb783bbbSClaudiu Beznea .offset = 0x28, 785cb783bbbSClaudiu Beznea }; 786cb783bbbSClaudiu Beznea 787cb783bbbSClaudiu Beznea /* Programmable clock layout. */ 788cb783bbbSClaudiu Beznea static const struct clk_programmable_layout programmable_layout = { 789cb783bbbSClaudiu Beznea .pres_mask = 0xff, 790cb783bbbSClaudiu Beznea .pres_shift = 8, 791cb783bbbSClaudiu Beznea .css_mask = 0x1f, 792cb783bbbSClaudiu Beznea .have_slck_mck = 0, 793cb783bbbSClaudiu Beznea .is_pres_direct = 1, 794cb783bbbSClaudiu Beznea }; 795cb783bbbSClaudiu Beznea 796cb783bbbSClaudiu Beznea /* Peripheral clock layout. */ 797cb783bbbSClaudiu Beznea static const struct clk_pcr_layout sama7g5_pcr_layout = { 798cb783bbbSClaudiu Beznea .offset = 0x88, 799cb783bbbSClaudiu Beznea .cmd = BIT(31), 800cb783bbbSClaudiu Beznea .gckcss_mask = GENMASK(12, 8), 801cb783bbbSClaudiu Beznea .pid_mask = GENMASK(6, 0), 802cb783bbbSClaudiu Beznea }; 803cb783bbbSClaudiu Beznea 804cb783bbbSClaudiu Beznea static void __init sama7g5_pmc_setup(struct device_node *np) 805cb783bbbSClaudiu Beznea { 806cb783bbbSClaudiu Beznea const char *td_slck_name, *md_slck_name, *mainxtal_name; 807cb783bbbSClaudiu Beznea struct pmc_data *sama7g5_pmc; 808cb783bbbSClaudiu Beznea const char *parent_names[10]; 809cb783bbbSClaudiu Beznea void **alloc_mem = NULL; 810cb783bbbSClaudiu Beznea int alloc_mem_size = 0; 811cb783bbbSClaudiu Beznea struct regmap *regmap; 812cb783bbbSClaudiu Beznea struct clk_hw *hw; 813cb783bbbSClaudiu Beznea bool bypass; 814cb783bbbSClaudiu Beznea int i, j; 815cb783bbbSClaudiu Beznea 816cb783bbbSClaudiu Beznea i = of_property_match_string(np, "clock-names", "td_slck"); 817cb783bbbSClaudiu Beznea if (i < 0) 818cb783bbbSClaudiu Beznea return; 819cb783bbbSClaudiu Beznea 820cb783bbbSClaudiu Beznea td_slck_name = of_clk_get_parent_name(np, i); 821cb783bbbSClaudiu Beznea 822cb783bbbSClaudiu Beznea i = of_property_match_string(np, "clock-names", "md_slck"); 823cb783bbbSClaudiu Beznea if (i < 0) 824cb783bbbSClaudiu Beznea return; 825cb783bbbSClaudiu Beznea 826cb783bbbSClaudiu Beznea md_slck_name = of_clk_get_parent_name(np, i); 827cb783bbbSClaudiu Beznea 828cb783bbbSClaudiu Beznea i = of_property_match_string(np, "clock-names", "main_xtal"); 829cb783bbbSClaudiu Beznea if (i < 0) 830cb783bbbSClaudiu Beznea return; 831cb783bbbSClaudiu Beznea 832cb783bbbSClaudiu Beznea mainxtal_name = of_clk_get_parent_name(np, i); 833cb783bbbSClaudiu Beznea 834cb783bbbSClaudiu Beznea regmap = device_node_to_regmap(np); 835cb783bbbSClaudiu Beznea if (IS_ERR(regmap)) 836cb783bbbSClaudiu Beznea return; 837cb783bbbSClaudiu Beznea 838*3d86ee17SEugen Hristev sama7g5_pmc = pmc_data_allocate(PMC_ETHPLL + 1, 839cb783bbbSClaudiu Beznea nck(sama7g5_systemck), 840cb783bbbSClaudiu Beznea nck(sama7g5_periphck), 84191274497SClaudiu Beznea nck(sama7g5_gck), 8); 842cb783bbbSClaudiu Beznea if (!sama7g5_pmc) 843cb783bbbSClaudiu Beznea return; 844cb783bbbSClaudiu Beznea 845cb783bbbSClaudiu Beznea alloc_mem = kmalloc(sizeof(void *) * 846cb783bbbSClaudiu Beznea (ARRAY_SIZE(sama7g5_mckx) + ARRAY_SIZE(sama7g5_gck)), 847cb783bbbSClaudiu Beznea GFP_KERNEL); 848cb783bbbSClaudiu Beznea if (!alloc_mem) 849cb783bbbSClaudiu Beznea goto err_free; 850cb783bbbSClaudiu Beznea 851cb783bbbSClaudiu Beznea hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, 852cb783bbbSClaudiu Beznea 50000000); 853cb783bbbSClaudiu Beznea if (IS_ERR(hw)) 854cb783bbbSClaudiu Beznea goto err_free; 855cb783bbbSClaudiu Beznea 856cb783bbbSClaudiu Beznea bypass = of_property_read_bool(np, "atmel,osc-bypass"); 857cb783bbbSClaudiu Beznea 858cb783bbbSClaudiu Beznea hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, 859cb783bbbSClaudiu Beznea bypass); 860cb783bbbSClaudiu Beznea if (IS_ERR(hw)) 861cb783bbbSClaudiu Beznea goto err_free; 862cb783bbbSClaudiu Beznea 863cb783bbbSClaudiu Beznea parent_names[0] = "main_rc_osc"; 864cb783bbbSClaudiu Beznea parent_names[1] = "main_osc"; 865cb783bbbSClaudiu Beznea hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2); 866cb783bbbSClaudiu Beznea if (IS_ERR(hw)) 867cb783bbbSClaudiu Beznea goto err_free; 868cb783bbbSClaudiu Beznea 869cb783bbbSClaudiu Beznea sama7g5_pmc->chws[PMC_MAIN] = hw; 870cb783bbbSClaudiu Beznea 871cb783bbbSClaudiu Beznea for (i = 0; i < PLL_ID_MAX; i++) { 872cb783bbbSClaudiu Beznea for (j = 0; j < 3; j++) { 873cb783bbbSClaudiu Beznea struct clk_hw *parent_hw; 874cb783bbbSClaudiu Beznea 875cb783bbbSClaudiu Beznea if (!sama7g5_plls[i][j].n) 876cb783bbbSClaudiu Beznea continue; 877cb783bbbSClaudiu Beznea 878cb783bbbSClaudiu Beznea switch (sama7g5_plls[i][j].t) { 879cb783bbbSClaudiu Beznea case PLL_TYPE_FRAC: 880cb783bbbSClaudiu Beznea if (!strcmp(sama7g5_plls[i][j].p, "mainck")) 881cb783bbbSClaudiu Beznea parent_hw = sama7g5_pmc->chws[PMC_MAIN]; 882cb783bbbSClaudiu Beznea else 883cb783bbbSClaudiu Beznea parent_hw = __clk_get_hw(of_clk_get_by_name(np, 884cb783bbbSClaudiu Beznea sama7g5_plls[i][j].p)); 885cb783bbbSClaudiu Beznea 886cb783bbbSClaudiu Beznea hw = sam9x60_clk_register_frac_pll(regmap, 887cb783bbbSClaudiu Beznea &pmc_pll_lock, sama7g5_plls[i][j].n, 888cb783bbbSClaudiu Beznea sama7g5_plls[i][j].p, parent_hw, i, 889cb783bbbSClaudiu Beznea &pll_characteristics, 890cb783bbbSClaudiu Beznea sama7g5_plls[i][j].l, 891cb783bbbSClaudiu Beznea sama7g5_plls[i][j].c); 892cb783bbbSClaudiu Beznea break; 893cb783bbbSClaudiu Beznea 894cb783bbbSClaudiu Beznea case PLL_TYPE_DIV: 895cb783bbbSClaudiu Beznea hw = sam9x60_clk_register_div_pll(regmap, 896cb783bbbSClaudiu Beznea &pmc_pll_lock, sama7g5_plls[i][j].n, 897cb783bbbSClaudiu Beznea sama7g5_plls[i][j].p, i, 898cb783bbbSClaudiu Beznea &pll_characteristics, 899cb783bbbSClaudiu Beznea sama7g5_plls[i][j].l, 900cb783bbbSClaudiu Beznea sama7g5_plls[i][j].c); 901cb783bbbSClaudiu Beznea break; 902cb783bbbSClaudiu Beznea 903cb783bbbSClaudiu Beznea default: 904cb783bbbSClaudiu Beznea continue; 905cb783bbbSClaudiu Beznea } 906cb783bbbSClaudiu Beznea 907cb783bbbSClaudiu Beznea if (IS_ERR(hw)) 908cb783bbbSClaudiu Beznea goto err_free; 909cb783bbbSClaudiu Beznea 910cb783bbbSClaudiu Beznea if (sama7g5_plls[i][j].eid) 911cb783bbbSClaudiu Beznea sama7g5_pmc->chws[sama7g5_plls[i][j].eid] = hw; 912cb783bbbSClaudiu Beznea } 913cb783bbbSClaudiu Beznea } 914cb783bbbSClaudiu Beznea 915cb783bbbSClaudiu Beznea parent_names[0] = md_slck_name; 916cb783bbbSClaudiu Beznea parent_names[1] = "mainck"; 917cb783bbbSClaudiu Beznea parent_names[2] = "cpupll_divpmcck"; 918cb783bbbSClaudiu Beznea parent_names[3] = "syspll_divpmcck"; 919cb783bbbSClaudiu Beznea hw = at91_clk_register_master(regmap, "mck0", 4, parent_names, 920cb783bbbSClaudiu Beznea &mck0_layout, &mck0_characteristics); 921cb783bbbSClaudiu Beznea if (IS_ERR(hw)) 922cb783bbbSClaudiu Beznea goto err_free; 923cb783bbbSClaudiu Beznea 924cb783bbbSClaudiu Beznea sama7g5_pmc->chws[PMC_MCK] = hw; 925cb783bbbSClaudiu Beznea 926cb783bbbSClaudiu Beznea parent_names[0] = md_slck_name; 927cb783bbbSClaudiu Beznea parent_names[1] = td_slck_name; 928cb783bbbSClaudiu Beznea parent_names[2] = "mainck"; 929cb783bbbSClaudiu Beznea parent_names[3] = "mck0"; 930cb783bbbSClaudiu Beznea for (i = 0; i < ARRAY_SIZE(sama7g5_mckx); i++) { 931cb783bbbSClaudiu Beznea u8 num_parents = 4 + sama7g5_mckx[i].ep_count; 932cb783bbbSClaudiu Beznea u32 *mux_table; 933cb783bbbSClaudiu Beznea 934cb783bbbSClaudiu Beznea mux_table = kmalloc_array(num_parents, sizeof(*mux_table), 935cb783bbbSClaudiu Beznea GFP_KERNEL); 936cb783bbbSClaudiu Beznea if (!mux_table) 937cb783bbbSClaudiu Beznea goto err_free; 938cb783bbbSClaudiu Beznea 939cb783bbbSClaudiu Beznea SAMA7G5_INIT_TABLE(mux_table, 4); 940cb783bbbSClaudiu Beznea SAMA7G5_FILL_TABLE(&mux_table[4], sama7g5_mckx[i].ep_mux_table, 941cb783bbbSClaudiu Beznea sama7g5_mckx[i].ep_count); 942cb783bbbSClaudiu Beznea SAMA7G5_FILL_TABLE(&parent_names[4], sama7g5_mckx[i].ep, 943cb783bbbSClaudiu Beznea sama7g5_mckx[i].ep_count); 944cb783bbbSClaudiu Beznea 945cb783bbbSClaudiu Beznea hw = at91_clk_sama7g5_register_master(regmap, sama7g5_mckx[i].n, 946cb783bbbSClaudiu Beznea num_parents, parent_names, mux_table, 947cb783bbbSClaudiu Beznea &pmc_mckX_lock, sama7g5_mckx[i].id, 948cb783bbbSClaudiu Beznea sama7g5_mckx[i].c, 949cb783bbbSClaudiu Beznea sama7g5_mckx[i].ep_chg_id); 950cb783bbbSClaudiu Beznea if (IS_ERR(hw)) 951cb783bbbSClaudiu Beznea goto err_free; 952cb783bbbSClaudiu Beznea 953cb783bbbSClaudiu Beznea alloc_mem[alloc_mem_size++] = mux_table; 954cb783bbbSClaudiu Beznea } 955cb783bbbSClaudiu Beznea 956cb783bbbSClaudiu Beznea hw = at91_clk_sama7g5_register_utmi(regmap, "utmick", "main_xtal"); 957cb783bbbSClaudiu Beznea if (IS_ERR(hw)) 958cb783bbbSClaudiu Beznea goto err_free; 959cb783bbbSClaudiu Beznea 960cb783bbbSClaudiu Beznea sama7g5_pmc->chws[PMC_UTMI] = hw; 961cb783bbbSClaudiu Beznea 962cb783bbbSClaudiu Beznea parent_names[0] = md_slck_name; 963cb783bbbSClaudiu Beznea parent_names[1] = td_slck_name; 964cb783bbbSClaudiu Beznea parent_names[2] = "mainck"; 965cb783bbbSClaudiu Beznea parent_names[3] = "mck0"; 966cb783bbbSClaudiu Beznea parent_names[4] = "syspll_divpmcck"; 967cb783bbbSClaudiu Beznea parent_names[5] = "ddrpll_divpmcck"; 968cb783bbbSClaudiu Beznea parent_names[6] = "imgpll_divpmcck"; 969cb783bbbSClaudiu Beznea parent_names[7] = "baudpll_divpmcck"; 970cb783bbbSClaudiu Beznea parent_names[8] = "audiopll_divpmcck"; 971cb783bbbSClaudiu Beznea parent_names[9] = "ethpll_divpmcck"; 972cb783bbbSClaudiu Beznea for (i = 0; i < 8; i++) { 973cb783bbbSClaudiu Beznea char name[6]; 974cb783bbbSClaudiu Beznea 975cb783bbbSClaudiu Beznea snprintf(name, sizeof(name), "prog%d", i); 976cb783bbbSClaudiu Beznea 977cb783bbbSClaudiu Beznea hw = at91_clk_register_programmable(regmap, name, parent_names, 978cb783bbbSClaudiu Beznea 10, i, 979cb783bbbSClaudiu Beznea &programmable_layout, 980cb783bbbSClaudiu Beznea sama7g5_prog_mux_table); 981cb783bbbSClaudiu Beznea if (IS_ERR(hw)) 982cb783bbbSClaudiu Beznea goto err_free; 98391274497SClaudiu Beznea 98491274497SClaudiu Beznea sama7g5_pmc->pchws[i] = hw; 985cb783bbbSClaudiu Beznea } 986cb783bbbSClaudiu Beznea 987cb783bbbSClaudiu Beznea for (i = 0; i < ARRAY_SIZE(sama7g5_systemck); i++) { 988cb783bbbSClaudiu Beznea hw = at91_clk_register_system(regmap, sama7g5_systemck[i].n, 989cb783bbbSClaudiu Beznea sama7g5_systemck[i].p, 990cb783bbbSClaudiu Beznea sama7g5_systemck[i].id); 991cb783bbbSClaudiu Beznea if (IS_ERR(hw)) 992cb783bbbSClaudiu Beznea goto err_free; 993cb783bbbSClaudiu Beznea 994cb783bbbSClaudiu Beznea sama7g5_pmc->shws[sama7g5_systemck[i].id] = hw; 995cb783bbbSClaudiu Beznea } 996cb783bbbSClaudiu Beznea 997cb783bbbSClaudiu Beznea for (i = 0; i < ARRAY_SIZE(sama7g5_periphck); i++) { 998cb783bbbSClaudiu Beznea hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, 999cb783bbbSClaudiu Beznea &sama7g5_pcr_layout, 1000cb783bbbSClaudiu Beznea sama7g5_periphck[i].n, 1001cb783bbbSClaudiu Beznea sama7g5_periphck[i].p, 1002cb783bbbSClaudiu Beznea sama7g5_periphck[i].id, 1003cb783bbbSClaudiu Beznea &sama7g5_periphck[i].r, 1004cb783bbbSClaudiu Beznea sama7g5_periphck[i].chgp ? 0 : 1005cb783bbbSClaudiu Beznea INT_MIN); 1006cb783bbbSClaudiu Beznea if (IS_ERR(hw)) 1007cb783bbbSClaudiu Beznea goto err_free; 1008cb783bbbSClaudiu Beznea 1009cb783bbbSClaudiu Beznea sama7g5_pmc->phws[sama7g5_periphck[i].id] = hw; 1010cb783bbbSClaudiu Beznea } 1011cb783bbbSClaudiu Beznea 1012cb783bbbSClaudiu Beznea parent_names[0] = md_slck_name; 1013cb783bbbSClaudiu Beznea parent_names[1] = td_slck_name; 1014cb783bbbSClaudiu Beznea parent_names[2] = "mainck"; 1015cb783bbbSClaudiu Beznea parent_names[3] = "mck0"; 1016cb783bbbSClaudiu Beznea for (i = 0; i < ARRAY_SIZE(sama7g5_gck); i++) { 1017cb783bbbSClaudiu Beznea u8 num_parents = 4 + sama7g5_gck[i].pp_count; 1018cb783bbbSClaudiu Beznea u32 *mux_table; 1019cb783bbbSClaudiu Beznea 1020cb783bbbSClaudiu Beznea mux_table = kmalloc_array(num_parents, sizeof(*mux_table), 1021cb783bbbSClaudiu Beznea GFP_KERNEL); 1022cb783bbbSClaudiu Beznea if (!mux_table) 1023cb783bbbSClaudiu Beznea goto err_free; 1024cb783bbbSClaudiu Beznea 1025cb783bbbSClaudiu Beznea SAMA7G5_INIT_TABLE(mux_table, 4); 1026cb783bbbSClaudiu Beznea SAMA7G5_FILL_TABLE(&mux_table[4], sama7g5_gck[i].pp_mux_table, 1027cb783bbbSClaudiu Beznea sama7g5_gck[i].pp_count); 1028cb783bbbSClaudiu Beznea SAMA7G5_FILL_TABLE(&parent_names[4], sama7g5_gck[i].pp, 1029cb783bbbSClaudiu Beznea sama7g5_gck[i].pp_count); 1030cb783bbbSClaudiu Beznea 1031cb783bbbSClaudiu Beznea hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, 1032cb783bbbSClaudiu Beznea &sama7g5_pcr_layout, 1033cb783bbbSClaudiu Beznea sama7g5_gck[i].n, 1034cb783bbbSClaudiu Beznea parent_names, mux_table, 1035cb783bbbSClaudiu Beznea num_parents, 1036cb783bbbSClaudiu Beznea sama7g5_gck[i].id, 1037cb783bbbSClaudiu Beznea &sama7g5_gck[i].r, 1038cb783bbbSClaudiu Beznea sama7g5_gck[i].pp_chg_id); 1039cb783bbbSClaudiu Beznea if (IS_ERR(hw)) 1040cb783bbbSClaudiu Beznea goto err_free; 1041cb783bbbSClaudiu Beznea 1042cb783bbbSClaudiu Beznea sama7g5_pmc->ghws[sama7g5_gck[i].id] = hw; 1043cb783bbbSClaudiu Beznea alloc_mem[alloc_mem_size++] = mux_table; 1044cb783bbbSClaudiu Beznea } 1045cb783bbbSClaudiu Beznea 1046cb783bbbSClaudiu Beznea of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sama7g5_pmc); 1047cb783bbbSClaudiu Beznea 1048cb783bbbSClaudiu Beznea return; 1049cb783bbbSClaudiu Beznea 1050cb783bbbSClaudiu Beznea err_free: 1051cb783bbbSClaudiu Beznea if (alloc_mem) { 1052cb783bbbSClaudiu Beznea for (i = 0; i < alloc_mem_size; i++) 1053cb783bbbSClaudiu Beznea kfree(alloc_mem[i]); 1054cb783bbbSClaudiu Beznea kfree(alloc_mem); 1055cb783bbbSClaudiu Beznea } 1056cb783bbbSClaudiu Beznea 105791274497SClaudiu Beznea kfree(sama7g5_pmc); 1058cb783bbbSClaudiu Beznea } 1059cb783bbbSClaudiu Beznea 1060cb783bbbSClaudiu Beznea /* Some clks are used for a clocksource */ 1061cb783bbbSClaudiu Beznea CLK_OF_DECLARE(sama7g5_pmc, "microchip,sama7g5-pmc", sama7g5_pmc_setup); 1062