1 // SPDX-License-Identifier: GPL-2.0 2 #include <linux/clk-provider.h> 3 #include <linux/mfd/syscon.h> 4 #include <linux/slab.h> 5 6 #include <dt-bindings/clock/at91.h> 7 8 #include "pmc.h" 9 10 static const struct clk_master_characteristics mck_characteristics = { 11 .output = { .min = 125000000, .max = 200000000 }, 12 .divisors = { 1, 2, 4, 3 }, 13 }; 14 15 static u8 plla_out[] = { 0 }; 16 17 static u16 plla_icpll[] = { 0 }; 18 19 static const struct clk_range plla_outputs[] = { 20 { .min = 600000000, .max = 1200000000 }, 21 }; 22 23 static const struct clk_pll_characteristics plla_characteristics = { 24 .input = { .min = 12000000, .max = 12000000 }, 25 .num_output = ARRAY_SIZE(plla_outputs), 26 .output = plla_outputs, 27 .icpll = plla_icpll, 28 .out = plla_out, 29 }; 30 31 static const struct clk_pcr_layout sama5d4_pcr_layout = { 32 .offset = 0x10c, 33 .cmd = BIT(12), 34 .pid_mask = GENMASK(6, 0), 35 }; 36 37 static const struct { 38 char *n; 39 char *p; 40 u8 id; 41 } sama5d4_systemck[] = { 42 { .n = "ddrck", .p = "masterck", .id = 2 }, 43 { .n = "lcdck", .p = "masterck", .id = 3 }, 44 { .n = "smdck", .p = "smdclk", .id = 4 }, 45 { .n = "uhpck", .p = "usbck", .id = 6 }, 46 { .n = "udpck", .p = "usbck", .id = 7 }, 47 { .n = "pck0", .p = "prog0", .id = 8 }, 48 { .n = "pck1", .p = "prog1", .id = 9 }, 49 { .n = "pck2", .p = "prog2", .id = 10 }, 50 }; 51 52 static const struct { 53 char *n; 54 u8 id; 55 } sama5d4_periph32ck[] = { 56 { .n = "pioD_clk", .id = 5 }, 57 { .n = "usart0_clk", .id = 6 }, 58 { .n = "usart1_clk", .id = 7 }, 59 { .n = "icm_clk", .id = 9 }, 60 { .n = "aes_clk", .id = 12 }, 61 { .n = "tdes_clk", .id = 14 }, 62 { .n = "sha_clk", .id = 15 }, 63 { .n = "matrix1_clk", .id = 17 }, 64 { .n = "hsmc_clk", .id = 22 }, 65 { .n = "pioA_clk", .id = 23 }, 66 { .n = "pioB_clk", .id = 24 }, 67 { .n = "pioC_clk", .id = 25 }, 68 { .n = "pioE_clk", .id = 26 }, 69 { .n = "uart0_clk", .id = 27 }, 70 { .n = "uart1_clk", .id = 28 }, 71 { .n = "usart2_clk", .id = 29 }, 72 { .n = "usart3_clk", .id = 30 }, 73 { .n = "usart4_clk", .id = 31 }, 74 { .n = "twi0_clk", .id = 32 }, 75 { .n = "twi1_clk", .id = 33 }, 76 { .n = "twi2_clk", .id = 34 }, 77 { .n = "mci0_clk", .id = 35 }, 78 { .n = "mci1_clk", .id = 36 }, 79 { .n = "spi0_clk", .id = 37 }, 80 { .n = "spi1_clk", .id = 38 }, 81 { .n = "spi2_clk", .id = 39 }, 82 { .n = "tcb0_clk", .id = 40 }, 83 { .n = "tcb1_clk", .id = 41 }, 84 { .n = "tcb2_clk", .id = 42 }, 85 { .n = "pwm_clk", .id = 43 }, 86 { .n = "adc_clk", .id = 44 }, 87 { .n = "dbgu_clk", .id = 45 }, 88 { .n = "uhphs_clk", .id = 46 }, 89 { .n = "udphs_clk", .id = 47 }, 90 { .n = "ssc0_clk", .id = 48 }, 91 { .n = "ssc1_clk", .id = 49 }, 92 { .n = "trng_clk", .id = 53 }, 93 { .n = "macb0_clk", .id = 54 }, 94 { .n = "macb1_clk", .id = 55 }, 95 { .n = "fuse_clk", .id = 57 }, 96 { .n = "securam_clk", .id = 59 }, 97 { .n = "smd_clk", .id = 61 }, 98 { .n = "twi3_clk", .id = 62 }, 99 { .n = "catb_clk", .id = 63 }, 100 }; 101 102 static const struct { 103 char *n; 104 u8 id; 105 } sama5d4_periphck[] = { 106 { .n = "dma0_clk", .id = 8 }, 107 { .n = "cpkcc_clk", .id = 10 }, 108 { .n = "aesb_clk", .id = 13 }, 109 { .n = "mpddr_clk", .id = 16 }, 110 { .n = "matrix0_clk", .id = 18 }, 111 { .n = "vdec_clk", .id = 19 }, 112 { .n = "dma1_clk", .id = 50 }, 113 { .n = "lcdc_clk", .id = 51 }, 114 { .n = "isi_clk", .id = 52 }, 115 }; 116 117 static void __init sama5d4_pmc_setup(struct device_node *np) 118 { 119 struct clk_range range = CLK_RANGE(0, 0); 120 const char *slck_name, *mainxtal_name; 121 struct pmc_data *sama5d4_pmc; 122 const char *parent_names[5]; 123 struct regmap *regmap; 124 struct clk_hw *hw; 125 int i; 126 bool bypass; 127 128 i = of_property_match_string(np, "clock-names", "slow_clk"); 129 if (i < 0) 130 return; 131 132 slck_name = of_clk_get_parent_name(np, i); 133 134 i = of_property_match_string(np, "clock-names", "main_xtal"); 135 if (i < 0) 136 return; 137 mainxtal_name = of_clk_get_parent_name(np, i); 138 139 regmap = syscon_node_to_regmap(np); 140 if (IS_ERR(regmap)) 141 return; 142 143 sama5d4_pmc = pmc_data_allocate(PMC_MCK2 + 1, 144 nck(sama5d4_systemck), 145 nck(sama5d4_periph32ck), 0); 146 if (!sama5d4_pmc) 147 return; 148 149 hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, 150 100000000); 151 if (IS_ERR(hw)) 152 goto err_free; 153 154 bypass = of_property_read_bool(np, "atmel,osc-bypass"); 155 156 hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, 157 bypass); 158 if (IS_ERR(hw)) 159 goto err_free; 160 161 parent_names[0] = "main_rc_osc"; 162 parent_names[1] = "main_osc"; 163 hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2); 164 if (IS_ERR(hw)) 165 goto err_free; 166 167 hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0, 168 &sama5d3_pll_layout, &plla_characteristics); 169 if (IS_ERR(hw)) 170 goto err_free; 171 172 hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack"); 173 if (IS_ERR(hw)) 174 goto err_free; 175 176 hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck"); 177 if (IS_ERR(hw)) 178 goto err_free; 179 180 sama5d4_pmc->chws[PMC_UTMI] = hw; 181 182 parent_names[0] = slck_name; 183 parent_names[1] = "mainck"; 184 parent_names[2] = "plladivck"; 185 parent_names[3] = "utmick"; 186 hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, 187 &at91sam9x5_master_layout, 188 &mck_characteristics); 189 if (IS_ERR(hw)) 190 goto err_free; 191 192 sama5d4_pmc->chws[PMC_MCK] = hw; 193 194 hw = at91_clk_register_h32mx(regmap, "h32mxck", "masterck"); 195 if (IS_ERR(hw)) 196 goto err_free; 197 198 sama5d4_pmc->chws[PMC_MCK2] = hw; 199 200 parent_names[0] = "plladivck"; 201 parent_names[1] = "utmick"; 202 hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2); 203 if (IS_ERR(hw)) 204 goto err_free; 205 206 parent_names[0] = "plladivck"; 207 parent_names[1] = "utmick"; 208 hw = at91sam9x5_clk_register_smd(regmap, "smdclk", parent_names, 2); 209 if (IS_ERR(hw)) 210 goto err_free; 211 212 parent_names[0] = slck_name; 213 parent_names[1] = "mainck"; 214 parent_names[2] = "plladivck"; 215 parent_names[3] = "utmick"; 216 parent_names[4] = "masterck"; 217 for (i = 0; i < 3; i++) { 218 char name[6]; 219 220 snprintf(name, sizeof(name), "prog%d", i); 221 222 hw = at91_clk_register_programmable(regmap, name, 223 parent_names, 5, i, 224 &at91sam9x5_programmable_layout); 225 if (IS_ERR(hw)) 226 goto err_free; 227 } 228 229 for (i = 0; i < ARRAY_SIZE(sama5d4_systemck); i++) { 230 hw = at91_clk_register_system(regmap, sama5d4_systemck[i].n, 231 sama5d4_systemck[i].p, 232 sama5d4_systemck[i].id); 233 if (IS_ERR(hw)) 234 goto err_free; 235 236 sama5d4_pmc->shws[sama5d4_systemck[i].id] = hw; 237 } 238 239 for (i = 0; i < ARRAY_SIZE(sama5d4_periphck); i++) { 240 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, 241 &sama5d4_pcr_layout, 242 sama5d4_periphck[i].n, 243 "masterck", 244 sama5d4_periphck[i].id, 245 &range); 246 if (IS_ERR(hw)) 247 goto err_free; 248 249 sama5d4_pmc->phws[sama5d4_periphck[i].id] = hw; 250 } 251 252 for (i = 0; i < ARRAY_SIZE(sama5d4_periph32ck); i++) { 253 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, 254 &sama5d4_pcr_layout, 255 sama5d4_periph32ck[i].n, 256 "h32mxck", 257 sama5d4_periph32ck[i].id, 258 &range); 259 if (IS_ERR(hw)) 260 goto err_free; 261 262 sama5d4_pmc->phws[sama5d4_periph32ck[i].id] = hw; 263 } 264 265 of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sama5d4_pmc); 266 267 return; 268 269 err_free: 270 pmc_data_free(sama5d4_pmc); 271 } 272 CLK_OF_DECLARE_DRIVER(sama5d4_pmc, "atmel,sama5d4-pmc", sama5d4_pmc_setup); 273