1 // SPDX-License-Identifier: GPL-2.0 2 #include <linux/clk-provider.h> 3 #include <linux/mfd/syscon.h> 4 #include <linux/slab.h> 5 6 #include <dt-bindings/clock/at91.h> 7 8 #include "pmc.h" 9 10 static DEFINE_SPINLOCK(mck_lock); 11 12 static const struct clk_master_characteristics mck_characteristics = { 13 .output = { .min = 0, .max = 166000000 }, 14 .divisors = { 1, 2, 4, 3 }, 15 }; 16 17 static u8 plla_out[] = { 0 }; 18 19 static u16 plla_icpll[] = { 0 }; 20 21 static const struct clk_range plla_outputs[] = { 22 { .min = 400000000, .max = 1000000000 }, 23 }; 24 25 static const struct clk_pll_characteristics plla_characteristics = { 26 .input = { .min = 8000000, .max = 50000000 }, 27 .num_output = ARRAY_SIZE(plla_outputs), 28 .output = plla_outputs, 29 .icpll = plla_icpll, 30 .out = plla_out, 31 }; 32 33 static const struct clk_pcr_layout sama5d3_pcr_layout = { 34 .offset = 0x10c, 35 .cmd = BIT(12), 36 .pid_mask = GENMASK(6, 0), 37 .div_mask = GENMASK(17, 16), 38 }; 39 40 static const struct { 41 char *n; 42 char *p; 43 u8 id; 44 } sama5d3_systemck[] = { 45 { .n = "ddrck", .p = "masterck_div", .id = 2 }, 46 { .n = "lcdck", .p = "masterck_div", .id = 3 }, 47 { .n = "smdck", .p = "smdclk", .id = 4 }, 48 { .n = "uhpck", .p = "usbck", .id = 6 }, 49 { .n = "udpck", .p = "usbck", .id = 7 }, 50 { .n = "pck0", .p = "prog0", .id = 8 }, 51 { .n = "pck1", .p = "prog1", .id = 9 }, 52 { .n = "pck2", .p = "prog2", .id = 10 }, 53 }; 54 55 static const struct { 56 char *n; 57 u8 id; 58 struct clk_range r; 59 } sama5d3_periphck[] = { 60 { .n = "dbgu_clk", .id = 2, }, 61 { .n = "hsmc_clk", .id = 5, }, 62 { .n = "pioA_clk", .id = 6, }, 63 { .n = "pioB_clk", .id = 7, }, 64 { .n = "pioC_clk", .id = 8, }, 65 { .n = "pioD_clk", .id = 9, }, 66 { .n = "pioE_clk", .id = 10, }, 67 { .n = "usart0_clk", .id = 12, .r = { .min = 0, .max = 83000000 }, }, 68 { .n = "usart1_clk", .id = 13, .r = { .min = 0, .max = 83000000 }, }, 69 { .n = "usart2_clk", .id = 14, .r = { .min = 0, .max = 83000000 }, }, 70 { .n = "usart3_clk", .id = 15, .r = { .min = 0, .max = 83000000 }, }, 71 { .n = "uart0_clk", .id = 16, .r = { .min = 0, .max = 83000000 }, }, 72 { .n = "uart1_clk", .id = 17, .r = { .min = 0, .max = 83000000 }, }, 73 { .n = "twi0_clk", .id = 18, .r = { .min = 0, .max = 41500000 }, }, 74 { .n = "twi1_clk", .id = 19, .r = { .min = 0, .max = 41500000 }, }, 75 { .n = "twi2_clk", .id = 20, .r = { .min = 0, .max = 41500000 }, }, 76 { .n = "mci0_clk", .id = 21, }, 77 { .n = "mci1_clk", .id = 22, }, 78 { .n = "mci2_clk", .id = 23, }, 79 { .n = "spi0_clk", .id = 24, .r = { .min = 0, .max = 166000000 }, }, 80 { .n = "spi1_clk", .id = 25, .r = { .min = 0, .max = 166000000 }, }, 81 { .n = "tcb0_clk", .id = 26, .r = { .min = 0, .max = 166000000 }, }, 82 { .n = "tcb1_clk", .id = 27, .r = { .min = 0, .max = 166000000 }, }, 83 { .n = "pwm_clk", .id = 28, }, 84 { .n = "adc_clk", .id = 29, .r = { .min = 0, .max = 83000000 }, }, 85 { .n = "dma0_clk", .id = 30, }, 86 { .n = "dma1_clk", .id = 31, }, 87 { .n = "uhphs_clk", .id = 32, }, 88 { .n = "udphs_clk", .id = 33, }, 89 { .n = "macb0_clk", .id = 34, }, 90 { .n = "macb1_clk", .id = 35, }, 91 { .n = "lcdc_clk", .id = 36, }, 92 { .n = "isi_clk", .id = 37, }, 93 { .n = "ssc0_clk", .id = 38, .r = { .min = 0, .max = 83000000 }, }, 94 { .n = "ssc1_clk", .id = 39, .r = { .min = 0, .max = 83000000 }, }, 95 { .n = "can0_clk", .id = 40, .r = { .min = 0, .max = 83000000 }, }, 96 { .n = "can1_clk", .id = 41, .r = { .min = 0, .max = 83000000 }, }, 97 { .n = "sha_clk", .id = 42, }, 98 { .n = "aes_clk", .id = 43, }, 99 { .n = "tdes_clk", .id = 44, }, 100 { .n = "trng_clk", .id = 45, }, 101 { .n = "fuse_clk", .id = 48, }, 102 { .n = "mpddr_clk", .id = 49, }, 103 }; 104 105 static void __init sama5d3_pmc_setup(struct device_node *np) 106 { 107 const char *slck_name, *mainxtal_name; 108 struct pmc_data *sama5d3_pmc; 109 const char *parent_names[5]; 110 struct regmap *regmap; 111 struct clk_hw *hw; 112 int i; 113 bool bypass; 114 115 i = of_property_match_string(np, "clock-names", "slow_clk"); 116 if (i < 0) 117 return; 118 119 slck_name = of_clk_get_parent_name(np, i); 120 121 i = of_property_match_string(np, "clock-names", "main_xtal"); 122 if (i < 0) 123 return; 124 mainxtal_name = of_clk_get_parent_name(np, i); 125 126 regmap = device_node_to_regmap(np); 127 if (IS_ERR(regmap)) 128 return; 129 130 sama5d3_pmc = pmc_data_allocate(PMC_PLLACK + 1, 131 nck(sama5d3_systemck), 132 nck(sama5d3_periphck), 0, 3); 133 if (!sama5d3_pmc) 134 return; 135 136 hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, 137 50000000); 138 if (IS_ERR(hw)) 139 goto err_free; 140 141 bypass = of_property_read_bool(np, "atmel,osc-bypass"); 142 143 hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, 144 bypass); 145 if (IS_ERR(hw)) 146 goto err_free; 147 148 parent_names[0] = "main_rc_osc"; 149 parent_names[1] = "main_osc"; 150 hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2); 151 if (IS_ERR(hw)) 152 goto err_free; 153 154 hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0, 155 &sama5d3_pll_layout, &plla_characteristics); 156 if (IS_ERR(hw)) 157 goto err_free; 158 159 hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack"); 160 if (IS_ERR(hw)) 161 goto err_free; 162 163 sama5d3_pmc->chws[PMC_PLLACK] = hw; 164 165 hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck"); 166 if (IS_ERR(hw)) 167 goto err_free; 168 169 sama5d3_pmc->chws[PMC_UTMI] = hw; 170 171 parent_names[0] = slck_name; 172 parent_names[1] = "mainck"; 173 parent_names[2] = "plladivck"; 174 parent_names[3] = "utmick"; 175 hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, 176 parent_names, 177 &at91sam9x5_master_layout, 178 &mck_characteristics, &mck_lock, 179 CLK_SET_RATE_GATE, INT_MIN); 180 if (IS_ERR(hw)) 181 goto err_free; 182 183 hw = at91_clk_register_master_div(regmap, "masterck_div", 184 "masterck_pres", 185 &at91sam9x5_master_layout, 186 &mck_characteristics, &mck_lock, 187 CLK_SET_RATE_GATE); 188 if (IS_ERR(hw)) 189 goto err_free; 190 191 sama5d3_pmc->chws[PMC_MCK] = hw; 192 193 parent_names[0] = "plladivck"; 194 parent_names[1] = "utmick"; 195 hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2); 196 if (IS_ERR(hw)) 197 goto err_free; 198 199 hw = at91sam9x5_clk_register_smd(regmap, "smdclk", parent_names, 2); 200 if (IS_ERR(hw)) 201 goto err_free; 202 203 parent_names[0] = slck_name; 204 parent_names[1] = "mainck"; 205 parent_names[2] = "plladivck"; 206 parent_names[3] = "utmick"; 207 parent_names[4] = "masterck_div"; 208 for (i = 0; i < 3; i++) { 209 char name[6]; 210 211 snprintf(name, sizeof(name), "prog%d", i); 212 213 hw = at91_clk_register_programmable(regmap, name, 214 parent_names, 5, i, 215 &at91sam9x5_programmable_layout, 216 NULL); 217 if (IS_ERR(hw)) 218 goto err_free; 219 220 sama5d3_pmc->pchws[i] = hw; 221 } 222 223 for (i = 0; i < ARRAY_SIZE(sama5d3_systemck); i++) { 224 hw = at91_clk_register_system(regmap, sama5d3_systemck[i].n, 225 sama5d3_systemck[i].p, 226 sama5d3_systemck[i].id); 227 if (IS_ERR(hw)) 228 goto err_free; 229 230 sama5d3_pmc->shws[sama5d3_systemck[i].id] = hw; 231 } 232 233 for (i = 0; i < ARRAY_SIZE(sama5d3_periphck); i++) { 234 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, 235 &sama5d3_pcr_layout, 236 sama5d3_periphck[i].n, 237 "masterck_div", 238 sama5d3_periphck[i].id, 239 &sama5d3_periphck[i].r, 240 INT_MIN); 241 if (IS_ERR(hw)) 242 goto err_free; 243 244 sama5d3_pmc->phws[sama5d3_periphck[i].id] = hw; 245 } 246 247 of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sama5d3_pmc); 248 249 return; 250 251 err_free: 252 kfree(sama5d3_pmc); 253 } 254 /* 255 * The TCB is used as the clocksource so its clock is needed early. This means 256 * this can't be a platform driver. 257 */ 258 CLK_OF_DECLARE_DRIVER(sama5d3_pmc, "atmel,sama5d3-pmc", sama5d3_pmc_setup); 259