1 // SPDX-License-Identifier: GPL-2.0 2 #include <linux/clk-provider.h> 3 #include <linux/clk/at91_pmc.h> 4 #include <linux/of.h> 5 #include <linux/mfd/syscon.h> 6 #include <linux/regmap.h> 7 #include <linux/slab.h> 8 9 #include "pmc.h" 10 11 #define MASTER_SOURCE_MAX 4 12 13 #define PERIPHERAL_AT91RM9200 0 14 #define PERIPHERAL_AT91SAM9X5 1 15 16 #define PERIPHERAL_MAX 64 17 18 #define PERIPHERAL_ID_MIN 2 19 20 #define PROG_SOURCE_MAX 5 21 #define PROG_ID_MAX 7 22 23 #define SYSTEM_MAX_ID 31 24 25 #define GCK_INDEX_DT_AUDIO_PLL 5 26 27 #ifdef CONFIG_HAVE_AT91_AUDIO_PLL 28 static void __init of_sama5d2_clk_audio_pll_frac_setup(struct device_node *np) 29 { 30 struct clk_hw *hw; 31 const char *name = np->name; 32 const char *parent_name; 33 struct regmap *regmap; 34 35 regmap = syscon_node_to_regmap(of_get_parent(np)); 36 if (IS_ERR(regmap)) 37 return; 38 39 parent_name = of_clk_get_parent_name(np, 0); 40 41 hw = at91_clk_register_audio_pll_frac(regmap, name, parent_name); 42 if (IS_ERR(hw)) 43 return; 44 45 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); 46 } 47 CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_frac_setup, 48 "atmel,sama5d2-clk-audio-pll-frac", 49 of_sama5d2_clk_audio_pll_frac_setup); 50 51 static void __init of_sama5d2_clk_audio_pll_pad_setup(struct device_node *np) 52 { 53 struct clk_hw *hw; 54 const char *name = np->name; 55 const char *parent_name; 56 struct regmap *regmap; 57 58 regmap = syscon_node_to_regmap(of_get_parent(np)); 59 if (IS_ERR(regmap)) 60 return; 61 62 parent_name = of_clk_get_parent_name(np, 0); 63 64 hw = at91_clk_register_audio_pll_pad(regmap, name, parent_name); 65 if (IS_ERR(hw)) 66 return; 67 68 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); 69 } 70 CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_pad_setup, 71 "atmel,sama5d2-clk-audio-pll-pad", 72 of_sama5d2_clk_audio_pll_pad_setup); 73 74 static void __init of_sama5d2_clk_audio_pll_pmc_setup(struct device_node *np) 75 { 76 struct clk_hw *hw; 77 const char *name = np->name; 78 const char *parent_name; 79 struct regmap *regmap; 80 81 regmap = syscon_node_to_regmap(of_get_parent(np)); 82 if (IS_ERR(regmap)) 83 return; 84 85 parent_name = of_clk_get_parent_name(np, 0); 86 87 hw = at91_clk_register_audio_pll_pmc(regmap, name, parent_name); 88 if (IS_ERR(hw)) 89 return; 90 91 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); 92 } 93 CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_pmc_setup, 94 "atmel,sama5d2-clk-audio-pll-pmc", 95 of_sama5d2_clk_audio_pll_pmc_setup); 96 #endif /* CONFIG_HAVE_AT91_AUDIO_PLL */ 97 98 static const struct clk_pcr_layout dt_pcr_layout = { 99 .offset = 0x10c, 100 .cmd = BIT(12), 101 .pid_mask = GENMASK(5, 0), 102 .div_mask = GENMASK(17, 16), 103 .gckcss_mask = GENMASK(10, 8), 104 }; 105 106 #ifdef CONFIG_HAVE_AT91_GENERATED_CLK 107 #define GENERATED_SOURCE_MAX 6 108 109 #define GCK_ID_I2S0 54 110 #define GCK_ID_I2S1 55 111 #define GCK_ID_CLASSD 59 112 113 static void __init of_sama5d2_clk_generated_setup(struct device_node *np) 114 { 115 int num; 116 u32 id; 117 const char *name; 118 struct clk_hw *hw; 119 unsigned int num_parents; 120 const char *parent_names[GENERATED_SOURCE_MAX]; 121 struct device_node *gcknp; 122 struct clk_range range = CLK_RANGE(0, 0); 123 struct regmap *regmap; 124 125 num_parents = of_clk_get_parent_count(np); 126 if (num_parents == 0 || num_parents > GENERATED_SOURCE_MAX) 127 return; 128 129 of_clk_parent_fill(np, parent_names, num_parents); 130 131 num = of_get_child_count(np); 132 if (!num || num > PERIPHERAL_MAX) 133 return; 134 135 regmap = syscon_node_to_regmap(of_get_parent(np)); 136 if (IS_ERR(regmap)) 137 return; 138 139 for_each_child_of_node(np, gcknp) { 140 int chg_pid = INT_MIN; 141 142 if (of_property_read_u32(gcknp, "reg", &id)) 143 continue; 144 145 if (id < PERIPHERAL_ID_MIN || id >= PERIPHERAL_MAX) 146 continue; 147 148 if (of_property_read_string(np, "clock-output-names", &name)) 149 name = gcknp->name; 150 151 of_at91_get_clk_range(gcknp, "atmel,clk-output-range", 152 &range); 153 154 if (of_device_is_compatible(np, "atmel,sama5d2-clk-generated") && 155 (id == GCK_ID_I2S0 || id == GCK_ID_I2S1 || 156 id == GCK_ID_CLASSD)) 157 chg_pid = GCK_INDEX_DT_AUDIO_PLL; 158 159 hw = at91_clk_register_generated(regmap, &pmc_pcr_lock, 160 &dt_pcr_layout, name, 161 parent_names, NULL, 162 num_parents, id, &range, 163 chg_pid); 164 if (IS_ERR(hw)) 165 continue; 166 167 of_clk_add_hw_provider(gcknp, of_clk_hw_simple_get, hw); 168 } 169 } 170 CLK_OF_DECLARE(of_sama5d2_clk_generated_setup, "atmel,sama5d2-clk-generated", 171 of_sama5d2_clk_generated_setup); 172 #endif /* CONFIG_HAVE_AT91_GENERATED_CLK */ 173 174 #ifdef CONFIG_HAVE_AT91_H32MX 175 static void __init of_sama5d4_clk_h32mx_setup(struct device_node *np) 176 { 177 struct clk_hw *hw; 178 const char *name = np->name; 179 const char *parent_name; 180 struct regmap *regmap; 181 182 regmap = syscon_node_to_regmap(of_get_parent(np)); 183 if (IS_ERR(regmap)) 184 return; 185 186 parent_name = of_clk_get_parent_name(np, 0); 187 188 hw = at91_clk_register_h32mx(regmap, name, parent_name); 189 if (IS_ERR(hw)) 190 return; 191 192 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); 193 } 194 CLK_OF_DECLARE(of_sama5d4_clk_h32mx_setup, "atmel,sama5d4-clk-h32mx", 195 of_sama5d4_clk_h32mx_setup); 196 #endif /* CONFIG_HAVE_AT91_H32MX */ 197 198 #ifdef CONFIG_HAVE_AT91_I2S_MUX_CLK 199 #define I2S_BUS_NR 2 200 201 static void __init of_sama5d2_clk_i2s_mux_setup(struct device_node *np) 202 { 203 struct regmap *regmap_sfr; 204 u8 bus_id; 205 const char *parent_names[2]; 206 struct device_node *i2s_mux_np; 207 struct clk_hw *hw; 208 int ret; 209 210 regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr"); 211 if (IS_ERR(regmap_sfr)) 212 return; 213 214 for_each_child_of_node(np, i2s_mux_np) { 215 if (of_property_read_u8(i2s_mux_np, "reg", &bus_id)) 216 continue; 217 218 if (bus_id > I2S_BUS_NR) 219 continue; 220 221 ret = of_clk_parent_fill(i2s_mux_np, parent_names, 2); 222 if (ret != 2) 223 continue; 224 225 hw = at91_clk_i2s_mux_register(regmap_sfr, i2s_mux_np->name, 226 parent_names, 2, bus_id); 227 if (IS_ERR(hw)) 228 continue; 229 230 of_clk_add_hw_provider(i2s_mux_np, of_clk_hw_simple_get, hw); 231 } 232 } 233 CLK_OF_DECLARE(sama5d2_clk_i2s_mux, "atmel,sama5d2-clk-i2s-mux", 234 of_sama5d2_clk_i2s_mux_setup); 235 #endif /* CONFIG_HAVE_AT91_I2S_MUX_CLK */ 236 237 static void __init of_at91rm9200_clk_main_osc_setup(struct device_node *np) 238 { 239 struct clk_hw *hw; 240 const char *name = np->name; 241 const char *parent_name; 242 struct regmap *regmap; 243 bool bypass; 244 245 of_property_read_string(np, "clock-output-names", &name); 246 bypass = of_property_read_bool(np, "atmel,osc-bypass"); 247 parent_name = of_clk_get_parent_name(np, 0); 248 249 regmap = syscon_node_to_regmap(of_get_parent(np)); 250 if (IS_ERR(regmap)) 251 return; 252 253 hw = at91_clk_register_main_osc(regmap, name, parent_name, bypass); 254 if (IS_ERR(hw)) 255 return; 256 257 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); 258 } 259 CLK_OF_DECLARE(at91rm9200_clk_main_osc, "atmel,at91rm9200-clk-main-osc", 260 of_at91rm9200_clk_main_osc_setup); 261 262 static void __init of_at91sam9x5_clk_main_rc_osc_setup(struct device_node *np) 263 { 264 struct clk_hw *hw; 265 u32 frequency = 0; 266 u32 accuracy = 0; 267 const char *name = np->name; 268 struct regmap *regmap; 269 270 of_property_read_string(np, "clock-output-names", &name); 271 of_property_read_u32(np, "clock-frequency", &frequency); 272 of_property_read_u32(np, "clock-accuracy", &accuracy); 273 274 regmap = syscon_node_to_regmap(of_get_parent(np)); 275 if (IS_ERR(regmap)) 276 return; 277 278 hw = at91_clk_register_main_rc_osc(regmap, name, frequency, accuracy); 279 if (IS_ERR(hw)) 280 return; 281 282 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); 283 } 284 CLK_OF_DECLARE(at91sam9x5_clk_main_rc_osc, "atmel,at91sam9x5-clk-main-rc-osc", 285 of_at91sam9x5_clk_main_rc_osc_setup); 286 287 static void __init of_at91rm9200_clk_main_setup(struct device_node *np) 288 { 289 struct clk_hw *hw; 290 const char *parent_name; 291 const char *name = np->name; 292 struct regmap *regmap; 293 294 parent_name = of_clk_get_parent_name(np, 0); 295 of_property_read_string(np, "clock-output-names", &name); 296 297 regmap = syscon_node_to_regmap(of_get_parent(np)); 298 if (IS_ERR(regmap)) 299 return; 300 301 hw = at91_clk_register_rm9200_main(regmap, name, parent_name); 302 if (IS_ERR(hw)) 303 return; 304 305 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); 306 } 307 CLK_OF_DECLARE(at91rm9200_clk_main, "atmel,at91rm9200-clk-main", 308 of_at91rm9200_clk_main_setup); 309 310 static void __init of_at91sam9x5_clk_main_setup(struct device_node *np) 311 { 312 struct clk_hw *hw; 313 const char *parent_names[2]; 314 unsigned int num_parents; 315 const char *name = np->name; 316 struct regmap *regmap; 317 318 num_parents = of_clk_get_parent_count(np); 319 if (num_parents == 0 || num_parents > 2) 320 return; 321 322 of_clk_parent_fill(np, parent_names, num_parents); 323 regmap = syscon_node_to_regmap(of_get_parent(np)); 324 if (IS_ERR(regmap)) 325 return; 326 327 of_property_read_string(np, "clock-output-names", &name); 328 329 hw = at91_clk_register_sam9x5_main(regmap, name, parent_names, 330 num_parents); 331 if (IS_ERR(hw)) 332 return; 333 334 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); 335 } 336 CLK_OF_DECLARE(at91sam9x5_clk_main, "atmel,at91sam9x5-clk-main", 337 of_at91sam9x5_clk_main_setup); 338 339 static struct clk_master_characteristics * __init 340 of_at91_clk_master_get_characteristics(struct device_node *np) 341 { 342 struct clk_master_characteristics *characteristics; 343 344 characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL); 345 if (!characteristics) 346 return NULL; 347 348 if (of_at91_get_clk_range(np, "atmel,clk-output-range", &characteristics->output)) 349 goto out_free_characteristics; 350 351 of_property_read_u32_array(np, "atmel,clk-divisors", 352 characteristics->divisors, 4); 353 354 characteristics->have_div3_pres = 355 of_property_read_bool(np, "atmel,master-clk-have-div3-pres"); 356 357 return characteristics; 358 359 out_free_characteristics: 360 kfree(characteristics); 361 return NULL; 362 } 363 364 static void __init 365 of_at91_clk_master_setup(struct device_node *np, 366 const struct clk_master_layout *layout) 367 { 368 struct clk_hw *hw; 369 unsigned int num_parents; 370 const char *parent_names[MASTER_SOURCE_MAX]; 371 const char *name = np->name; 372 struct clk_master_characteristics *characteristics; 373 struct regmap *regmap; 374 375 num_parents = of_clk_get_parent_count(np); 376 if (num_parents == 0 || num_parents > MASTER_SOURCE_MAX) 377 return; 378 379 of_clk_parent_fill(np, parent_names, num_parents); 380 381 of_property_read_string(np, "clock-output-names", &name); 382 383 characteristics = of_at91_clk_master_get_characteristics(np); 384 if (!characteristics) 385 return; 386 387 regmap = syscon_node_to_regmap(of_get_parent(np)); 388 if (IS_ERR(regmap)) 389 return; 390 391 hw = at91_clk_register_master(regmap, name, num_parents, 392 parent_names, layout, 393 characteristics); 394 if (IS_ERR(hw)) 395 goto out_free_characteristics; 396 397 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); 398 return; 399 400 out_free_characteristics: 401 kfree(characteristics); 402 } 403 404 static void __init of_at91rm9200_clk_master_setup(struct device_node *np) 405 { 406 of_at91_clk_master_setup(np, &at91rm9200_master_layout); 407 } 408 CLK_OF_DECLARE(at91rm9200_clk_master, "atmel,at91rm9200-clk-master", 409 of_at91rm9200_clk_master_setup); 410 411 static void __init of_at91sam9x5_clk_master_setup(struct device_node *np) 412 { 413 of_at91_clk_master_setup(np, &at91sam9x5_master_layout); 414 } 415 CLK_OF_DECLARE(at91sam9x5_clk_master, "atmel,at91sam9x5-clk-master", 416 of_at91sam9x5_clk_master_setup); 417 418 static void __init 419 of_at91_clk_periph_setup(struct device_node *np, u8 type) 420 { 421 int num; 422 u32 id; 423 struct clk_hw *hw; 424 const char *parent_name; 425 const char *name; 426 struct device_node *periphclknp; 427 struct regmap *regmap; 428 429 parent_name = of_clk_get_parent_name(np, 0); 430 if (!parent_name) 431 return; 432 433 num = of_get_child_count(np); 434 if (!num || num > PERIPHERAL_MAX) 435 return; 436 437 regmap = syscon_node_to_regmap(of_get_parent(np)); 438 if (IS_ERR(regmap)) 439 return; 440 441 for_each_child_of_node(np, periphclknp) { 442 if (of_property_read_u32(periphclknp, "reg", &id)) 443 continue; 444 445 if (id >= PERIPHERAL_MAX) 446 continue; 447 448 if (of_property_read_string(np, "clock-output-names", &name)) 449 name = periphclknp->name; 450 451 if (type == PERIPHERAL_AT91RM9200) { 452 hw = at91_clk_register_peripheral(regmap, name, 453 parent_name, id); 454 } else { 455 struct clk_range range = CLK_RANGE(0, 0); 456 457 of_at91_get_clk_range(periphclknp, 458 "atmel,clk-output-range", 459 &range); 460 461 hw = at91_clk_register_sam9x5_peripheral(regmap, 462 &pmc_pcr_lock, 463 &dt_pcr_layout, 464 name, 465 parent_name, 466 id, &range, 467 INT_MIN); 468 } 469 470 if (IS_ERR(hw)) 471 continue; 472 473 of_clk_add_hw_provider(periphclknp, of_clk_hw_simple_get, hw); 474 } 475 } 476 477 static void __init of_at91rm9200_clk_periph_setup(struct device_node *np) 478 { 479 of_at91_clk_periph_setup(np, PERIPHERAL_AT91RM9200); 480 } 481 CLK_OF_DECLARE(at91rm9200_clk_periph, "atmel,at91rm9200-clk-peripheral", 482 of_at91rm9200_clk_periph_setup); 483 484 static void __init of_at91sam9x5_clk_periph_setup(struct device_node *np) 485 { 486 of_at91_clk_periph_setup(np, PERIPHERAL_AT91SAM9X5); 487 } 488 CLK_OF_DECLARE(at91sam9x5_clk_periph, "atmel,at91sam9x5-clk-peripheral", 489 of_at91sam9x5_clk_periph_setup); 490 491 static struct clk_pll_characteristics * __init 492 of_at91_clk_pll_get_characteristics(struct device_node *np) 493 { 494 int i; 495 int offset; 496 u32 tmp; 497 int num_output; 498 u32 num_cells; 499 struct clk_range input; 500 struct clk_range *output; 501 u8 *out = NULL; 502 u16 *icpll = NULL; 503 struct clk_pll_characteristics *characteristics; 504 505 if (of_at91_get_clk_range(np, "atmel,clk-input-range", &input)) 506 return NULL; 507 508 if (of_property_read_u32(np, "#atmel,pll-clk-output-range-cells", 509 &num_cells)) 510 return NULL; 511 512 if (num_cells < 2 || num_cells > 4) 513 return NULL; 514 515 if (!of_get_property(np, "atmel,pll-clk-output-ranges", &tmp)) 516 return NULL; 517 num_output = tmp / (sizeof(u32) * num_cells); 518 519 characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL); 520 if (!characteristics) 521 return NULL; 522 523 output = kcalloc(num_output, sizeof(*output), GFP_KERNEL); 524 if (!output) 525 goto out_free_characteristics; 526 527 if (num_cells > 2) { 528 out = kcalloc(num_output, sizeof(*out), GFP_KERNEL); 529 if (!out) 530 goto out_free_output; 531 } 532 533 if (num_cells > 3) { 534 icpll = kcalloc(num_output, sizeof(*icpll), GFP_KERNEL); 535 if (!icpll) 536 goto out_free_output; 537 } 538 539 for (i = 0; i < num_output; i++) { 540 offset = i * num_cells; 541 if (of_property_read_u32_index(np, 542 "atmel,pll-clk-output-ranges", 543 offset, &tmp)) 544 goto out_free_output; 545 output[i].min = tmp; 546 if (of_property_read_u32_index(np, 547 "atmel,pll-clk-output-ranges", 548 offset + 1, &tmp)) 549 goto out_free_output; 550 output[i].max = tmp; 551 552 if (num_cells == 2) 553 continue; 554 555 if (of_property_read_u32_index(np, 556 "atmel,pll-clk-output-ranges", 557 offset + 2, &tmp)) 558 goto out_free_output; 559 out[i] = tmp; 560 561 if (num_cells == 3) 562 continue; 563 564 if (of_property_read_u32_index(np, 565 "atmel,pll-clk-output-ranges", 566 offset + 3, &tmp)) 567 goto out_free_output; 568 icpll[i] = tmp; 569 } 570 571 characteristics->input = input; 572 characteristics->num_output = num_output; 573 characteristics->output = output; 574 characteristics->out = out; 575 characteristics->icpll = icpll; 576 return characteristics; 577 578 out_free_output: 579 kfree(icpll); 580 kfree(out); 581 kfree(output); 582 out_free_characteristics: 583 kfree(characteristics); 584 return NULL; 585 } 586 587 static void __init 588 of_at91_clk_pll_setup(struct device_node *np, 589 const struct clk_pll_layout *layout) 590 { 591 u32 id; 592 struct clk_hw *hw; 593 struct regmap *regmap; 594 const char *parent_name; 595 const char *name = np->name; 596 struct clk_pll_characteristics *characteristics; 597 598 if (of_property_read_u32(np, "reg", &id)) 599 return; 600 601 parent_name = of_clk_get_parent_name(np, 0); 602 603 of_property_read_string(np, "clock-output-names", &name); 604 605 regmap = syscon_node_to_regmap(of_get_parent(np)); 606 if (IS_ERR(regmap)) 607 return; 608 609 characteristics = of_at91_clk_pll_get_characteristics(np); 610 if (!characteristics) 611 return; 612 613 hw = at91_clk_register_pll(regmap, name, parent_name, id, layout, 614 characteristics); 615 if (IS_ERR(hw)) 616 goto out_free_characteristics; 617 618 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); 619 return; 620 621 out_free_characteristics: 622 kfree(characteristics); 623 } 624 625 static void __init of_at91rm9200_clk_pll_setup(struct device_node *np) 626 { 627 of_at91_clk_pll_setup(np, &at91rm9200_pll_layout); 628 } 629 CLK_OF_DECLARE(at91rm9200_clk_pll, "atmel,at91rm9200-clk-pll", 630 of_at91rm9200_clk_pll_setup); 631 632 static void __init of_at91sam9g45_clk_pll_setup(struct device_node *np) 633 { 634 of_at91_clk_pll_setup(np, &at91sam9g45_pll_layout); 635 } 636 CLK_OF_DECLARE(at91sam9g45_clk_pll, "atmel,at91sam9g45-clk-pll", 637 of_at91sam9g45_clk_pll_setup); 638 639 static void __init of_at91sam9g20_clk_pllb_setup(struct device_node *np) 640 { 641 of_at91_clk_pll_setup(np, &at91sam9g20_pllb_layout); 642 } 643 CLK_OF_DECLARE(at91sam9g20_clk_pllb, "atmel,at91sam9g20-clk-pllb", 644 of_at91sam9g20_clk_pllb_setup); 645 646 static void __init of_sama5d3_clk_pll_setup(struct device_node *np) 647 { 648 of_at91_clk_pll_setup(np, &sama5d3_pll_layout); 649 } 650 CLK_OF_DECLARE(sama5d3_clk_pll, "atmel,sama5d3-clk-pll", 651 of_sama5d3_clk_pll_setup); 652 653 static void __init 654 of_at91sam9x5_clk_plldiv_setup(struct device_node *np) 655 { 656 struct clk_hw *hw; 657 const char *parent_name; 658 const char *name = np->name; 659 struct regmap *regmap; 660 661 parent_name = of_clk_get_parent_name(np, 0); 662 663 of_property_read_string(np, "clock-output-names", &name); 664 665 regmap = syscon_node_to_regmap(of_get_parent(np)); 666 if (IS_ERR(regmap)) 667 return; 668 669 hw = at91_clk_register_plldiv(regmap, name, parent_name); 670 if (IS_ERR(hw)) 671 return; 672 673 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); 674 } 675 CLK_OF_DECLARE(at91sam9x5_clk_plldiv, "atmel,at91sam9x5-clk-plldiv", 676 of_at91sam9x5_clk_plldiv_setup); 677 678 static void __init 679 of_at91_clk_prog_setup(struct device_node *np, 680 const struct clk_programmable_layout *layout, 681 u32 *mux_table) 682 { 683 int num; 684 u32 id; 685 struct clk_hw *hw; 686 unsigned int num_parents; 687 const char *parent_names[PROG_SOURCE_MAX]; 688 const char *name; 689 struct device_node *progclknp; 690 struct regmap *regmap; 691 692 num_parents = of_clk_get_parent_count(np); 693 if (num_parents == 0 || num_parents > PROG_SOURCE_MAX) 694 return; 695 696 of_clk_parent_fill(np, parent_names, num_parents); 697 698 num = of_get_child_count(np); 699 if (!num || num > (PROG_ID_MAX + 1)) 700 return; 701 702 regmap = syscon_node_to_regmap(of_get_parent(np)); 703 if (IS_ERR(regmap)) 704 return; 705 706 for_each_child_of_node(np, progclknp) { 707 if (of_property_read_u32(progclknp, "reg", &id)) 708 continue; 709 710 if (of_property_read_string(np, "clock-output-names", &name)) 711 name = progclknp->name; 712 713 hw = at91_clk_register_programmable(regmap, name, 714 parent_names, num_parents, 715 id, layout, mux_table); 716 if (IS_ERR(hw)) 717 continue; 718 719 of_clk_add_hw_provider(progclknp, of_clk_hw_simple_get, hw); 720 } 721 } 722 723 static void __init of_at91rm9200_clk_prog_setup(struct device_node *np) 724 { 725 of_at91_clk_prog_setup(np, &at91rm9200_programmable_layout, NULL); 726 } 727 CLK_OF_DECLARE(at91rm9200_clk_prog, "atmel,at91rm9200-clk-programmable", 728 of_at91rm9200_clk_prog_setup); 729 730 static void __init of_at91sam9g45_clk_prog_setup(struct device_node *np) 731 { 732 of_at91_clk_prog_setup(np, &at91sam9g45_programmable_layout, NULL); 733 } 734 CLK_OF_DECLARE(at91sam9g45_clk_prog, "atmel,at91sam9g45-clk-programmable", 735 of_at91sam9g45_clk_prog_setup); 736 737 static void __init of_at91sam9x5_clk_prog_setup(struct device_node *np) 738 { 739 of_at91_clk_prog_setup(np, &at91sam9x5_programmable_layout, NULL); 740 } 741 CLK_OF_DECLARE(at91sam9x5_clk_prog, "atmel,at91sam9x5-clk-programmable", 742 of_at91sam9x5_clk_prog_setup); 743 744 static void __init of_at91sam9260_clk_slow_setup(struct device_node *np) 745 { 746 struct clk_hw *hw; 747 const char *parent_names[2]; 748 unsigned int num_parents; 749 const char *name = np->name; 750 struct regmap *regmap; 751 752 num_parents = of_clk_get_parent_count(np); 753 if (num_parents != 2) 754 return; 755 756 of_clk_parent_fill(np, parent_names, num_parents); 757 regmap = syscon_node_to_regmap(of_get_parent(np)); 758 if (IS_ERR(regmap)) 759 return; 760 761 of_property_read_string(np, "clock-output-names", &name); 762 763 hw = at91_clk_register_sam9260_slow(regmap, name, parent_names, 764 num_parents); 765 if (IS_ERR(hw)) 766 return; 767 768 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); 769 } 770 CLK_OF_DECLARE(at91sam9260_clk_slow, "atmel,at91sam9260-clk-slow", 771 of_at91sam9260_clk_slow_setup); 772 773 #ifdef CONFIG_HAVE_AT91_SMD 774 #define SMD_SOURCE_MAX 2 775 776 static void __init of_at91sam9x5_clk_smd_setup(struct device_node *np) 777 { 778 struct clk_hw *hw; 779 unsigned int num_parents; 780 const char *parent_names[SMD_SOURCE_MAX]; 781 const char *name = np->name; 782 struct regmap *regmap; 783 784 num_parents = of_clk_get_parent_count(np); 785 if (num_parents == 0 || num_parents > SMD_SOURCE_MAX) 786 return; 787 788 of_clk_parent_fill(np, parent_names, num_parents); 789 790 of_property_read_string(np, "clock-output-names", &name); 791 792 regmap = syscon_node_to_regmap(of_get_parent(np)); 793 if (IS_ERR(regmap)) 794 return; 795 796 hw = at91sam9x5_clk_register_smd(regmap, name, parent_names, 797 num_parents); 798 if (IS_ERR(hw)) 799 return; 800 801 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); 802 } 803 CLK_OF_DECLARE(at91sam9x5_clk_smd, "atmel,at91sam9x5-clk-smd", 804 of_at91sam9x5_clk_smd_setup); 805 #endif /* CONFIG_HAVE_AT91_SMD */ 806 807 static void __init of_at91rm9200_clk_sys_setup(struct device_node *np) 808 { 809 int num; 810 u32 id; 811 struct clk_hw *hw; 812 const char *name; 813 struct device_node *sysclknp; 814 const char *parent_name; 815 struct regmap *regmap; 816 817 num = of_get_child_count(np); 818 if (num > (SYSTEM_MAX_ID + 1)) 819 return; 820 821 regmap = syscon_node_to_regmap(of_get_parent(np)); 822 if (IS_ERR(regmap)) 823 return; 824 825 for_each_child_of_node(np, sysclknp) { 826 if (of_property_read_u32(sysclknp, "reg", &id)) 827 continue; 828 829 if (of_property_read_string(np, "clock-output-names", &name)) 830 name = sysclknp->name; 831 832 parent_name = of_clk_get_parent_name(sysclknp, 0); 833 834 hw = at91_clk_register_system(regmap, name, parent_name, id); 835 if (IS_ERR(hw)) 836 continue; 837 838 of_clk_add_hw_provider(sysclknp, of_clk_hw_simple_get, hw); 839 } 840 } 841 CLK_OF_DECLARE(at91rm9200_clk_sys, "atmel,at91rm9200-clk-system", 842 of_at91rm9200_clk_sys_setup); 843 844 #ifdef CONFIG_HAVE_AT91_USB_CLK 845 #define USB_SOURCE_MAX 2 846 847 static void __init of_at91sam9x5_clk_usb_setup(struct device_node *np) 848 { 849 struct clk_hw *hw; 850 unsigned int num_parents; 851 const char *parent_names[USB_SOURCE_MAX]; 852 const char *name = np->name; 853 struct regmap *regmap; 854 855 num_parents = of_clk_get_parent_count(np); 856 if (num_parents == 0 || num_parents > USB_SOURCE_MAX) 857 return; 858 859 of_clk_parent_fill(np, parent_names, num_parents); 860 861 of_property_read_string(np, "clock-output-names", &name); 862 863 regmap = syscon_node_to_regmap(of_get_parent(np)); 864 if (IS_ERR(regmap)) 865 return; 866 867 hw = at91sam9x5_clk_register_usb(regmap, name, parent_names, 868 num_parents); 869 if (IS_ERR(hw)) 870 return; 871 872 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); 873 } 874 CLK_OF_DECLARE(at91sam9x5_clk_usb, "atmel,at91sam9x5-clk-usb", 875 of_at91sam9x5_clk_usb_setup); 876 877 static void __init of_at91sam9n12_clk_usb_setup(struct device_node *np) 878 { 879 struct clk_hw *hw; 880 const char *parent_name; 881 const char *name = np->name; 882 struct regmap *regmap; 883 884 parent_name = of_clk_get_parent_name(np, 0); 885 if (!parent_name) 886 return; 887 888 of_property_read_string(np, "clock-output-names", &name); 889 890 regmap = syscon_node_to_regmap(of_get_parent(np)); 891 if (IS_ERR(regmap)) 892 return; 893 894 hw = at91sam9n12_clk_register_usb(regmap, name, parent_name); 895 if (IS_ERR(hw)) 896 return; 897 898 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); 899 } 900 CLK_OF_DECLARE(at91sam9n12_clk_usb, "atmel,at91sam9n12-clk-usb", 901 of_at91sam9n12_clk_usb_setup); 902 903 static void __init of_at91rm9200_clk_usb_setup(struct device_node *np) 904 { 905 struct clk_hw *hw; 906 const char *parent_name; 907 const char *name = np->name; 908 u32 divisors[4] = {0, 0, 0, 0}; 909 struct regmap *regmap; 910 911 parent_name = of_clk_get_parent_name(np, 0); 912 if (!parent_name) 913 return; 914 915 of_property_read_u32_array(np, "atmel,clk-divisors", divisors, 4); 916 if (!divisors[0]) 917 return; 918 919 of_property_read_string(np, "clock-output-names", &name); 920 921 regmap = syscon_node_to_regmap(of_get_parent(np)); 922 if (IS_ERR(regmap)) 923 return; 924 hw = at91rm9200_clk_register_usb(regmap, name, parent_name, divisors); 925 if (IS_ERR(hw)) 926 return; 927 928 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); 929 } 930 CLK_OF_DECLARE(at91rm9200_clk_usb, "atmel,at91rm9200-clk-usb", 931 of_at91rm9200_clk_usb_setup); 932 #endif /* CONFIG_HAVE_AT91_USB_CLK */ 933 934 #ifdef CONFIG_HAVE_AT91_UTMI 935 static void __init of_at91sam9x5_clk_utmi_setup(struct device_node *np) 936 { 937 struct clk_hw *hw; 938 const char *parent_name; 939 const char *name = np->name; 940 struct regmap *regmap_pmc, *regmap_sfr; 941 942 parent_name = of_clk_get_parent_name(np, 0); 943 944 of_property_read_string(np, "clock-output-names", &name); 945 946 regmap_pmc = syscon_node_to_regmap(of_get_parent(np)); 947 if (IS_ERR(regmap_pmc)) 948 return; 949 950 /* 951 * If the device supports different mainck rates, this value has to be 952 * set in the UTMI Clock Trimming register. 953 * - 9x5: mainck supports several rates but it is indicated that a 954 * 12 MHz is needed in case of USB. 955 * - sama5d3 and sama5d2: mainck supports several rates. Configuring 956 * the FREQ field of the UTMI Clock Trimming register is mandatory. 957 * - sama5d4: mainck is at 12 MHz. 958 * 959 * We only need to retrieve sama5d3 or sama5d2 sfr regmap. 960 */ 961 regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d3-sfr"); 962 if (IS_ERR(regmap_sfr)) { 963 regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr"); 964 if (IS_ERR(regmap_sfr)) 965 regmap_sfr = NULL; 966 } 967 968 hw = at91_clk_register_utmi(regmap_pmc, regmap_sfr, name, parent_name); 969 if (IS_ERR(hw)) 970 return; 971 972 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); 973 } 974 CLK_OF_DECLARE(at91sam9x5_clk_utmi, "atmel,at91sam9x5-clk-utmi", 975 of_at91sam9x5_clk_utmi_setup); 976 #endif /* CONFIG_HAVE_AT91_UTMI */ 977