1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  *  Copyright (C) 2019 Microchip Technology Inc.
4  *
5  */
6 
7 #include <linux/bitfield.h>
8 #include <linux/clk-provider.h>
9 #include <linux/clkdev.h>
10 #include <linux/clk/at91_pmc.h>
11 #include <linux/of.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/regmap.h>
14 
15 #include "pmc.h"
16 
17 #define PMC_PLL_CTRL0	0xc
18 #define		PMC_PLL_CTRL0_DIV_MSK		GENMASK(7, 0)
19 #define		PMC_PLL_CTRL0_ENPLL		BIT(28)
20 #define		PMC_PLL_CTRL0_ENPLLCK		BIT(29)
21 #define		PMC_PLL_CTRL0_ENLOCK		BIT(31)
22 
23 #define PMC_PLL_CTRL1	0x10
24 #define		PMC_PLL_CTRL1_FRACR_MSK		GENMASK(21, 0)
25 #define		PMC_PLL_CTRL1_MUL_MSK		GENMASK(30, 24)
26 
27 #define PMC_PLL_ACR	0x18
28 #define		PMC_PLL_ACR_DEFAULT_UPLL	0x12020010UL
29 #define		PMC_PLL_ACR_DEFAULT_PLLA	0x00020010UL
30 #define		PMC_PLL_ACR_UTMIVR		BIT(12)
31 #define		PMC_PLL_ACR_UTMIBG		BIT(13)
32 #define		PMC_PLL_ACR_LOOP_FILTER_MSK	GENMASK(31, 24)
33 
34 #define PMC_PLL_UPDT	0x1c
35 #define		PMC_PLL_UPDT_UPDATE		BIT(8)
36 
37 #define PMC_PLL_ISR0	0xec
38 
39 #define PLL_DIV_MAX		(FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, UINT_MAX) + 1)
40 #define UPLL_DIV		2
41 #define PLL_MUL_MAX		(FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, UINT_MAX) + 1)
42 
43 #define PLL_MAX_ID		1
44 
45 struct sam9x60_pll {
46 	struct clk_hw hw;
47 	struct regmap *regmap;
48 	spinlock_t *lock;
49 	const struct clk_pll_characteristics *characteristics;
50 	u32 frac;
51 	u8 id;
52 	u8 div;
53 	u16 mul;
54 };
55 
56 #define to_sam9x60_pll(hw) container_of(hw, struct sam9x60_pll, hw)
57 
58 static inline bool sam9x60_pll_ready(struct regmap *regmap, int id)
59 {
60 	unsigned int status;
61 
62 	regmap_read(regmap, PMC_PLL_ISR0, &status);
63 
64 	return !!(status & BIT(id));
65 }
66 
67 static int sam9x60_pll_prepare(struct clk_hw *hw)
68 {
69 	struct sam9x60_pll *pll = to_sam9x60_pll(hw);
70 	struct regmap *regmap = pll->regmap;
71 	unsigned long flags;
72 	u8 div;
73 	u16 mul;
74 	u32 val;
75 
76 	spin_lock_irqsave(pll->lock, flags);
77 	regmap_write(regmap, PMC_PLL_UPDT, pll->id);
78 
79 	regmap_read(regmap, PMC_PLL_CTRL0, &val);
80 	div = FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, val);
81 
82 	regmap_read(regmap, PMC_PLL_CTRL1, &val);
83 	mul = FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, val);
84 
85 	if (sam9x60_pll_ready(regmap, pll->id) &&
86 	    (div == pll->div && mul == pll->mul)) {
87 		spin_unlock_irqrestore(pll->lock, flags);
88 		return 0;
89 	}
90 
91 	/* Recommended value for PMC_PLL_ACR */
92 	if (pll->characteristics->upll)
93 		val = PMC_PLL_ACR_DEFAULT_UPLL;
94 	else
95 		val = PMC_PLL_ACR_DEFAULT_PLLA;
96 	regmap_write(regmap, PMC_PLL_ACR, val);
97 
98 	regmap_write(regmap, PMC_PLL_CTRL1,
99 		     FIELD_PREP(PMC_PLL_CTRL1_MUL_MSK, pll->mul));
100 
101 	if (pll->characteristics->upll) {
102 		/* Enable the UTMI internal bandgap */
103 		val |= PMC_PLL_ACR_UTMIBG;
104 		regmap_write(regmap, PMC_PLL_ACR, val);
105 
106 		udelay(10);
107 
108 		/* Enable the UTMI internal regulator */
109 		val |= PMC_PLL_ACR_UTMIVR;
110 		regmap_write(regmap, PMC_PLL_ACR, val);
111 
112 		udelay(10);
113 	}
114 
115 	regmap_update_bits(regmap, PMC_PLL_UPDT,
116 			   PMC_PLL_UPDT_UPDATE, PMC_PLL_UPDT_UPDATE);
117 
118 	regmap_write(regmap, PMC_PLL_CTRL0,
119 		     PMC_PLL_CTRL0_ENLOCK | PMC_PLL_CTRL0_ENPLL |
120 		     PMC_PLL_CTRL0_ENPLLCK | pll->div);
121 
122 	regmap_update_bits(regmap, PMC_PLL_UPDT,
123 			   PMC_PLL_UPDT_UPDATE, PMC_PLL_UPDT_UPDATE);
124 
125 	while (!sam9x60_pll_ready(regmap, pll->id))
126 		cpu_relax();
127 
128 	spin_unlock_irqrestore(pll->lock, flags);
129 
130 	return 0;
131 }
132 
133 static int sam9x60_pll_is_prepared(struct clk_hw *hw)
134 {
135 	struct sam9x60_pll *pll = to_sam9x60_pll(hw);
136 
137 	return sam9x60_pll_ready(pll->regmap, pll->id);
138 }
139 
140 static void sam9x60_pll_unprepare(struct clk_hw *hw)
141 {
142 	struct sam9x60_pll *pll = to_sam9x60_pll(hw);
143 	unsigned long flags;
144 
145 	spin_lock_irqsave(pll->lock, flags);
146 
147 	regmap_write(pll->regmap, PMC_PLL_UPDT, pll->id);
148 
149 	regmap_update_bits(pll->regmap, PMC_PLL_CTRL0,
150 			   PMC_PLL_CTRL0_ENPLLCK, 0);
151 
152 	regmap_update_bits(pll->regmap, PMC_PLL_UPDT,
153 			   PMC_PLL_UPDT_UPDATE, PMC_PLL_UPDT_UPDATE);
154 
155 	regmap_update_bits(pll->regmap, PMC_PLL_CTRL0, PMC_PLL_CTRL0_ENPLL, 0);
156 
157 	if (pll->characteristics->upll)
158 		regmap_update_bits(pll->regmap, PMC_PLL_ACR,
159 				   PMC_PLL_ACR_UTMIBG | PMC_PLL_ACR_UTMIVR, 0);
160 
161 	regmap_update_bits(pll->regmap, PMC_PLL_UPDT,
162 			   PMC_PLL_UPDT_UPDATE, PMC_PLL_UPDT_UPDATE);
163 
164 	spin_unlock_irqrestore(pll->lock, flags);
165 }
166 
167 static unsigned long sam9x60_pll_recalc_rate(struct clk_hw *hw,
168 					     unsigned long parent_rate)
169 {
170 	struct sam9x60_pll *pll = to_sam9x60_pll(hw);
171 
172 	return (parent_rate * (pll->mul + 1)) / (pll->div + 1);
173 }
174 
175 static long sam9x60_pll_get_best_div_mul(struct sam9x60_pll *pll,
176 					 unsigned long rate,
177 					 unsigned long parent_rate,
178 					 bool update)
179 {
180 	const struct clk_pll_characteristics *characteristics =
181 							pll->characteristics;
182 	unsigned long bestremainder = ULONG_MAX;
183 	unsigned long maxdiv, mindiv, tmpdiv;
184 	long bestrate = -ERANGE;
185 	unsigned long bestdiv = 0;
186 	unsigned long bestmul = 0;
187 	unsigned long bestfrac = 0;
188 
189 	if (rate < characteristics->output[0].min ||
190 	    rate > characteristics->output[0].max)
191 		return -ERANGE;
192 
193 	if (!pll->characteristics->upll) {
194 		mindiv = parent_rate / rate;
195 		if (mindiv < 2)
196 			mindiv = 2;
197 
198 		maxdiv = DIV_ROUND_UP(parent_rate * PLL_MUL_MAX, rate);
199 		if (maxdiv > PLL_DIV_MAX)
200 			maxdiv = PLL_DIV_MAX;
201 	} else {
202 		mindiv = maxdiv = UPLL_DIV;
203 	}
204 
205 	for (tmpdiv = mindiv; tmpdiv <= maxdiv; tmpdiv++) {
206 		unsigned long remainder;
207 		unsigned long tmprate;
208 		unsigned long tmpmul;
209 		unsigned long tmpfrac = 0;
210 
211 		/*
212 		 * Calculate the multiplier associated with the current
213 		 * divider that provide the closest rate to the requested one.
214 		 */
215 		tmpmul = mult_frac(rate, tmpdiv, parent_rate);
216 		tmprate = mult_frac(parent_rate, tmpmul, tmpdiv);
217 		remainder = rate - tmprate;
218 
219 		if (remainder) {
220 			tmpfrac = DIV_ROUND_CLOSEST_ULL((u64)remainder * tmpdiv * (1 << 22),
221 							parent_rate);
222 
223 			tmprate += DIV_ROUND_CLOSEST_ULL((u64)tmpfrac * parent_rate,
224 							 tmpdiv * (1 << 22));
225 
226 			if (tmprate > rate)
227 				remainder = tmprate - rate;
228 			else
229 				remainder = rate - tmprate;
230 		}
231 
232 		/*
233 		 * Compare the remainder with the best remainder found until
234 		 * now and elect a new best multiplier/divider pair if the
235 		 * current remainder is smaller than the best one.
236 		 */
237 		if (remainder < bestremainder) {
238 			bestremainder = remainder;
239 			bestdiv = tmpdiv;
240 			bestmul = tmpmul;
241 			bestrate = tmprate;
242 			bestfrac = tmpfrac;
243 		}
244 
245 		/* We've found a perfect match!  */
246 		if (!remainder)
247 			break;
248 	}
249 
250 	/* Check if bestrate is a valid output rate  */
251 	if (bestrate < characteristics->output[0].min &&
252 	    bestrate > characteristics->output[0].max)
253 		return -ERANGE;
254 
255 	if (update) {
256 		pll->div = bestdiv - 1;
257 		pll->mul = bestmul - 1;
258 		pll->frac = bestfrac;
259 	}
260 
261 	return bestrate;
262 }
263 
264 static long sam9x60_pll_round_rate(struct clk_hw *hw, unsigned long rate,
265 				   unsigned long *parent_rate)
266 {
267 	struct sam9x60_pll *pll = to_sam9x60_pll(hw);
268 
269 	return sam9x60_pll_get_best_div_mul(pll, rate, *parent_rate, false);
270 }
271 
272 static int sam9x60_pll_set_rate(struct clk_hw *hw, unsigned long rate,
273 				unsigned long parent_rate)
274 {
275 	struct sam9x60_pll *pll = to_sam9x60_pll(hw);
276 
277 	return sam9x60_pll_get_best_div_mul(pll, rate, parent_rate, true);
278 }
279 
280 static const struct clk_ops pll_ops = {
281 	.prepare = sam9x60_pll_prepare,
282 	.unprepare = sam9x60_pll_unprepare,
283 	.is_prepared = sam9x60_pll_is_prepared,
284 	.recalc_rate = sam9x60_pll_recalc_rate,
285 	.round_rate = sam9x60_pll_round_rate,
286 	.set_rate = sam9x60_pll_set_rate,
287 };
288 
289 struct clk_hw * __init
290 sam9x60_clk_register_pll(struct regmap *regmap, spinlock_t *lock,
291 			 const char *name, const char *parent_name, u8 id,
292 			 const struct clk_pll_characteristics *characteristics)
293 {
294 	struct sam9x60_pll *pll;
295 	struct clk_hw *hw;
296 	struct clk_init_data init;
297 	unsigned int pllr;
298 	int ret;
299 
300 	if (id > PLL_MAX_ID)
301 		return ERR_PTR(-EINVAL);
302 
303 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
304 	if (!pll)
305 		return ERR_PTR(-ENOMEM);
306 
307 	init.name = name;
308 	init.ops = &pll_ops;
309 	init.parent_names = &parent_name;
310 	init.num_parents = 1;
311 	init.flags = CLK_SET_RATE_GATE;
312 
313 	pll->id = id;
314 	pll->hw.init = &init;
315 	pll->characteristics = characteristics;
316 	pll->regmap = regmap;
317 	pll->lock = lock;
318 
319 	regmap_write(regmap, PMC_PLL_UPDT, id);
320 	regmap_read(regmap, PMC_PLL_CTRL0, &pllr);
321 	pll->div = FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, pllr);
322 	regmap_read(regmap, PMC_PLL_CTRL1, &pllr);
323 	pll->mul = FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, pllr);
324 
325 	hw = &pll->hw;
326 	ret = clk_hw_register(NULL, hw);
327 	if (ret) {
328 		kfree(pll);
329 		hw = ERR_PTR(ret);
330 	}
331 
332 	return hw;
333 }
334 
335