1 /* 2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 */ 10 11 #include <linux/clk-provider.h> 12 #include <linux/clkdev.h> 13 #include <linux/clk/at91_pmc.h> 14 #include <linux/of.h> 15 #include <linux/mfd/syscon.h> 16 #include <linux/regmap.h> 17 18 #include "pmc.h" 19 20 #define to_clk_plldiv(hw) container_of(hw, struct clk_plldiv, hw) 21 22 struct clk_plldiv { 23 struct clk_hw hw; 24 struct regmap *regmap; 25 }; 26 27 static unsigned long clk_plldiv_recalc_rate(struct clk_hw *hw, 28 unsigned long parent_rate) 29 { 30 struct clk_plldiv *plldiv = to_clk_plldiv(hw); 31 unsigned int mckr; 32 33 regmap_read(plldiv->regmap, AT91_PMC_MCKR, &mckr); 34 35 if (mckr & AT91_PMC_PLLADIV2) 36 return parent_rate / 2; 37 38 return parent_rate; 39 } 40 41 static long clk_plldiv_round_rate(struct clk_hw *hw, unsigned long rate, 42 unsigned long *parent_rate) 43 { 44 unsigned long div; 45 46 if (rate > *parent_rate) 47 return *parent_rate; 48 div = *parent_rate / 2; 49 if (rate < div) 50 return div; 51 52 if (rate - div < *parent_rate - rate) 53 return div; 54 55 return *parent_rate; 56 } 57 58 static int clk_plldiv_set_rate(struct clk_hw *hw, unsigned long rate, 59 unsigned long parent_rate) 60 { 61 struct clk_plldiv *plldiv = to_clk_plldiv(hw); 62 63 if ((parent_rate != rate) && (parent_rate / 2 != rate)) 64 return -EINVAL; 65 66 regmap_update_bits(plldiv->regmap, AT91_PMC_MCKR, AT91_PMC_PLLADIV2, 67 parent_rate != rate ? AT91_PMC_PLLADIV2 : 0); 68 69 return 0; 70 } 71 72 static const struct clk_ops plldiv_ops = { 73 .recalc_rate = clk_plldiv_recalc_rate, 74 .round_rate = clk_plldiv_round_rate, 75 .set_rate = clk_plldiv_set_rate, 76 }; 77 78 static struct clk_hw * __init 79 at91_clk_register_plldiv(struct regmap *regmap, const char *name, 80 const char *parent_name) 81 { 82 struct clk_plldiv *plldiv; 83 struct clk_hw *hw; 84 struct clk_init_data init; 85 int ret; 86 87 plldiv = kzalloc(sizeof(*plldiv), GFP_KERNEL); 88 if (!plldiv) 89 return ERR_PTR(-ENOMEM); 90 91 init.name = name; 92 init.ops = &plldiv_ops; 93 init.parent_names = parent_name ? &parent_name : NULL; 94 init.num_parents = parent_name ? 1 : 0; 95 init.flags = CLK_SET_RATE_GATE; 96 97 plldiv->hw.init = &init; 98 plldiv->regmap = regmap; 99 100 hw = &plldiv->hw; 101 ret = clk_hw_register(NULL, &plldiv->hw); 102 if (ret) { 103 kfree(plldiv); 104 hw = ERR_PTR(ret); 105 } 106 107 return hw; 108 } 109 110 static void __init 111 of_at91sam9x5_clk_plldiv_setup(struct device_node *np) 112 { 113 struct clk_hw *hw; 114 const char *parent_name; 115 const char *name = np->name; 116 struct regmap *regmap; 117 118 parent_name = of_clk_get_parent_name(np, 0); 119 120 of_property_read_string(np, "clock-output-names", &name); 121 122 regmap = syscon_node_to_regmap(of_get_parent(np)); 123 if (IS_ERR(regmap)) 124 return; 125 126 hw = at91_clk_register_plldiv(regmap, name, parent_name); 127 if (IS_ERR(hw)) 128 return; 129 130 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); 131 } 132 CLK_OF_DECLARE(at91sam9x5_clk_plldiv, "atmel,at91sam9x5-clk-plldiv", 133 of_at91sam9x5_clk_plldiv_setup); 134