1 /* 2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 */ 10 11 #include <linux/clk-provider.h> 12 #include <linux/clkdev.h> 13 #include <linux/clk/at91_pmc.h> 14 #include <linux/of.h> 15 #include <linux/mfd/syscon.h> 16 #include <linux/regmap.h> 17 18 #include "pmc.h" 19 20 #define MASTER_SOURCE_MAX 4 21 22 #define MASTER_PRES_MASK 0x7 23 #define MASTER_PRES_MAX MASTER_PRES_MASK 24 #define MASTER_DIV_SHIFT 8 25 #define MASTER_DIV_MASK 0x3 26 27 #define to_clk_master(hw) container_of(hw, struct clk_master, hw) 28 29 struct clk_master { 30 struct clk_hw hw; 31 struct regmap *regmap; 32 const struct clk_master_layout *layout; 33 const struct clk_master_characteristics *characteristics; 34 }; 35 36 static inline bool clk_master_ready(struct regmap *regmap) 37 { 38 unsigned int status; 39 40 regmap_read(regmap, AT91_PMC_SR, &status); 41 42 return status & AT91_PMC_MCKRDY ? 1 : 0; 43 } 44 45 static int clk_master_prepare(struct clk_hw *hw) 46 { 47 struct clk_master *master = to_clk_master(hw); 48 49 while (!clk_master_ready(master->regmap)) 50 cpu_relax(); 51 52 return 0; 53 } 54 55 static int clk_master_is_prepared(struct clk_hw *hw) 56 { 57 struct clk_master *master = to_clk_master(hw); 58 59 return clk_master_ready(master->regmap); 60 } 61 62 static unsigned long clk_master_recalc_rate(struct clk_hw *hw, 63 unsigned long parent_rate) 64 { 65 u8 pres; 66 u8 div; 67 unsigned long rate = parent_rate; 68 struct clk_master *master = to_clk_master(hw); 69 const struct clk_master_layout *layout = master->layout; 70 const struct clk_master_characteristics *characteristics = 71 master->characteristics; 72 unsigned int mckr; 73 74 regmap_read(master->regmap, AT91_PMC_MCKR, &mckr); 75 mckr &= layout->mask; 76 77 pres = (mckr >> layout->pres_shift) & MASTER_PRES_MASK; 78 div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; 79 80 if (characteristics->have_div3_pres && pres == MASTER_PRES_MAX) 81 rate /= 3; 82 else 83 rate >>= pres; 84 85 rate /= characteristics->divisors[div]; 86 87 if (rate < characteristics->output.min) 88 pr_warn("master clk is underclocked"); 89 else if (rate > characteristics->output.max) 90 pr_warn("master clk is overclocked"); 91 92 return rate; 93 } 94 95 static u8 clk_master_get_parent(struct clk_hw *hw) 96 { 97 struct clk_master *master = to_clk_master(hw); 98 unsigned int mckr; 99 100 regmap_read(master->regmap, AT91_PMC_MCKR, &mckr); 101 102 return mckr & AT91_PMC_CSS; 103 } 104 105 static const struct clk_ops master_ops = { 106 .prepare = clk_master_prepare, 107 .is_prepared = clk_master_is_prepared, 108 .recalc_rate = clk_master_recalc_rate, 109 .get_parent = clk_master_get_parent, 110 }; 111 112 struct clk_hw * __init 113 at91_clk_register_master(struct regmap *regmap, 114 const char *name, int num_parents, 115 const char **parent_names, 116 const struct clk_master_layout *layout, 117 const struct clk_master_characteristics *characteristics) 118 { 119 struct clk_master *master; 120 struct clk_init_data init; 121 struct clk_hw *hw; 122 int ret; 123 124 if (!name || !num_parents || !parent_names) 125 return ERR_PTR(-EINVAL); 126 127 master = kzalloc(sizeof(*master), GFP_KERNEL); 128 if (!master) 129 return ERR_PTR(-ENOMEM); 130 131 init.name = name; 132 init.ops = &master_ops; 133 init.parent_names = parent_names; 134 init.num_parents = num_parents; 135 init.flags = 0; 136 137 master->hw.init = &init; 138 master->layout = layout; 139 master->characteristics = characteristics; 140 master->regmap = regmap; 141 142 hw = &master->hw; 143 ret = clk_hw_register(NULL, &master->hw); 144 if (ret) { 145 kfree(master); 146 hw = ERR_PTR(ret); 147 } 148 149 return hw; 150 } 151 152 153 const struct clk_master_layout at91rm9200_master_layout = { 154 .mask = 0x31F, 155 .pres_shift = 2, 156 }; 157 158 const struct clk_master_layout at91sam9x5_master_layout = { 159 .mask = 0x373, 160 .pres_shift = 4, 161 }; 162 163 164 static struct clk_master_characteristics * __init 165 of_at91_clk_master_get_characteristics(struct device_node *np) 166 { 167 struct clk_master_characteristics *characteristics; 168 169 characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL); 170 if (!characteristics) 171 return NULL; 172 173 if (of_at91_get_clk_range(np, "atmel,clk-output-range", &characteristics->output)) 174 goto out_free_characteristics; 175 176 of_property_read_u32_array(np, "atmel,clk-divisors", 177 characteristics->divisors, 4); 178 179 characteristics->have_div3_pres = 180 of_property_read_bool(np, "atmel,master-clk-have-div3-pres"); 181 182 return characteristics; 183 184 out_free_characteristics: 185 kfree(characteristics); 186 return NULL; 187 } 188 189 static void __init 190 of_at91_clk_master_setup(struct device_node *np, 191 const struct clk_master_layout *layout) 192 { 193 struct clk_hw *hw; 194 unsigned int num_parents; 195 const char *parent_names[MASTER_SOURCE_MAX]; 196 const char *name = np->name; 197 struct clk_master_characteristics *characteristics; 198 struct regmap *regmap; 199 200 num_parents = of_clk_get_parent_count(np); 201 if (num_parents == 0 || num_parents > MASTER_SOURCE_MAX) 202 return; 203 204 of_clk_parent_fill(np, parent_names, num_parents); 205 206 of_property_read_string(np, "clock-output-names", &name); 207 208 characteristics = of_at91_clk_master_get_characteristics(np); 209 if (!characteristics) 210 return; 211 212 regmap = syscon_node_to_regmap(of_get_parent(np)); 213 if (IS_ERR(regmap)) 214 return; 215 216 hw = at91_clk_register_master(regmap, name, num_parents, 217 parent_names, layout, 218 characteristics); 219 if (IS_ERR(hw)) 220 goto out_free_characteristics; 221 222 of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); 223 return; 224 225 out_free_characteristics: 226 kfree(characteristics); 227 } 228 229 static void __init of_at91rm9200_clk_master_setup(struct device_node *np) 230 { 231 of_at91_clk_master_setup(np, &at91rm9200_master_layout); 232 } 233 CLK_OF_DECLARE(at91rm9200_clk_master, "atmel,at91rm9200-clk-master", 234 of_at91rm9200_clk_master_setup); 235 236 static void __init of_at91sam9x5_clk_master_setup(struct device_node *np) 237 { 238 of_at91_clk_master_setup(np, &at91sam9x5_master_layout); 239 } 240 CLK_OF_DECLARE(at91sam9x5_clk_master, "atmel,at91sam9x5-clk-master", 241 of_at91sam9x5_clk_master_setup); 242