1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2015 Atmel Corporation, 4 * Nicolas Ferre <nicolas.ferre@atmel.com> 5 * 6 * Based on clk-programmable & clk-peripheral drivers by Boris BREZILLON. 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/clk-provider.h> 11 #include <linux/clkdev.h> 12 #include <linux/clk/at91_pmc.h> 13 #include <linux/of.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/regmap.h> 16 17 #include "pmc.h" 18 19 #define GENERATED_MAX_DIV 255 20 21 struct clk_generated { 22 struct clk_hw hw; 23 struct regmap *regmap; 24 struct clk_range range; 25 spinlock_t *lock; 26 u32 *mux_table; 27 u32 id; 28 u32 gckdiv; 29 const struct clk_pcr_layout *layout; 30 struct at91_clk_pms pms; 31 u8 parent_id; 32 int chg_pid; 33 }; 34 35 #define to_clk_generated(hw) \ 36 container_of(hw, struct clk_generated, hw) 37 38 static int clk_generated_set(struct clk_generated *gck, int status) 39 { 40 unsigned long flags; 41 unsigned int enable = status ? AT91_PMC_PCR_GCKEN : 0; 42 43 spin_lock_irqsave(gck->lock, flags); 44 regmap_write(gck->regmap, gck->layout->offset, 45 (gck->id & gck->layout->pid_mask)); 46 regmap_update_bits(gck->regmap, gck->layout->offset, 47 AT91_PMC_PCR_GCKDIV_MASK | gck->layout->gckcss_mask | 48 gck->layout->cmd | enable, 49 field_prep(gck->layout->gckcss_mask, gck->parent_id) | 50 gck->layout->cmd | 51 FIELD_PREP(AT91_PMC_PCR_GCKDIV_MASK, gck->gckdiv) | 52 enable); 53 spin_unlock_irqrestore(gck->lock, flags); 54 55 return 0; 56 } 57 58 static int clk_generated_enable(struct clk_hw *hw) 59 { 60 struct clk_generated *gck = to_clk_generated(hw); 61 62 pr_debug("GCLK: %s, gckdiv = %d, parent id = %d\n", 63 __func__, gck->gckdiv, gck->parent_id); 64 65 clk_generated_set(gck, 1); 66 67 return 0; 68 } 69 70 static void clk_generated_disable(struct clk_hw *hw) 71 { 72 struct clk_generated *gck = to_clk_generated(hw); 73 unsigned long flags; 74 75 spin_lock_irqsave(gck->lock, flags); 76 regmap_write(gck->regmap, gck->layout->offset, 77 (gck->id & gck->layout->pid_mask)); 78 regmap_update_bits(gck->regmap, gck->layout->offset, 79 gck->layout->cmd | AT91_PMC_PCR_GCKEN, 80 gck->layout->cmd); 81 spin_unlock_irqrestore(gck->lock, flags); 82 } 83 84 static int clk_generated_is_enabled(struct clk_hw *hw) 85 { 86 struct clk_generated *gck = to_clk_generated(hw); 87 unsigned long flags; 88 unsigned int status; 89 90 spin_lock_irqsave(gck->lock, flags); 91 regmap_write(gck->regmap, gck->layout->offset, 92 (gck->id & gck->layout->pid_mask)); 93 regmap_read(gck->regmap, gck->layout->offset, &status); 94 spin_unlock_irqrestore(gck->lock, flags); 95 96 return !!(status & AT91_PMC_PCR_GCKEN); 97 } 98 99 static unsigned long 100 clk_generated_recalc_rate(struct clk_hw *hw, 101 unsigned long parent_rate) 102 { 103 struct clk_generated *gck = to_clk_generated(hw); 104 105 return DIV_ROUND_CLOSEST(parent_rate, gck->gckdiv + 1); 106 } 107 108 static void clk_generated_best_diff(struct clk_rate_request *req, 109 struct clk_hw *parent, 110 unsigned long parent_rate, u32 div, 111 int *best_diff, long *best_rate) 112 { 113 unsigned long tmp_rate; 114 int tmp_diff; 115 116 if (!div) 117 tmp_rate = parent_rate; 118 else 119 tmp_rate = parent_rate / div; 120 tmp_diff = abs(req->rate - tmp_rate); 121 122 if (*best_diff < 0 || *best_diff >= tmp_diff) { 123 *best_rate = tmp_rate; 124 *best_diff = tmp_diff; 125 req->best_parent_rate = parent_rate; 126 req->best_parent_hw = parent; 127 } 128 } 129 130 static int clk_generated_determine_rate(struct clk_hw *hw, 131 struct clk_rate_request *req) 132 { 133 struct clk_generated *gck = to_clk_generated(hw); 134 struct clk_hw *parent = NULL; 135 struct clk_rate_request req_parent = *req; 136 long best_rate = -EINVAL; 137 unsigned long min_rate, parent_rate; 138 int best_diff = -1; 139 int i; 140 u32 div; 141 142 /* do not look for a rate that is outside of our range */ 143 if (gck->range.max && req->rate > gck->range.max) 144 req->rate = gck->range.max; 145 if (gck->range.min && req->rate < gck->range.min) 146 req->rate = gck->range.min; 147 148 for (i = 0; i < clk_hw_get_num_parents(hw); i++) { 149 if (gck->chg_pid == i) 150 continue; 151 152 parent = clk_hw_get_parent_by_index(hw, i); 153 if (!parent) 154 continue; 155 156 parent_rate = clk_hw_get_rate(parent); 157 min_rate = DIV_ROUND_CLOSEST(parent_rate, GENERATED_MAX_DIV + 1); 158 if (!parent_rate || 159 (gck->range.max && min_rate > gck->range.max)) 160 continue; 161 162 div = DIV_ROUND_CLOSEST(parent_rate, req->rate); 163 if (div > GENERATED_MAX_DIV + 1) 164 div = GENERATED_MAX_DIV + 1; 165 166 clk_generated_best_diff(req, parent, parent_rate, div, 167 &best_diff, &best_rate); 168 169 if (!best_diff) 170 break; 171 } 172 173 /* 174 * The audio_pll rate can be modified, unlike the five others clocks 175 * that should never be altered. 176 * The audio_pll can technically be used by multiple consumers. However, 177 * with the rate locking, the first consumer to enable to clock will be 178 * the one definitely setting the rate of the clock. 179 * Since audio IPs are most likely to request the same rate, we enforce 180 * that the only clks able to modify gck rate are those of audio IPs. 181 */ 182 183 if (gck->chg_pid < 0) 184 goto end; 185 186 parent = clk_hw_get_parent_by_index(hw, gck->chg_pid); 187 if (!parent) 188 goto end; 189 190 for (div = 1; div < GENERATED_MAX_DIV + 2; div++) { 191 req_parent.rate = req->rate * div; 192 if (__clk_determine_rate(parent, &req_parent)) 193 continue; 194 clk_generated_best_diff(req, parent, req_parent.rate, div, 195 &best_diff, &best_rate); 196 197 if (!best_diff) 198 break; 199 } 200 201 end: 202 pr_debug("GCLK: %s, best_rate = %ld, parent clk: %s @ %ld\n", 203 __func__, best_rate, 204 __clk_get_name((req->best_parent_hw)->clk), 205 req->best_parent_rate); 206 207 if (best_rate < 0 || (gck->range.max && best_rate > gck->range.max)) 208 return -EINVAL; 209 210 req->rate = best_rate; 211 return 0; 212 } 213 214 /* No modification of hardware as we have the flag CLK_SET_PARENT_GATE set */ 215 static int clk_generated_set_parent(struct clk_hw *hw, u8 index) 216 { 217 struct clk_generated *gck = to_clk_generated(hw); 218 219 if (index >= clk_hw_get_num_parents(hw)) 220 return -EINVAL; 221 222 if (gck->mux_table) 223 gck->parent_id = clk_mux_index_to_val(gck->mux_table, 0, index); 224 else 225 gck->parent_id = index; 226 227 return 0; 228 } 229 230 static u8 clk_generated_get_parent(struct clk_hw *hw) 231 { 232 struct clk_generated *gck = to_clk_generated(hw); 233 234 return gck->parent_id; 235 } 236 237 /* No modification of hardware as we have the flag CLK_SET_RATE_GATE set */ 238 static int clk_generated_set_rate(struct clk_hw *hw, 239 unsigned long rate, 240 unsigned long parent_rate) 241 { 242 struct clk_generated *gck = to_clk_generated(hw); 243 u32 div; 244 245 if (!rate) 246 return -EINVAL; 247 248 if (gck->range.max && rate > gck->range.max) 249 return -EINVAL; 250 251 div = DIV_ROUND_CLOSEST(parent_rate, rate); 252 if (div > GENERATED_MAX_DIV + 1 || !div) 253 return -EINVAL; 254 255 gck->gckdiv = div - 1; 256 return 0; 257 } 258 259 static int clk_generated_save_context(struct clk_hw *hw) 260 { 261 struct clk_generated *gck = to_clk_generated(hw); 262 263 gck->pms.status = clk_generated_is_enabled(&gck->hw); 264 265 return 0; 266 } 267 268 static void clk_generated_restore_context(struct clk_hw *hw) 269 { 270 struct clk_generated *gck = to_clk_generated(hw); 271 272 if (gck->pms.status) 273 clk_generated_set(gck, gck->pms.status); 274 } 275 276 static const struct clk_ops generated_ops = { 277 .enable = clk_generated_enable, 278 .disable = clk_generated_disable, 279 .is_enabled = clk_generated_is_enabled, 280 .recalc_rate = clk_generated_recalc_rate, 281 .determine_rate = clk_generated_determine_rate, 282 .get_parent = clk_generated_get_parent, 283 .set_parent = clk_generated_set_parent, 284 .set_rate = clk_generated_set_rate, 285 .save_context = clk_generated_save_context, 286 .restore_context = clk_generated_restore_context, 287 }; 288 289 /** 290 * clk_generated_startup - Initialize a given clock to its default parent and 291 * divisor parameter. 292 * 293 * @gck: Generated clock to set the startup parameters for. 294 * 295 * Take parameters from the hardware and update local clock configuration 296 * accordingly. 297 */ 298 static void clk_generated_startup(struct clk_generated *gck) 299 { 300 u32 tmp; 301 unsigned long flags; 302 303 spin_lock_irqsave(gck->lock, flags); 304 regmap_write(gck->regmap, gck->layout->offset, 305 (gck->id & gck->layout->pid_mask)); 306 regmap_read(gck->regmap, gck->layout->offset, &tmp); 307 spin_unlock_irqrestore(gck->lock, flags); 308 309 gck->parent_id = field_get(gck->layout->gckcss_mask, tmp); 310 gck->gckdiv = FIELD_GET(AT91_PMC_PCR_GCKDIV_MASK, tmp); 311 } 312 313 struct clk_hw * __init 314 at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock, 315 const struct clk_pcr_layout *layout, 316 const char *name, const char **parent_names, 317 u32 *mux_table, u8 num_parents, u8 id, 318 const struct clk_range *range, 319 int chg_pid) 320 { 321 struct clk_generated *gck; 322 struct clk_init_data init; 323 struct clk_hw *hw; 324 int ret; 325 326 gck = kzalloc(sizeof(*gck), GFP_KERNEL); 327 if (!gck) 328 return ERR_PTR(-ENOMEM); 329 330 init.name = name; 331 init.ops = &generated_ops; 332 init.parent_names = parent_names; 333 init.num_parents = num_parents; 334 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; 335 if (chg_pid >= 0) 336 init.flags |= CLK_SET_RATE_PARENT; 337 338 gck->id = id; 339 gck->hw.init = &init; 340 gck->regmap = regmap; 341 gck->lock = lock; 342 gck->range = *range; 343 gck->chg_pid = chg_pid; 344 gck->layout = layout; 345 gck->mux_table = mux_table; 346 347 clk_generated_startup(gck); 348 hw = &gck->hw; 349 ret = clk_hw_register(NULL, &gck->hw); 350 if (ret) { 351 kfree(gck); 352 hw = ERR_PTR(ret); 353 } 354 355 return hw; 356 } 357