1 /* 2 * Copyright (C) 2015 Atmel Corporation, 3 * Nicolas Ferre <nicolas.ferre@atmel.com> 4 * 5 * Based on clk-programmable & clk-peripheral drivers by Boris BREZILLON. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 */ 13 14 #include <linux/bitfield.h> 15 #include <linux/clk-provider.h> 16 #include <linux/clkdev.h> 17 #include <linux/clk/at91_pmc.h> 18 #include <linux/of.h> 19 #include <linux/mfd/syscon.h> 20 #include <linux/regmap.h> 21 22 #include "pmc.h" 23 24 #define GENERATED_MAX_DIV 255 25 26 #define GCK_INDEX_DT_AUDIO_PLL 5 27 28 struct clk_generated { 29 struct clk_hw hw; 30 struct regmap *regmap; 31 struct clk_range range; 32 spinlock_t *lock; 33 u32 id; 34 u32 gckdiv; 35 const struct clk_pcr_layout *layout; 36 u8 parent_id; 37 bool audio_pll_allowed; 38 }; 39 40 #define to_clk_generated(hw) \ 41 container_of(hw, struct clk_generated, hw) 42 43 static int clk_generated_enable(struct clk_hw *hw) 44 { 45 struct clk_generated *gck = to_clk_generated(hw); 46 unsigned long flags; 47 48 pr_debug("GCLK: %s, gckdiv = %d, parent id = %d\n", 49 __func__, gck->gckdiv, gck->parent_id); 50 51 spin_lock_irqsave(gck->lock, flags); 52 regmap_write(gck->regmap, gck->layout->offset, 53 (gck->id & gck->layout->pid_mask)); 54 regmap_update_bits(gck->regmap, gck->layout->offset, 55 AT91_PMC_PCR_GCKDIV_MASK | gck->layout->gckcss_mask | 56 gck->layout->cmd | AT91_PMC_PCR_GCKEN, 57 field_prep(gck->layout->gckcss_mask, gck->parent_id) | 58 gck->layout->cmd | 59 FIELD_PREP(AT91_PMC_PCR_GCKDIV_MASK, gck->gckdiv) | 60 AT91_PMC_PCR_GCKEN); 61 spin_unlock_irqrestore(gck->lock, flags); 62 return 0; 63 } 64 65 static void clk_generated_disable(struct clk_hw *hw) 66 { 67 struct clk_generated *gck = to_clk_generated(hw); 68 unsigned long flags; 69 70 spin_lock_irqsave(gck->lock, flags); 71 regmap_write(gck->regmap, gck->layout->offset, 72 (gck->id & gck->layout->pid_mask)); 73 regmap_update_bits(gck->regmap, gck->layout->offset, 74 gck->layout->cmd | AT91_PMC_PCR_GCKEN, 75 gck->layout->cmd); 76 spin_unlock_irqrestore(gck->lock, flags); 77 } 78 79 static int clk_generated_is_enabled(struct clk_hw *hw) 80 { 81 struct clk_generated *gck = to_clk_generated(hw); 82 unsigned long flags; 83 unsigned int status; 84 85 spin_lock_irqsave(gck->lock, flags); 86 regmap_write(gck->regmap, gck->layout->offset, 87 (gck->id & gck->layout->pid_mask)); 88 regmap_read(gck->regmap, gck->layout->offset, &status); 89 spin_unlock_irqrestore(gck->lock, flags); 90 91 return status & AT91_PMC_PCR_GCKEN ? 1 : 0; 92 } 93 94 static unsigned long 95 clk_generated_recalc_rate(struct clk_hw *hw, 96 unsigned long parent_rate) 97 { 98 struct clk_generated *gck = to_clk_generated(hw); 99 100 return DIV_ROUND_CLOSEST(parent_rate, gck->gckdiv + 1); 101 } 102 103 static void clk_generated_best_diff(struct clk_rate_request *req, 104 struct clk_hw *parent, 105 unsigned long parent_rate, u32 div, 106 int *best_diff, long *best_rate) 107 { 108 unsigned long tmp_rate; 109 int tmp_diff; 110 111 if (!div) 112 tmp_rate = parent_rate; 113 else 114 tmp_rate = parent_rate / div; 115 tmp_diff = abs(req->rate - tmp_rate); 116 117 if (*best_diff < 0 || *best_diff > tmp_diff) { 118 *best_rate = tmp_rate; 119 *best_diff = tmp_diff; 120 req->best_parent_rate = parent_rate; 121 req->best_parent_hw = parent; 122 } 123 } 124 125 static int clk_generated_determine_rate(struct clk_hw *hw, 126 struct clk_rate_request *req) 127 { 128 struct clk_generated *gck = to_clk_generated(hw); 129 struct clk_hw *parent = NULL; 130 struct clk_rate_request req_parent = *req; 131 long best_rate = -EINVAL; 132 unsigned long min_rate, parent_rate; 133 int best_diff = -1; 134 int i; 135 u32 div; 136 137 for (i = 0; i < clk_hw_get_num_parents(hw) - 1; i++) { 138 parent = clk_hw_get_parent_by_index(hw, i); 139 if (!parent) 140 continue; 141 142 parent_rate = clk_hw_get_rate(parent); 143 min_rate = DIV_ROUND_CLOSEST(parent_rate, GENERATED_MAX_DIV + 1); 144 if (!parent_rate || 145 (gck->range.max && min_rate > gck->range.max)) 146 continue; 147 148 div = DIV_ROUND_CLOSEST(parent_rate, req->rate); 149 150 clk_generated_best_diff(req, parent, parent_rate, div, 151 &best_diff, &best_rate); 152 153 if (!best_diff) 154 break; 155 } 156 157 /* 158 * The audio_pll rate can be modified, unlike the five others clocks 159 * that should never be altered. 160 * The audio_pll can technically be used by multiple consumers. However, 161 * with the rate locking, the first consumer to enable to clock will be 162 * the one definitely setting the rate of the clock. 163 * Since audio IPs are most likely to request the same rate, we enforce 164 * that the only clks able to modify gck rate are those of audio IPs. 165 */ 166 167 if (!gck->audio_pll_allowed) 168 goto end; 169 170 parent = clk_hw_get_parent_by_index(hw, GCK_INDEX_DT_AUDIO_PLL); 171 if (!parent) 172 goto end; 173 174 for (div = 1; div < GENERATED_MAX_DIV + 2; div++) { 175 req_parent.rate = req->rate * div; 176 __clk_determine_rate(parent, &req_parent); 177 clk_generated_best_diff(req, parent, req_parent.rate, div, 178 &best_diff, &best_rate); 179 180 if (!best_diff) 181 break; 182 } 183 184 end: 185 pr_debug("GCLK: %s, best_rate = %ld, parent clk: %s @ %ld\n", 186 __func__, best_rate, 187 __clk_get_name((req->best_parent_hw)->clk), 188 req->best_parent_rate); 189 190 if (best_rate < 0) 191 return best_rate; 192 193 req->rate = best_rate; 194 return 0; 195 } 196 197 /* No modification of hardware as we have the flag CLK_SET_PARENT_GATE set */ 198 static int clk_generated_set_parent(struct clk_hw *hw, u8 index) 199 { 200 struct clk_generated *gck = to_clk_generated(hw); 201 202 if (index >= clk_hw_get_num_parents(hw)) 203 return -EINVAL; 204 205 gck->parent_id = index; 206 return 0; 207 } 208 209 static u8 clk_generated_get_parent(struct clk_hw *hw) 210 { 211 struct clk_generated *gck = to_clk_generated(hw); 212 213 return gck->parent_id; 214 } 215 216 /* No modification of hardware as we have the flag CLK_SET_RATE_GATE set */ 217 static int clk_generated_set_rate(struct clk_hw *hw, 218 unsigned long rate, 219 unsigned long parent_rate) 220 { 221 struct clk_generated *gck = to_clk_generated(hw); 222 u32 div; 223 224 if (!rate) 225 return -EINVAL; 226 227 if (gck->range.max && rate > gck->range.max) 228 return -EINVAL; 229 230 div = DIV_ROUND_CLOSEST(parent_rate, rate); 231 if (div > GENERATED_MAX_DIV + 1 || !div) 232 return -EINVAL; 233 234 gck->gckdiv = div - 1; 235 return 0; 236 } 237 238 static const struct clk_ops generated_ops = { 239 .enable = clk_generated_enable, 240 .disable = clk_generated_disable, 241 .is_enabled = clk_generated_is_enabled, 242 .recalc_rate = clk_generated_recalc_rate, 243 .determine_rate = clk_generated_determine_rate, 244 .get_parent = clk_generated_get_parent, 245 .set_parent = clk_generated_set_parent, 246 .set_rate = clk_generated_set_rate, 247 }; 248 249 /** 250 * clk_generated_startup - Initialize a given clock to its default parent and 251 * divisor parameter. 252 * 253 * @gck: Generated clock to set the startup parameters for. 254 * 255 * Take parameters from the hardware and update local clock configuration 256 * accordingly. 257 */ 258 static void clk_generated_startup(struct clk_generated *gck) 259 { 260 u32 tmp; 261 unsigned long flags; 262 263 spin_lock_irqsave(gck->lock, flags); 264 regmap_write(gck->regmap, gck->layout->offset, 265 (gck->id & gck->layout->pid_mask)); 266 regmap_read(gck->regmap, gck->layout->offset, &tmp); 267 spin_unlock_irqrestore(gck->lock, flags); 268 269 gck->parent_id = field_get(gck->layout->gckcss_mask, tmp); 270 gck->gckdiv = FIELD_GET(AT91_PMC_PCR_GCKDIV_MASK, tmp); 271 } 272 273 struct clk_hw * __init 274 at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock, 275 const struct clk_pcr_layout *layout, 276 const char *name, const char **parent_names, 277 u8 num_parents, u8 id, bool pll_audio, 278 const struct clk_range *range) 279 { 280 struct clk_generated *gck; 281 struct clk_init_data init; 282 struct clk_hw *hw; 283 int ret; 284 285 gck = kzalloc(sizeof(*gck), GFP_KERNEL); 286 if (!gck) 287 return ERR_PTR(-ENOMEM); 288 289 init.name = name; 290 init.ops = &generated_ops; 291 init.parent_names = parent_names; 292 init.num_parents = num_parents; 293 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | 294 CLK_SET_RATE_PARENT; 295 296 gck->id = id; 297 gck->hw.init = &init; 298 gck->regmap = regmap; 299 gck->lock = lock; 300 gck->range = *range; 301 gck->audio_pll_allowed = pll_audio; 302 gck->layout = layout; 303 304 clk_generated_startup(gck); 305 hw = &gck->hw; 306 ret = clk_hw_register(NULL, &gck->hw); 307 if (ret) { 308 kfree(gck); 309 hw = ERR_PTR(ret); 310 } else { 311 pmc_register_id(id); 312 } 313 314 return hw; 315 } 316