1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2015 Atmel Corporation, 4 * Nicolas Ferre <nicolas.ferre@atmel.com> 5 * 6 * Based on clk-programmable & clk-peripheral drivers by Boris BREZILLON. 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/clk-provider.h> 11 #include <linux/clkdev.h> 12 #include <linux/clk/at91_pmc.h> 13 #include <linux/of.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/regmap.h> 16 17 #include "pmc.h" 18 19 #define GENERATED_MAX_DIV 255 20 21 #define GCK_INDEX_DT_AUDIO_PLL 5 22 23 struct clk_generated { 24 struct clk_hw hw; 25 struct regmap *regmap; 26 struct clk_range range; 27 spinlock_t *lock; 28 u32 id; 29 u32 gckdiv; 30 const struct clk_pcr_layout *layout; 31 u8 parent_id; 32 bool audio_pll_allowed; 33 }; 34 35 #define to_clk_generated(hw) \ 36 container_of(hw, struct clk_generated, hw) 37 38 static int clk_generated_enable(struct clk_hw *hw) 39 { 40 struct clk_generated *gck = to_clk_generated(hw); 41 unsigned long flags; 42 43 pr_debug("GCLK: %s, gckdiv = %d, parent id = %d\n", 44 __func__, gck->gckdiv, gck->parent_id); 45 46 spin_lock_irqsave(gck->lock, flags); 47 regmap_write(gck->regmap, gck->layout->offset, 48 (gck->id & gck->layout->pid_mask)); 49 regmap_update_bits(gck->regmap, gck->layout->offset, 50 AT91_PMC_PCR_GCKDIV_MASK | gck->layout->gckcss_mask | 51 gck->layout->cmd | AT91_PMC_PCR_GCKEN, 52 field_prep(gck->layout->gckcss_mask, gck->parent_id) | 53 gck->layout->cmd | 54 FIELD_PREP(AT91_PMC_PCR_GCKDIV_MASK, gck->gckdiv) | 55 AT91_PMC_PCR_GCKEN); 56 spin_unlock_irqrestore(gck->lock, flags); 57 return 0; 58 } 59 60 static void clk_generated_disable(struct clk_hw *hw) 61 { 62 struct clk_generated *gck = to_clk_generated(hw); 63 unsigned long flags; 64 65 spin_lock_irqsave(gck->lock, flags); 66 regmap_write(gck->regmap, gck->layout->offset, 67 (gck->id & gck->layout->pid_mask)); 68 regmap_update_bits(gck->regmap, gck->layout->offset, 69 gck->layout->cmd | AT91_PMC_PCR_GCKEN, 70 gck->layout->cmd); 71 spin_unlock_irqrestore(gck->lock, flags); 72 } 73 74 static int clk_generated_is_enabled(struct clk_hw *hw) 75 { 76 struct clk_generated *gck = to_clk_generated(hw); 77 unsigned long flags; 78 unsigned int status; 79 80 spin_lock_irqsave(gck->lock, flags); 81 regmap_write(gck->regmap, gck->layout->offset, 82 (gck->id & gck->layout->pid_mask)); 83 regmap_read(gck->regmap, gck->layout->offset, &status); 84 spin_unlock_irqrestore(gck->lock, flags); 85 86 return status & AT91_PMC_PCR_GCKEN ? 1 : 0; 87 } 88 89 static unsigned long 90 clk_generated_recalc_rate(struct clk_hw *hw, 91 unsigned long parent_rate) 92 { 93 struct clk_generated *gck = to_clk_generated(hw); 94 95 return DIV_ROUND_CLOSEST(parent_rate, gck->gckdiv + 1); 96 } 97 98 static void clk_generated_best_diff(struct clk_rate_request *req, 99 struct clk_hw *parent, 100 unsigned long parent_rate, u32 div, 101 int *best_diff, long *best_rate) 102 { 103 unsigned long tmp_rate; 104 int tmp_diff; 105 106 if (!div) 107 tmp_rate = parent_rate; 108 else 109 tmp_rate = parent_rate / div; 110 tmp_diff = abs(req->rate - tmp_rate); 111 112 if (*best_diff < 0 || *best_diff > tmp_diff) { 113 *best_rate = tmp_rate; 114 *best_diff = tmp_diff; 115 req->best_parent_rate = parent_rate; 116 req->best_parent_hw = parent; 117 } 118 } 119 120 static int clk_generated_determine_rate(struct clk_hw *hw, 121 struct clk_rate_request *req) 122 { 123 struct clk_generated *gck = to_clk_generated(hw); 124 struct clk_hw *parent = NULL; 125 struct clk_rate_request req_parent = *req; 126 long best_rate = -EINVAL; 127 unsigned long min_rate, parent_rate; 128 int best_diff = -1; 129 int i; 130 u32 div; 131 132 for (i = 0; i < clk_hw_get_num_parents(hw) - 1; i++) { 133 parent = clk_hw_get_parent_by_index(hw, i); 134 if (!parent) 135 continue; 136 137 parent_rate = clk_hw_get_rate(parent); 138 min_rate = DIV_ROUND_CLOSEST(parent_rate, GENERATED_MAX_DIV + 1); 139 if (!parent_rate || 140 (gck->range.max && min_rate > gck->range.max)) 141 continue; 142 143 div = DIV_ROUND_CLOSEST(parent_rate, req->rate); 144 145 clk_generated_best_diff(req, parent, parent_rate, div, 146 &best_diff, &best_rate); 147 148 if (!best_diff) 149 break; 150 } 151 152 /* 153 * The audio_pll rate can be modified, unlike the five others clocks 154 * that should never be altered. 155 * The audio_pll can technically be used by multiple consumers. However, 156 * with the rate locking, the first consumer to enable to clock will be 157 * the one definitely setting the rate of the clock. 158 * Since audio IPs are most likely to request the same rate, we enforce 159 * that the only clks able to modify gck rate are those of audio IPs. 160 */ 161 162 if (!gck->audio_pll_allowed) 163 goto end; 164 165 parent = clk_hw_get_parent_by_index(hw, GCK_INDEX_DT_AUDIO_PLL); 166 if (!parent) 167 goto end; 168 169 for (div = 1; div < GENERATED_MAX_DIV + 2; div++) { 170 req_parent.rate = req->rate * div; 171 __clk_determine_rate(parent, &req_parent); 172 clk_generated_best_diff(req, parent, req_parent.rate, div, 173 &best_diff, &best_rate); 174 175 if (!best_diff) 176 break; 177 } 178 179 end: 180 pr_debug("GCLK: %s, best_rate = %ld, parent clk: %s @ %ld\n", 181 __func__, best_rate, 182 __clk_get_name((req->best_parent_hw)->clk), 183 req->best_parent_rate); 184 185 if (best_rate < 0) 186 return best_rate; 187 188 req->rate = best_rate; 189 return 0; 190 } 191 192 /* No modification of hardware as we have the flag CLK_SET_PARENT_GATE set */ 193 static int clk_generated_set_parent(struct clk_hw *hw, u8 index) 194 { 195 struct clk_generated *gck = to_clk_generated(hw); 196 197 if (index >= clk_hw_get_num_parents(hw)) 198 return -EINVAL; 199 200 gck->parent_id = index; 201 return 0; 202 } 203 204 static u8 clk_generated_get_parent(struct clk_hw *hw) 205 { 206 struct clk_generated *gck = to_clk_generated(hw); 207 208 return gck->parent_id; 209 } 210 211 /* No modification of hardware as we have the flag CLK_SET_RATE_GATE set */ 212 static int clk_generated_set_rate(struct clk_hw *hw, 213 unsigned long rate, 214 unsigned long parent_rate) 215 { 216 struct clk_generated *gck = to_clk_generated(hw); 217 u32 div; 218 219 if (!rate) 220 return -EINVAL; 221 222 if (gck->range.max && rate > gck->range.max) 223 return -EINVAL; 224 225 div = DIV_ROUND_CLOSEST(parent_rate, rate); 226 if (div > GENERATED_MAX_DIV + 1 || !div) 227 return -EINVAL; 228 229 gck->gckdiv = div - 1; 230 return 0; 231 } 232 233 static const struct clk_ops generated_ops = { 234 .enable = clk_generated_enable, 235 .disable = clk_generated_disable, 236 .is_enabled = clk_generated_is_enabled, 237 .recalc_rate = clk_generated_recalc_rate, 238 .determine_rate = clk_generated_determine_rate, 239 .get_parent = clk_generated_get_parent, 240 .set_parent = clk_generated_set_parent, 241 .set_rate = clk_generated_set_rate, 242 }; 243 244 /** 245 * clk_generated_startup - Initialize a given clock to its default parent and 246 * divisor parameter. 247 * 248 * @gck: Generated clock to set the startup parameters for. 249 * 250 * Take parameters from the hardware and update local clock configuration 251 * accordingly. 252 */ 253 static void clk_generated_startup(struct clk_generated *gck) 254 { 255 u32 tmp; 256 unsigned long flags; 257 258 spin_lock_irqsave(gck->lock, flags); 259 regmap_write(gck->regmap, gck->layout->offset, 260 (gck->id & gck->layout->pid_mask)); 261 regmap_read(gck->regmap, gck->layout->offset, &tmp); 262 spin_unlock_irqrestore(gck->lock, flags); 263 264 gck->parent_id = field_get(gck->layout->gckcss_mask, tmp); 265 gck->gckdiv = FIELD_GET(AT91_PMC_PCR_GCKDIV_MASK, tmp); 266 } 267 268 struct clk_hw * __init 269 at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock, 270 const struct clk_pcr_layout *layout, 271 const char *name, const char **parent_names, 272 u8 num_parents, u8 id, bool pll_audio, 273 const struct clk_range *range) 274 { 275 struct clk_generated *gck; 276 struct clk_init_data init; 277 struct clk_hw *hw; 278 int ret; 279 280 gck = kzalloc(sizeof(*gck), GFP_KERNEL); 281 if (!gck) 282 return ERR_PTR(-ENOMEM); 283 284 init.name = name; 285 init.ops = &generated_ops; 286 init.parent_names = parent_names; 287 init.num_parents = num_parents; 288 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | 289 CLK_SET_RATE_PARENT; 290 291 gck->id = id; 292 gck->hw.init = &init; 293 gck->regmap = regmap; 294 gck->lock = lock; 295 gck->range = *range; 296 gck->audio_pll_allowed = pll_audio; 297 gck->layout = layout; 298 299 clk_generated_startup(gck); 300 hw = &gck->hw; 301 ret = clk_hw_register(NULL, &gck->hw); 302 if (ret) { 303 kfree(gck); 304 hw = ERR_PTR(ret); 305 } else { 306 pmc_register_id(id); 307 } 308 309 return hw; 310 } 311