1 /* 2 * Copyright (C) 2016 Atmel Corporation, 3 * Songjun Wu <songjun.wu@atmel.com>, 4 * Nicolas Ferre <nicolas.ferre@atmel.com> 5 * Copyright (C) 2017 Free Electrons, 6 * Quentin Schulz <quentin.schulz@free-electrons.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * The Sama5d2 SoC has two audio PLLs (PMC and PAD) that shares the same parent 14 * (FRAC). FRAC can output between 620 and 700MHz and only multiply the rate of 15 * its own parent. PMC and PAD can then divide the FRAC rate to best match the 16 * asked rate. 17 * 18 * Traits of FRAC clock: 19 * enable - clk_enable writes nd, fracr parameters and enables PLL 20 * rate - rate is adjustable. 21 * clk->rate = parent->rate * ((nd + 1) + (fracr / 2^22)) 22 * parent - fixed parent. No clk_set_parent support 23 * 24 * Traits of PMC clock: 25 * enable - clk_enable writes qdpmc, and enables PMC output 26 * rate - rate is adjustable. 27 * clk->rate = parent->rate / (qdpmc + 1) 28 * parent - fixed parent. No clk_set_parent support 29 * 30 * Traits of PAD clock: 31 * enable - clk_enable writes divisors and enables PAD output 32 * rate - rate is adjustable. 33 * clk->rate = parent->rate / (qdaudio * div)) 34 * parent - fixed parent. No clk_set_parent support 35 * 36 */ 37 38 #include <linux/clk.h> 39 #include <linux/clk-provider.h> 40 #include <linux/clk/at91_pmc.h> 41 #include <linux/of.h> 42 #include <linux/mfd/syscon.h> 43 #include <linux/regmap.h> 44 #include <linux/slab.h> 45 46 #define AUDIO_PLL_DIV_FRAC BIT(22) 47 #define AUDIO_PLL_ND_MAX (AT91_PMC_AUDIO_PLL_ND_MASK >> \ 48 AT91_PMC_AUDIO_PLL_ND_OFFSET) 49 50 #define AUDIO_PLL_QDPAD(qd, div) ((AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV(qd) & \ 51 AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MASK) | \ 52 (AT91_PMC_AUDIO_PLL_QDPAD_DIV(div) & \ 53 AT91_PMC_AUDIO_PLL_QDPAD_DIV_MASK)) 54 55 #define AUDIO_PLL_QDPMC_MAX (AT91_PMC_AUDIO_PLL_QDPMC_MASK >> \ 56 AT91_PMC_AUDIO_PLL_QDPMC_OFFSET) 57 58 #define AUDIO_PLL_FOUT_MIN 620000000UL 59 #define AUDIO_PLL_FOUT_MAX 700000000UL 60 61 struct clk_audio_frac { 62 struct clk_hw hw; 63 struct regmap *regmap; 64 u32 fracr; 65 u8 nd; 66 }; 67 68 struct clk_audio_pad { 69 struct clk_hw hw; 70 struct regmap *regmap; 71 u8 qdaudio; 72 u8 div; 73 }; 74 75 struct clk_audio_pmc { 76 struct clk_hw hw; 77 struct regmap *regmap; 78 u8 qdpmc; 79 }; 80 81 #define to_clk_audio_frac(hw) container_of(hw, struct clk_audio_frac, hw) 82 #define to_clk_audio_pad(hw) container_of(hw, struct clk_audio_pad, hw) 83 #define to_clk_audio_pmc(hw) container_of(hw, struct clk_audio_pmc, hw) 84 85 static int clk_audio_pll_frac_enable(struct clk_hw *hw) 86 { 87 struct clk_audio_frac *frac = to_clk_audio_frac(hw); 88 89 regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0, 90 AT91_PMC_AUDIO_PLL_RESETN, 0); 91 regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0, 92 AT91_PMC_AUDIO_PLL_RESETN, 93 AT91_PMC_AUDIO_PLL_RESETN); 94 regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL1, 95 AT91_PMC_AUDIO_PLL_FRACR_MASK, frac->fracr); 96 97 /* 98 * reset and enable have to be done in 2 separated writes 99 * for AT91_PMC_AUDIO_PLL0 100 */ 101 regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0, 102 AT91_PMC_AUDIO_PLL_PLLEN | 103 AT91_PMC_AUDIO_PLL_ND_MASK, 104 AT91_PMC_AUDIO_PLL_PLLEN | 105 AT91_PMC_AUDIO_PLL_ND(frac->nd)); 106 107 return 0; 108 } 109 110 static int clk_audio_pll_pad_enable(struct clk_hw *hw) 111 { 112 struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw); 113 114 regmap_update_bits(apad_ck->regmap, AT91_PMC_AUDIO_PLL1, 115 AT91_PMC_AUDIO_PLL_QDPAD_MASK, 116 AUDIO_PLL_QDPAD(apad_ck->qdaudio, apad_ck->div)); 117 regmap_update_bits(apad_ck->regmap, AT91_PMC_AUDIO_PLL0, 118 AT91_PMC_AUDIO_PLL_PADEN, AT91_PMC_AUDIO_PLL_PADEN); 119 120 return 0; 121 } 122 123 static int clk_audio_pll_pmc_enable(struct clk_hw *hw) 124 { 125 struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw); 126 127 regmap_update_bits(apmc_ck->regmap, AT91_PMC_AUDIO_PLL0, 128 AT91_PMC_AUDIO_PLL_PMCEN | 129 AT91_PMC_AUDIO_PLL_QDPMC_MASK, 130 AT91_PMC_AUDIO_PLL_PMCEN | 131 AT91_PMC_AUDIO_PLL_QDPMC(apmc_ck->qdpmc)); 132 return 0; 133 } 134 135 static void clk_audio_pll_frac_disable(struct clk_hw *hw) 136 { 137 struct clk_audio_frac *frac = to_clk_audio_frac(hw); 138 139 regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0, 140 AT91_PMC_AUDIO_PLL_PLLEN, 0); 141 /* do it in 2 separated writes */ 142 regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0, 143 AT91_PMC_AUDIO_PLL_RESETN, 0); 144 } 145 146 static void clk_audio_pll_pad_disable(struct clk_hw *hw) 147 { 148 struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw); 149 150 regmap_update_bits(apad_ck->regmap, AT91_PMC_AUDIO_PLL0, 151 AT91_PMC_AUDIO_PLL_PADEN, 0); 152 } 153 154 static void clk_audio_pll_pmc_disable(struct clk_hw *hw) 155 { 156 struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw); 157 158 regmap_update_bits(apmc_ck->regmap, AT91_PMC_AUDIO_PLL0, 159 AT91_PMC_AUDIO_PLL_PMCEN, 0); 160 } 161 162 static unsigned long clk_audio_pll_fout(unsigned long parent_rate, 163 unsigned long nd, unsigned long fracr) 164 { 165 unsigned long long fr = (unsigned long long)parent_rate * fracr; 166 167 pr_debug("A PLL: %s, fr = %llu\n", __func__, fr); 168 169 fr = DIV_ROUND_CLOSEST_ULL(fr, AUDIO_PLL_DIV_FRAC); 170 171 pr_debug("A PLL: %s, fr = %llu\n", __func__, fr); 172 173 return parent_rate * (nd + 1) + fr; 174 } 175 176 static unsigned long clk_audio_pll_frac_recalc_rate(struct clk_hw *hw, 177 unsigned long parent_rate) 178 { 179 struct clk_audio_frac *frac = to_clk_audio_frac(hw); 180 unsigned long fout; 181 182 fout = clk_audio_pll_fout(parent_rate, frac->nd, frac->fracr); 183 184 pr_debug("A PLL: %s, fout = %lu (nd = %u, fracr = %lu)\n", __func__, 185 fout, frac->nd, (unsigned long)frac->fracr); 186 187 return fout; 188 } 189 190 static unsigned long clk_audio_pll_pad_recalc_rate(struct clk_hw *hw, 191 unsigned long parent_rate) 192 { 193 struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw); 194 unsigned long apad_rate = 0; 195 196 if (apad_ck->qdaudio && apad_ck->div) 197 apad_rate = parent_rate / (apad_ck->qdaudio * apad_ck->div); 198 199 pr_debug("A PLL/PAD: %s, apad_rate = %lu (div = %u, qdaudio = %u)\n", 200 __func__, apad_rate, apad_ck->div, apad_ck->qdaudio); 201 202 return apad_rate; 203 } 204 205 static unsigned long clk_audio_pll_pmc_recalc_rate(struct clk_hw *hw, 206 unsigned long parent_rate) 207 { 208 struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw); 209 unsigned long apmc_rate = 0; 210 211 apmc_rate = parent_rate / (apmc_ck->qdpmc + 1); 212 213 pr_debug("A PLL/PMC: %s, apmc_rate = %lu (qdpmc = %u)\n", __func__, 214 apmc_rate, apmc_ck->qdpmc); 215 216 return apmc_rate; 217 } 218 219 static int clk_audio_pll_frac_compute_frac(unsigned long rate, 220 unsigned long parent_rate, 221 unsigned long *nd, 222 unsigned long *fracr) 223 { 224 unsigned long long tmp, rem; 225 226 if (!rate) 227 return -EINVAL; 228 229 tmp = rate; 230 rem = do_div(tmp, parent_rate); 231 if (!tmp || tmp >= AUDIO_PLL_ND_MAX) 232 return -EINVAL; 233 234 *nd = tmp - 1; 235 236 tmp = rem * AUDIO_PLL_DIV_FRAC; 237 tmp = DIV_ROUND_CLOSEST_ULL(tmp, parent_rate); 238 if (tmp > AT91_PMC_AUDIO_PLL_FRACR_MASK) 239 return -EINVAL; 240 241 /* we can cast here as we verified the bounds just above */ 242 *fracr = (unsigned long)tmp; 243 244 return 0; 245 } 246 247 static int clk_audio_pll_frac_determine_rate(struct clk_hw *hw, 248 struct clk_rate_request *req) 249 { 250 unsigned long fracr, nd; 251 int ret; 252 253 pr_debug("A PLL: %s, rate = %lu (parent_rate = %lu)\n", __func__, 254 req->rate, req->best_parent_rate); 255 256 req->rate = clamp(req->rate, AUDIO_PLL_FOUT_MIN, AUDIO_PLL_FOUT_MAX); 257 258 req->min_rate = max(req->min_rate, AUDIO_PLL_FOUT_MIN); 259 req->max_rate = min(req->max_rate, AUDIO_PLL_FOUT_MAX); 260 261 ret = clk_audio_pll_frac_compute_frac(req->rate, req->best_parent_rate, 262 &nd, &fracr); 263 if (ret) 264 return ret; 265 266 req->rate = clk_audio_pll_fout(req->best_parent_rate, nd, fracr); 267 268 req->best_parent_hw = clk_hw_get_parent(hw); 269 270 pr_debug("A PLL: %s, best_rate = %lu (nd = %lu, fracr = %lu)\n", 271 __func__, req->rate, nd, fracr); 272 273 return 0; 274 } 275 276 static long clk_audio_pll_pad_round_rate(struct clk_hw *hw, unsigned long rate, 277 unsigned long *parent_rate) 278 { 279 struct clk_hw *pclk = clk_hw_get_parent(hw); 280 long best_rate = -EINVAL; 281 unsigned long best_parent_rate; 282 unsigned long tmp_qd; 283 u32 div; 284 long tmp_rate; 285 int tmp_diff; 286 int best_diff = -1; 287 288 pr_debug("A PLL/PAD: %s, rate = %lu (parent_rate = %lu)\n", __func__, 289 rate, *parent_rate); 290 291 /* 292 * Rate divisor is actually made of two different divisors, multiplied 293 * between themselves before dividing the rate. 294 * tmp_qd goes from 1 to 31 and div is either 2 or 3. 295 * In order to avoid testing twice the rate divisor (e.g. divisor 12 can 296 * be found with (tmp_qd, div) = (2, 6) or (3, 4)), we remove any loop 297 * for a rate divisor when div is 2 and tmp_qd is a multiple of 3. 298 * We cannot inverse it (condition div is 3 and tmp_qd is even) or we 299 * would miss some rate divisor that aren't reachable with div being 2 300 * (e.g. rate divisor 90 is made with div = 3 and tmp_qd = 30, thus 301 * tmp_qd is even so we skip it because we think div 2 could make this 302 * rate divisor which isn't possible since tmp_qd has to be <= 31). 303 */ 304 for (tmp_qd = 1; tmp_qd < AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX; tmp_qd++) 305 for (div = 2; div <= 3; div++) { 306 if (div == 2 && tmp_qd % 3 == 0) 307 continue; 308 309 best_parent_rate = clk_hw_round_rate(pclk, 310 rate * tmp_qd * div); 311 tmp_rate = best_parent_rate / (div * tmp_qd); 312 tmp_diff = abs(rate - tmp_rate); 313 314 if (best_diff < 0 || best_diff > tmp_diff) { 315 *parent_rate = best_parent_rate; 316 best_rate = tmp_rate; 317 best_diff = tmp_diff; 318 } 319 } 320 321 pr_debug("A PLL/PAD: %s, best_rate = %ld, best_parent_rate = %lu\n", 322 __func__, best_rate, best_parent_rate); 323 324 return best_rate; 325 } 326 327 static long clk_audio_pll_pmc_round_rate(struct clk_hw *hw, unsigned long rate, 328 unsigned long *parent_rate) 329 { 330 struct clk_hw *pclk = clk_hw_get_parent(hw); 331 long best_rate = -EINVAL; 332 unsigned long best_parent_rate = 0; 333 u32 tmp_qd = 0, div; 334 long tmp_rate; 335 int tmp_diff; 336 int best_diff = -1; 337 338 pr_debug("A PLL/PMC: %s, rate = %lu (parent_rate = %lu)\n", __func__, 339 rate, *parent_rate); 340 341 for (div = 1; div <= AUDIO_PLL_QDPMC_MAX; div++) { 342 best_parent_rate = clk_round_rate(pclk->clk, rate * div); 343 tmp_rate = best_parent_rate / div; 344 tmp_diff = abs(rate - tmp_rate); 345 346 if (best_diff < 0 || best_diff > tmp_diff) { 347 *parent_rate = best_parent_rate; 348 best_rate = tmp_rate; 349 best_diff = tmp_diff; 350 tmp_qd = div; 351 } 352 } 353 354 pr_debug("A PLL/PMC: %s, best_rate = %ld, best_parent_rate = %lu (qd = %d)\n", 355 __func__, best_rate, *parent_rate, tmp_qd - 1); 356 357 return best_rate; 358 } 359 360 static int clk_audio_pll_frac_set_rate(struct clk_hw *hw, unsigned long rate, 361 unsigned long parent_rate) 362 { 363 struct clk_audio_frac *frac = to_clk_audio_frac(hw); 364 unsigned long fracr, nd; 365 int ret; 366 367 pr_debug("A PLL: %s, rate = %lu (parent_rate = %lu)\n", __func__, rate, 368 parent_rate); 369 370 if (rate < AUDIO_PLL_FOUT_MIN || rate > AUDIO_PLL_FOUT_MAX) 371 return -EINVAL; 372 373 ret = clk_audio_pll_frac_compute_frac(rate, parent_rate, &nd, &fracr); 374 if (ret) 375 return ret; 376 377 frac->nd = nd; 378 frac->fracr = fracr; 379 380 return 0; 381 } 382 383 static int clk_audio_pll_pad_set_rate(struct clk_hw *hw, unsigned long rate, 384 unsigned long parent_rate) 385 { 386 struct clk_audio_pad *apad_ck = to_clk_audio_pad(hw); 387 u8 tmp_div; 388 389 pr_debug("A PLL/PAD: %s, rate = %lu (parent_rate = %lu)\n", __func__, 390 rate, parent_rate); 391 392 if (!rate) 393 return -EINVAL; 394 395 tmp_div = parent_rate / rate; 396 if (tmp_div % 3 == 0) { 397 apad_ck->qdaudio = tmp_div / 3; 398 apad_ck->div = 3; 399 } else { 400 apad_ck->qdaudio = tmp_div / 2; 401 apad_ck->div = 2; 402 } 403 404 return 0; 405 } 406 407 static int clk_audio_pll_pmc_set_rate(struct clk_hw *hw, unsigned long rate, 408 unsigned long parent_rate) 409 { 410 struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(hw); 411 412 if (!rate) 413 return -EINVAL; 414 415 pr_debug("A PLL/PMC: %s, rate = %lu (parent_rate = %lu)\n", __func__, 416 rate, parent_rate); 417 418 apmc_ck->qdpmc = parent_rate / rate - 1; 419 420 return 0; 421 } 422 423 static const struct clk_ops audio_pll_frac_ops = { 424 .enable = clk_audio_pll_frac_enable, 425 .disable = clk_audio_pll_frac_disable, 426 .recalc_rate = clk_audio_pll_frac_recalc_rate, 427 .determine_rate = clk_audio_pll_frac_determine_rate, 428 .set_rate = clk_audio_pll_frac_set_rate, 429 }; 430 431 static const struct clk_ops audio_pll_pad_ops = { 432 .enable = clk_audio_pll_pad_enable, 433 .disable = clk_audio_pll_pad_disable, 434 .recalc_rate = clk_audio_pll_pad_recalc_rate, 435 .round_rate = clk_audio_pll_pad_round_rate, 436 .set_rate = clk_audio_pll_pad_set_rate, 437 }; 438 439 static const struct clk_ops audio_pll_pmc_ops = { 440 .enable = clk_audio_pll_pmc_enable, 441 .disable = clk_audio_pll_pmc_disable, 442 .recalc_rate = clk_audio_pll_pmc_recalc_rate, 443 .round_rate = clk_audio_pll_pmc_round_rate, 444 .set_rate = clk_audio_pll_pmc_set_rate, 445 }; 446 447 static int of_sama5d2_clk_audio_pll_setup(struct device_node *np, 448 struct clk_init_data *init, 449 struct clk_hw *hw, 450 struct regmap **clk_audio_regmap) 451 { 452 struct regmap *regmap; 453 const char *parent_names[1]; 454 int ret; 455 456 regmap = syscon_node_to_regmap(of_get_parent(np)); 457 if (IS_ERR(regmap)) 458 return PTR_ERR(regmap); 459 460 init->name = np->name; 461 of_clk_parent_fill(np, parent_names, 1); 462 init->parent_names = parent_names; 463 init->num_parents = 1; 464 465 hw->init = init; 466 *clk_audio_regmap = regmap; 467 468 ret = clk_hw_register(NULL, hw); 469 if (ret) 470 return ret; 471 472 return of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); 473 } 474 475 static void __init of_sama5d2_clk_audio_pll_frac_setup(struct device_node *np) 476 { 477 struct clk_audio_frac *frac_ck; 478 struct clk_init_data init = {}; 479 480 frac_ck = kzalloc(sizeof(*frac_ck), GFP_KERNEL); 481 if (!frac_ck) 482 return; 483 484 init.ops = &audio_pll_frac_ops; 485 init.flags = CLK_SET_RATE_GATE; 486 487 if (of_sama5d2_clk_audio_pll_setup(np, &init, &frac_ck->hw, 488 &frac_ck->regmap)) 489 kfree(frac_ck); 490 } 491 492 static void __init of_sama5d2_clk_audio_pll_pad_setup(struct device_node *np) 493 { 494 struct clk_audio_pad *apad_ck; 495 struct clk_init_data init = {}; 496 497 apad_ck = kzalloc(sizeof(*apad_ck), GFP_KERNEL); 498 if (!apad_ck) 499 return; 500 501 init.ops = &audio_pll_pad_ops; 502 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | 503 CLK_SET_RATE_PARENT; 504 505 if (of_sama5d2_clk_audio_pll_setup(np, &init, &apad_ck->hw, 506 &apad_ck->regmap)) 507 kfree(apad_ck); 508 } 509 510 static void __init of_sama5d2_clk_audio_pll_pmc_setup(struct device_node *np) 511 { 512 struct clk_audio_pad *apmc_ck; 513 struct clk_init_data init = {}; 514 515 apmc_ck = kzalloc(sizeof(*apmc_ck), GFP_KERNEL); 516 if (!apmc_ck) 517 return; 518 519 init.ops = &audio_pll_pmc_ops; 520 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | 521 CLK_SET_RATE_PARENT; 522 523 if (of_sama5d2_clk_audio_pll_setup(np, &init, &apmc_ck->hw, 524 &apmc_ck->regmap)) 525 kfree(apmc_ck); 526 } 527 528 CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_frac_setup, 529 "atmel,sama5d2-clk-audio-pll-frac", 530 of_sama5d2_clk_audio_pll_frac_setup); 531 CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_pad_setup, 532 "atmel,sama5d2-clk-audio-pll-pad", 533 of_sama5d2_clk_audio_pll_pad_setup); 534 CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_pmc_setup, 535 "atmel,sama5d2-clk-audio-pll-pmc", 536 of_sama5d2_clk_audio_pll_pmc_setup); 537