xref: /openbmc/linux/drivers/clk/at91/at91sam9rl.c (revision f5ad1c74)
1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
3 #include <linux/mfd/syscon.h>
4 #include <linux/slab.h>
5 
6 #include <dt-bindings/clock/at91.h>
7 
8 #include "pmc.h"
9 
10 static const struct clk_master_characteristics sam9rl_mck_characteristics = {
11 	.output = { .min = 0, .max = 94000000 },
12 	.divisors = { 1, 2, 4, 0 },
13 };
14 
15 static u8 sam9rl_plla_out[] = { 0, 2 };
16 
17 static const struct clk_range sam9rl_plla_outputs[] = {
18 	{ .min = 80000000, .max = 200000000 },
19 	{ .min = 190000000, .max = 240000000 },
20 };
21 
22 static const struct clk_pll_characteristics sam9rl_plla_characteristics = {
23 	.input = { .min = 1000000, .max = 32000000 },
24 	.num_output = ARRAY_SIZE(sam9rl_plla_outputs),
25 	.output = sam9rl_plla_outputs,
26 	.out = sam9rl_plla_out,
27 };
28 
29 static const struct {
30 	char *n;
31 	char *p;
32 	u8 id;
33 } at91sam9rl_systemck[] = {
34 	{ .n = "pck0",  .p = "prog0",    .id = 8 },
35 	{ .n = "pck1",  .p = "prog1",    .id = 9 },
36 };
37 
38 static const struct {
39 	char *n;
40 	u8 id;
41 } at91sam9rl_periphck[] = {
42 	{ .n = "pioA_clk",   .id = 2, },
43 	{ .n = "pioB_clk",   .id = 3, },
44 	{ .n = "pioC_clk",   .id = 4, },
45 	{ .n = "pioD_clk",   .id = 5, },
46 	{ .n = "usart0_clk", .id = 6, },
47 	{ .n = "usart1_clk", .id = 7, },
48 	{ .n = "usart2_clk", .id = 8, },
49 	{ .n = "usart3_clk", .id = 9, },
50 	{ .n = "mci0_clk",   .id = 10, },
51 	{ .n = "twi0_clk",   .id = 11, },
52 	{ .n = "twi1_clk",   .id = 12, },
53 	{ .n = "spi0_clk",   .id = 13, },
54 	{ .n = "ssc0_clk",   .id = 14, },
55 	{ .n = "ssc1_clk",   .id = 15, },
56 	{ .n = "tc0_clk",    .id = 16, },
57 	{ .n = "tc1_clk",    .id = 17, },
58 	{ .n = "tc2_clk",    .id = 18, },
59 	{ .n = "pwm_clk",    .id = 19, },
60 	{ .n = "adc_clk",    .id = 20, },
61 	{ .n = "dma0_clk",   .id = 21, },
62 	{ .n = "udphs_clk",  .id = 22, },
63 	{ .n = "lcd_clk",    .id = 23, },
64 };
65 
66 static void __init at91sam9rl_pmc_setup(struct device_node *np)
67 {
68 	const char *slck_name, *mainxtal_name;
69 	struct pmc_data *at91sam9rl_pmc;
70 	const char *parent_names[6];
71 	struct regmap *regmap;
72 	struct clk_hw *hw;
73 	int i;
74 
75 	i = of_property_match_string(np, "clock-names", "slow_clk");
76 	if (i < 0)
77 		return;
78 
79 	slck_name = of_clk_get_parent_name(np, i);
80 
81 	i = of_property_match_string(np, "clock-names", "main_xtal");
82 	if (i < 0)
83 		return;
84 	mainxtal_name = of_clk_get_parent_name(np, i);
85 
86 	regmap = device_node_to_regmap(np);
87 	if (IS_ERR(regmap))
88 		return;
89 
90 	at91sam9rl_pmc = pmc_data_allocate(PMC_PLLACK + 1,
91 					   nck(at91sam9rl_systemck),
92 					   nck(at91sam9rl_periphck), 0, 2);
93 	if (!at91sam9rl_pmc)
94 		return;
95 
96 	hw = at91_clk_register_rm9200_main(regmap, "mainck", mainxtal_name);
97 	if (IS_ERR(hw))
98 		goto err_free;
99 
100 	at91sam9rl_pmc->chws[PMC_MAIN] = hw;
101 
102 	hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
103 				   &at91rm9200_pll_layout,
104 				   &sam9rl_plla_characteristics);
105 	if (IS_ERR(hw))
106 		goto err_free;
107 
108 	at91sam9rl_pmc->chws[PMC_PLLACK] = hw;
109 
110 	hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck");
111 	if (IS_ERR(hw))
112 		goto err_free;
113 
114 	at91sam9rl_pmc->chws[PMC_UTMI] = hw;
115 
116 	parent_names[0] = slck_name;
117 	parent_names[1] = "mainck";
118 	parent_names[2] = "pllack";
119 	parent_names[3] = "utmick";
120 	hw = at91_clk_register_master(regmap, "masterck", 4, parent_names,
121 				      &at91rm9200_master_layout,
122 				      &sam9rl_mck_characteristics);
123 	if (IS_ERR(hw))
124 		goto err_free;
125 
126 	at91sam9rl_pmc->chws[PMC_MCK] = hw;
127 
128 	parent_names[0] = slck_name;
129 	parent_names[1] = "mainck";
130 	parent_names[2] = "pllack";
131 	parent_names[3] = "utmick";
132 	parent_names[4] = "masterck";
133 	for (i = 0; i < 2; i++) {
134 		char name[6];
135 
136 		snprintf(name, sizeof(name), "prog%d", i);
137 
138 		hw = at91_clk_register_programmable(regmap, name,
139 						    parent_names, 5, i,
140 						    &at91rm9200_programmable_layout,
141 						    NULL);
142 		if (IS_ERR(hw))
143 			goto err_free;
144 
145 		at91sam9rl_pmc->pchws[i] = hw;
146 	}
147 
148 	for (i = 0; i < ARRAY_SIZE(at91sam9rl_systemck); i++) {
149 		hw = at91_clk_register_system(regmap, at91sam9rl_systemck[i].n,
150 					      at91sam9rl_systemck[i].p,
151 					      at91sam9rl_systemck[i].id);
152 		if (IS_ERR(hw))
153 			goto err_free;
154 
155 		at91sam9rl_pmc->shws[at91sam9rl_systemck[i].id] = hw;
156 	}
157 
158 	for (i = 0; i < ARRAY_SIZE(at91sam9rl_periphck); i++) {
159 		hw = at91_clk_register_peripheral(regmap,
160 						  at91sam9rl_periphck[i].n,
161 						  "masterck",
162 						  at91sam9rl_periphck[i].id);
163 		if (IS_ERR(hw))
164 			goto err_free;
165 
166 		at91sam9rl_pmc->phws[at91sam9rl_periphck[i].id] = hw;
167 	}
168 
169 	of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9rl_pmc);
170 
171 	return;
172 
173 err_free:
174 	kfree(at91sam9rl_pmc);
175 }
176 CLK_OF_DECLARE_DRIVER(at91sam9rl_pmc, "atmel,at91sam9rl-pmc", at91sam9rl_pmc_setup);
177