1 // SPDX-License-Identifier: GPL-2.0 2 #include <linux/clk-provider.h> 3 #include <linux/mfd/syscon.h> 4 #include <linux/slab.h> 5 6 #include <dt-bindings/clock/at91.h> 7 8 #include "pmc.h" 9 10 static DEFINE_SPINLOCK(sam9rl_mck_lock); 11 12 static const struct clk_master_characteristics sam9rl_mck_characteristics = { 13 .output = { .min = 0, .max = 94000000 }, 14 .divisors = { 1, 2, 4, 0 }, 15 }; 16 17 static u8 sam9rl_plla_out[] = { 0, 2 }; 18 19 static const struct clk_range sam9rl_plla_outputs[] = { 20 { .min = 80000000, .max = 200000000 }, 21 { .min = 190000000, .max = 240000000 }, 22 }; 23 24 static const struct clk_pll_characteristics sam9rl_plla_characteristics = { 25 .input = { .min = 1000000, .max = 32000000 }, 26 .num_output = ARRAY_SIZE(sam9rl_plla_outputs), 27 .output = sam9rl_plla_outputs, 28 .out = sam9rl_plla_out, 29 }; 30 31 static const struct { 32 char *n; 33 char *p; 34 u8 id; 35 } at91sam9rl_systemck[] = { 36 { .n = "pck0", .p = "prog0", .id = 8 }, 37 { .n = "pck1", .p = "prog1", .id = 9 }, 38 }; 39 40 static const struct { 41 char *n; 42 u8 id; 43 } at91sam9rl_periphck[] = { 44 { .n = "pioA_clk", .id = 2, }, 45 { .n = "pioB_clk", .id = 3, }, 46 { .n = "pioC_clk", .id = 4, }, 47 { .n = "pioD_clk", .id = 5, }, 48 { .n = "usart0_clk", .id = 6, }, 49 { .n = "usart1_clk", .id = 7, }, 50 { .n = "usart2_clk", .id = 8, }, 51 { .n = "usart3_clk", .id = 9, }, 52 { .n = "mci0_clk", .id = 10, }, 53 { .n = "twi0_clk", .id = 11, }, 54 { .n = "twi1_clk", .id = 12, }, 55 { .n = "spi0_clk", .id = 13, }, 56 { .n = "ssc0_clk", .id = 14, }, 57 { .n = "ssc1_clk", .id = 15, }, 58 { .n = "tc0_clk", .id = 16, }, 59 { .n = "tc1_clk", .id = 17, }, 60 { .n = "tc2_clk", .id = 18, }, 61 { .n = "pwm_clk", .id = 19, }, 62 { .n = "adc_clk", .id = 20, }, 63 { .n = "dma0_clk", .id = 21, }, 64 { .n = "udphs_clk", .id = 22, }, 65 { .n = "lcd_clk", .id = 23, }, 66 }; 67 68 static void __init at91sam9rl_pmc_setup(struct device_node *np) 69 { 70 const char *slck_name, *mainxtal_name; 71 struct pmc_data *at91sam9rl_pmc; 72 const char *parent_names[6]; 73 struct regmap *regmap; 74 struct clk_hw *hw; 75 int i; 76 77 i = of_property_match_string(np, "clock-names", "slow_clk"); 78 if (i < 0) 79 return; 80 81 slck_name = of_clk_get_parent_name(np, i); 82 83 i = of_property_match_string(np, "clock-names", "main_xtal"); 84 if (i < 0) 85 return; 86 mainxtal_name = of_clk_get_parent_name(np, i); 87 88 regmap = device_node_to_regmap(np); 89 if (IS_ERR(regmap)) 90 return; 91 92 at91sam9rl_pmc = pmc_data_allocate(PMC_PLLACK + 1, 93 nck(at91sam9rl_systemck), 94 nck(at91sam9rl_periphck), 0, 2); 95 if (!at91sam9rl_pmc) 96 return; 97 98 hw = at91_clk_register_rm9200_main(regmap, "mainck", mainxtal_name, NULL); 99 if (IS_ERR(hw)) 100 goto err_free; 101 102 at91sam9rl_pmc->chws[PMC_MAIN] = hw; 103 104 hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0, 105 &at91rm9200_pll_layout, 106 &sam9rl_plla_characteristics); 107 if (IS_ERR(hw)) 108 goto err_free; 109 110 at91sam9rl_pmc->chws[PMC_PLLACK] = hw; 111 112 hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck", NULL); 113 if (IS_ERR(hw)) 114 goto err_free; 115 116 at91sam9rl_pmc->chws[PMC_UTMI] = hw; 117 118 parent_names[0] = slck_name; 119 parent_names[1] = "mainck"; 120 parent_names[2] = "pllack"; 121 parent_names[3] = "utmick"; 122 hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, 123 parent_names, NULL, 124 &at91rm9200_master_layout, 125 &sam9rl_mck_characteristics, 126 &sam9rl_mck_lock); 127 if (IS_ERR(hw)) 128 goto err_free; 129 130 hw = at91_clk_register_master_div(regmap, "masterck_div", 131 "masterck_pres", NULL, 132 &at91rm9200_master_layout, 133 &sam9rl_mck_characteristics, 134 &sam9rl_mck_lock, CLK_SET_RATE_GATE, 0); 135 if (IS_ERR(hw)) 136 goto err_free; 137 138 at91sam9rl_pmc->chws[PMC_MCK] = hw; 139 140 parent_names[0] = slck_name; 141 parent_names[1] = "mainck"; 142 parent_names[2] = "pllack"; 143 parent_names[3] = "utmick"; 144 parent_names[4] = "masterck_div"; 145 for (i = 0; i < 2; i++) { 146 char name[6]; 147 148 snprintf(name, sizeof(name), "prog%d", i); 149 150 hw = at91_clk_register_programmable(regmap, name, 151 parent_names, NULL, 5, i, 152 &at91rm9200_programmable_layout, 153 NULL); 154 if (IS_ERR(hw)) 155 goto err_free; 156 157 at91sam9rl_pmc->pchws[i] = hw; 158 } 159 160 for (i = 0; i < ARRAY_SIZE(at91sam9rl_systemck); i++) { 161 hw = at91_clk_register_system(regmap, at91sam9rl_systemck[i].n, 162 at91sam9rl_systemck[i].p, NULL, 163 at91sam9rl_systemck[i].id, 0); 164 if (IS_ERR(hw)) 165 goto err_free; 166 167 at91sam9rl_pmc->shws[at91sam9rl_systemck[i].id] = hw; 168 } 169 170 for (i = 0; i < ARRAY_SIZE(at91sam9rl_periphck); i++) { 171 hw = at91_clk_register_peripheral(regmap, 172 at91sam9rl_periphck[i].n, 173 "masterck_div", NULL, 174 at91sam9rl_periphck[i].id); 175 if (IS_ERR(hw)) 176 goto err_free; 177 178 at91sam9rl_pmc->phws[at91sam9rl_periphck[i].id] = hw; 179 } 180 181 of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9rl_pmc); 182 183 return; 184 185 err_free: 186 kfree(at91sam9rl_pmc); 187 } 188 189 CLK_OF_DECLARE(at91sam9rl_pmc, "atmel,at91sam9rl-pmc", at91sam9rl_pmc_setup); 190