1 // SPDX-License-Identifier: GPL-2.0 2 #include <linux/clk-provider.h> 3 #include <linux/mfd/syscon.h> 4 #include <linux/slab.h> 5 6 #include <dt-bindings/clock/at91.h> 7 8 #include "pmc.h" 9 10 static DEFINE_SPINLOCK(at91sam9n12_mck_lock); 11 12 static const struct clk_master_characteristics mck_characteristics = { 13 .output = { .min = 0, .max = 133333333 }, 14 .divisors = { 1, 2, 4, 3 }, 15 .have_div3_pres = 1, 16 }; 17 18 static u8 plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 }; 19 20 static u16 plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 }; 21 22 static const struct clk_range plla_outputs[] = { 23 { .min = 745000000, .max = 800000000 }, 24 { .min = 695000000, .max = 750000000 }, 25 { .min = 645000000, .max = 700000000 }, 26 { .min = 595000000, .max = 650000000 }, 27 { .min = 545000000, .max = 600000000 }, 28 { .min = 495000000, .max = 555000000 }, 29 { .min = 445000000, .max = 500000000 }, 30 { .min = 400000000, .max = 450000000 }, 31 }; 32 33 static const struct clk_pll_characteristics plla_characteristics = { 34 .input = { .min = 2000000, .max = 32000000 }, 35 .num_output = ARRAY_SIZE(plla_outputs), 36 .output = plla_outputs, 37 .icpll = plla_icpll, 38 .out = plla_out, 39 }; 40 41 static u8 pllb_out[] = { 0 }; 42 43 static const struct clk_range pllb_outputs[] = { 44 { .min = 30000000, .max = 100000000 }, 45 }; 46 47 static const struct clk_pll_characteristics pllb_characteristics = { 48 .input = { .min = 2000000, .max = 32000000 }, 49 .num_output = ARRAY_SIZE(pllb_outputs), 50 .output = pllb_outputs, 51 .out = pllb_out, 52 }; 53 54 static const struct { 55 char *n; 56 char *p; 57 unsigned long flags; 58 u8 id; 59 } at91sam9n12_systemck[] = { 60 /* 61 * ddrck feeds DDR controller and is enabled by bootloader thus we need 62 * to keep it enabled in case there is no Linux consumer for it. 63 */ 64 { .n = "ddrck", .p = "masterck_div", .id = 2, .flags = CLK_IS_CRITICAL }, 65 { .n = "lcdck", .p = "masterck_div", .id = 3 }, 66 { .n = "uhpck", .p = "usbck", .id = 6 }, 67 { .n = "udpck", .p = "usbck", .id = 7 }, 68 { .n = "pck0", .p = "prog0", .id = 8 }, 69 { .n = "pck1", .p = "prog1", .id = 9 }, 70 }; 71 72 static const struct clk_pcr_layout at91sam9n12_pcr_layout = { 73 .offset = 0x10c, 74 .cmd = BIT(12), 75 .pid_mask = GENMASK(5, 0), 76 .div_mask = GENMASK(17, 16), 77 }; 78 79 struct pck { 80 char *n; 81 u8 id; 82 }; 83 84 static const struct pck at91sam9n12_periphck[] = { 85 { .n = "pioAB_clk", .id = 2, }, 86 { .n = "pioCD_clk", .id = 3, }, 87 { .n = "fuse_clk", .id = 4, }, 88 { .n = "usart0_clk", .id = 5, }, 89 { .n = "usart1_clk", .id = 6, }, 90 { .n = "usart2_clk", .id = 7, }, 91 { .n = "usart3_clk", .id = 8, }, 92 { .n = "twi0_clk", .id = 9, }, 93 { .n = "twi1_clk", .id = 10, }, 94 { .n = "mci0_clk", .id = 12, }, 95 { .n = "spi0_clk", .id = 13, }, 96 { .n = "spi1_clk", .id = 14, }, 97 { .n = "uart0_clk", .id = 15, }, 98 { .n = "uart1_clk", .id = 16, }, 99 { .n = "tcb_clk", .id = 17, }, 100 { .n = "pwm_clk", .id = 18, }, 101 { .n = "adc_clk", .id = 19, }, 102 { .n = "dma0_clk", .id = 20, }, 103 { .n = "uhphs_clk", .id = 22, }, 104 { .n = "udphs_clk", .id = 23, }, 105 { .n = "lcdc_clk", .id = 25, }, 106 { .n = "sha_clk", .id = 27, }, 107 { .n = "ssc0_clk", .id = 28, }, 108 { .n = "aes_clk", .id = 29, }, 109 { .n = "trng_clk", .id = 30, }, 110 }; 111 112 static void __init at91sam9n12_pmc_setup(struct device_node *np) 113 { 114 struct clk_range range = CLK_RANGE(0, 0); 115 const char *slck_name, *mainxtal_name; 116 struct pmc_data *at91sam9n12_pmc; 117 const char *parent_names[6]; 118 struct regmap *regmap; 119 struct clk_hw *hw; 120 int i; 121 bool bypass; 122 123 i = of_property_match_string(np, "clock-names", "slow_clk"); 124 if (i < 0) 125 return; 126 127 slck_name = of_clk_get_parent_name(np, i); 128 129 i = of_property_match_string(np, "clock-names", "main_xtal"); 130 if (i < 0) 131 return; 132 mainxtal_name = of_clk_get_parent_name(np, i); 133 134 regmap = device_node_to_regmap(np); 135 if (IS_ERR(regmap)) 136 return; 137 138 at91sam9n12_pmc = pmc_data_allocate(PMC_PLLBCK + 1, 139 nck(at91sam9n12_systemck), 31, 0, 2); 140 if (!at91sam9n12_pmc) 141 return; 142 143 hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, 144 50000000); 145 if (IS_ERR(hw)) 146 goto err_free; 147 148 bypass = of_property_read_bool(np, "atmel,osc-bypass"); 149 150 hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL, 151 bypass); 152 if (IS_ERR(hw)) 153 goto err_free; 154 155 parent_names[0] = "main_rc_osc"; 156 parent_names[1] = "main_osc"; 157 hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL, 2); 158 if (IS_ERR(hw)) 159 goto err_free; 160 161 at91sam9n12_pmc->chws[PMC_MAIN] = hw; 162 163 hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0, 164 &at91rm9200_pll_layout, &plla_characteristics); 165 if (IS_ERR(hw)) 166 goto err_free; 167 168 hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack"); 169 if (IS_ERR(hw)) 170 goto err_free; 171 172 at91sam9n12_pmc->chws[PMC_PLLACK] = hw; 173 174 hw = at91_clk_register_pll(regmap, "pllbck", "mainck", 1, 175 &at91rm9200_pll_layout, &pllb_characteristics); 176 if (IS_ERR(hw)) 177 goto err_free; 178 179 at91sam9n12_pmc->chws[PMC_PLLBCK] = hw; 180 181 parent_names[0] = slck_name; 182 parent_names[1] = "mainck"; 183 parent_names[2] = "plladivck"; 184 parent_names[3] = "pllbck"; 185 hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4, 186 parent_names, NULL, 187 &at91sam9x5_master_layout, 188 &mck_characteristics, 189 &at91sam9n12_mck_lock); 190 if (IS_ERR(hw)) 191 goto err_free; 192 193 hw = at91_clk_register_master_div(regmap, "masterck_div", 194 "masterck_pres", NULL, 195 &at91sam9x5_master_layout, 196 &mck_characteristics, 197 &at91sam9n12_mck_lock, 198 CLK_SET_RATE_GATE, 0); 199 if (IS_ERR(hw)) 200 goto err_free; 201 202 at91sam9n12_pmc->chws[PMC_MCK] = hw; 203 204 hw = at91sam9n12_clk_register_usb(regmap, "usbck", "pllbck"); 205 if (IS_ERR(hw)) 206 goto err_free; 207 208 parent_names[0] = slck_name; 209 parent_names[1] = "mainck"; 210 parent_names[2] = "plladivck"; 211 parent_names[3] = "pllbck"; 212 parent_names[4] = "masterck_div"; 213 for (i = 0; i < 2; i++) { 214 char name[6]; 215 216 snprintf(name, sizeof(name), "prog%d", i); 217 218 hw = at91_clk_register_programmable(regmap, name, 219 parent_names, NULL, 5, i, 220 &at91sam9x5_programmable_layout, 221 NULL); 222 if (IS_ERR(hw)) 223 goto err_free; 224 225 at91sam9n12_pmc->pchws[i] = hw; 226 } 227 228 for (i = 0; i < ARRAY_SIZE(at91sam9n12_systemck); i++) { 229 hw = at91_clk_register_system(regmap, at91sam9n12_systemck[i].n, 230 at91sam9n12_systemck[i].p, NULL, 231 at91sam9n12_systemck[i].id, 232 at91sam9n12_systemck[i].flags); 233 if (IS_ERR(hw)) 234 goto err_free; 235 236 at91sam9n12_pmc->shws[at91sam9n12_systemck[i].id] = hw; 237 } 238 239 for (i = 0; i < ARRAY_SIZE(at91sam9n12_periphck); i++) { 240 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, 241 &at91sam9n12_pcr_layout, 242 at91sam9n12_periphck[i].n, 243 "masterck_div", NULL, 244 at91sam9n12_periphck[i].id, 245 &range, INT_MIN, 0); 246 if (IS_ERR(hw)) 247 goto err_free; 248 249 at91sam9n12_pmc->phws[at91sam9n12_periphck[i].id] = hw; 250 } 251 252 of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9n12_pmc); 253 254 return; 255 256 err_free: 257 kfree(at91sam9n12_pmc); 258 } 259 /* 260 * The TCB is used as the clocksource so its clock is needed early. This means 261 * this can't be a platform driver. 262 */ 263 CLK_OF_DECLARE(at91sam9n12_pmc, "atmel,at91sam9n12-pmc", at91sam9n12_pmc_setup); 264