1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Actions Semi S700 clock driver 4 * 5 * Copyright (c) 2014 Actions Semi Inc. 6 * Author: David Liu <liuwei@actions-semi.com> 7 * 8 * Author: Pathiban Nallathambi <pn@denx.de> 9 * Author: Saravanan Sekar <sravanhome@gmail.com> 10 */ 11 12 #include <linux/clk-provider.h> 13 #include <linux/platform_device.h> 14 15 #include "owl-common.h" 16 #include "owl-composite.h" 17 #include "owl-divider.h" 18 #include "owl-factor.h" 19 #include "owl-fixed-factor.h" 20 #include "owl-gate.h" 21 #include "owl-mux.h" 22 #include "owl-pll.h" 23 24 #include <dt-bindings/clock/actions,s700-cmu.h> 25 26 #define CMU_COREPLL (0x0000) 27 #define CMU_DEVPLL (0x0004) 28 #define CMU_DDRPLL (0x0008) 29 #define CMU_NANDPLL (0x000C) 30 #define CMU_DISPLAYPLL (0x0010) 31 #define CMU_AUDIOPLL (0x0014) 32 #define CMU_TVOUTPLL (0x0018) 33 #define CMU_BUSCLK (0x001C) 34 #define CMU_SENSORCLK (0x0020) 35 #define CMU_LCDCLK (0x0024) 36 #define CMU_DSIPLLCLK (0x0028) 37 #define CMU_CSICLK (0x002C) 38 #define CMU_DECLK (0x0030) 39 #define CMU_SICLK (0x0034) 40 #define CMU_BUSCLK1 (0x0038) 41 #define CMU_HDECLK (0x003C) 42 #define CMU_VDECLK (0x0040) 43 #define CMU_VCECLK (0x0044) 44 #define CMU_NANDCCLK (0x004C) 45 #define CMU_SD0CLK (0x0050) 46 #define CMU_SD1CLK (0x0054) 47 #define CMU_SD2CLK (0x0058) 48 #define CMU_UART0CLK (0x005C) 49 #define CMU_UART1CLK (0x0060) 50 #define CMU_UART2CLK (0x0064) 51 #define CMU_UART3CLK (0x0068) 52 #define CMU_UART4CLK (0x006C) 53 #define CMU_UART5CLK (0x0070) 54 #define CMU_UART6CLK (0x0074) 55 #define CMU_PWM0CLK (0x0078) 56 #define CMU_PWM1CLK (0x007C) 57 #define CMU_PWM2CLK (0x0080) 58 #define CMU_PWM3CLK (0x0084) 59 #define CMU_PWM4CLK (0x0088) 60 #define CMU_PWM5CLK (0x008C) 61 #define CMU_GPU3DCLK (0x0090) 62 #define CMU_CORECTL (0x009C) 63 #define CMU_DEVCLKEN0 (0x00A0) 64 #define CMU_DEVCLKEN1 (0x00A4) 65 #define CMU_DEVRST0 (0x00A8) 66 #define CMU_DEVRST1 (0x00AC) 67 #define CMU_USBPLL (0x00B0) 68 #define CMU_ETHERNETPLL (0x00B4) 69 #define CMU_CVBSPLL (0x00B8) 70 #define CMU_SSTSCLK (0x00C0) 71 72 static struct clk_pll_table clk_audio_pll_table[] = { 73 {0, 45158400}, {1, 49152000}, 74 {0, 0}, 75 }; 76 77 static struct clk_pll_table clk_cvbs_pll_table[] = { 78 {27, 29 * 12000000}, {28, 30 * 12000000}, {29, 31 * 12000000}, 79 {30, 32 * 12000000}, {31, 33 * 12000000}, {32, 34 * 12000000}, 80 {33, 35 * 12000000}, {34, 36 * 12000000}, {35, 37 * 12000000}, 81 {36, 38 * 12000000}, {37, 39 * 12000000}, {38, 40 * 12000000}, 82 {39, 41 * 12000000}, {40, 42 * 12000000}, {41, 43 * 12000000}, 83 {42, 44 * 12000000}, {43, 45 * 12000000}, {0, 0}, 84 }; 85 86 /* pll clocks */ 87 static OWL_PLL_NO_PARENT(clk_core_pll, "core_pll", CMU_COREPLL, 12000000, 9, 0, 8, 4, 174, NULL, CLK_IGNORE_UNUSED); 88 static OWL_PLL_NO_PARENT(clk_dev_pll, "dev_pll", CMU_DEVPLL, 6000000, 8, 0, 8, 8, 126, NULL, CLK_IGNORE_UNUSED); 89 static OWL_PLL_NO_PARENT(clk_ddr_pll, "ddr_pll", CMU_DDRPLL, 6000000, 8, 0, 8, 2, 180, NULL, CLK_IGNORE_UNUSED); 90 static OWL_PLL_NO_PARENT(clk_nand_pll, "nand_pll", CMU_NANDPLL, 6000000, 8, 0, 8, 2, 86, NULL, CLK_IGNORE_UNUSED); 91 static OWL_PLL_NO_PARENT(clk_display_pll, "display_pll", CMU_DISPLAYPLL, 6000000, 8, 0, 8, 2, 140, NULL, CLK_IGNORE_UNUSED); 92 static OWL_PLL_NO_PARENT(clk_cvbs_pll, "cvbs_pll", CMU_CVBSPLL, 0, 8, 0, 8, 27, 43, clk_cvbs_pll_table, CLK_IGNORE_UNUSED); 93 static OWL_PLL_NO_PARENT(clk_audio_pll, "audio_pll", CMU_AUDIOPLL, 0, 4, 0, 1, 0, 0, clk_audio_pll_table, CLK_IGNORE_UNUSED); 94 static OWL_PLL_NO_PARENT(clk_ethernet_pll, "ethernet_pll", CMU_ETHERNETPLL, 500000000, 0, 0, 0, 0, 0, NULL, CLK_IGNORE_UNUSED); 95 96 static const char *cpu_clk_mux_p[] = {"losc", "hosc", "core_pll", "noc1_clk_div"}; 97 static const char *dev_clk_p[] = { "hosc", "dev_pll"}; 98 static const char *noc_clk_mux_p[] = { "dev_clk", "display_pll", "nand_pll", "ddr_pll", "cvbs_pll"}; 99 100 static const char *csi_clk_mux_p[] = { "display_pll", "dev_clk"}; 101 static const char *de_clk_mux_p[] = { "display_pll", "dev_clk"}; 102 static const char *hde_clk_mux_p[] = { "dev_clk", "display_pll", "nand_pll", "ddr_pll"}; 103 static const char *nand_clk_mux_p[] = { "nand_pll", "display_pll", "dev_clk", "ddr_pll"}; 104 static const char *sd_clk_mux_p[] = { "dev_clk", "nand_pll", }; 105 static const char *uart_clk_mux_p[] = { "hosc", "dev_pll"}; 106 static const char *pwm_clk_mux_p[] = { "losc", "hosc"}; 107 static const char *gpu_clk_mux_p[] = { "dev_clk", "display_pll", "nand_pll", "ddr_clk", "cvbs_pll"}; 108 static const char *lcd_clk_mux_p[] = { "display_pll", "dev_clk" }; 109 static const char *i2s_clk_mux_p[] = { "audio_pll" }; 110 static const char *sensor_clk_mux_p[] = { "hosc", "si"}; 111 112 /* mux clocks */ 113 static OWL_MUX(clk_cpu, "cpu_clk", cpu_clk_mux_p, CMU_BUSCLK, 0, 2, CLK_SET_RATE_PARENT); 114 static OWL_MUX(clk_dev, "dev_clk", dev_clk_p, CMU_DEVPLL, 12, 1, CLK_SET_RATE_PARENT); 115 static OWL_MUX(clk_noc0_clk_mux, "noc0_clk_mux", noc_clk_mux_p, CMU_BUSCLK, 4, 3, CLK_SET_RATE_PARENT); 116 static OWL_MUX(clk_noc1_clk_mux, "noc1_clk_mux", noc_clk_mux_p, CMU_BUSCLK1, 4, 3, CLK_SET_RATE_PARENT); 117 static OWL_MUX(clk_hp_clk_mux, "hp_clk_mux", noc_clk_mux_p, CMU_BUSCLK1, 8, 3, CLK_SET_RATE_PARENT); 118 119 static struct clk_factor_table sd_factor_table[] = { 120 /* bit0 ~ 4 */ 121 {0, 1, 1}, {1, 1, 2}, {2, 1, 3}, {3, 1, 4}, 122 {4, 1, 5}, {5, 1, 6}, {6, 1, 7}, {7, 1, 8}, 123 {8, 1, 9}, {9, 1, 10}, {10, 1, 11}, {11, 1, 12}, 124 {12, 1, 13}, {13, 1, 14}, {14, 1, 15}, {15, 1, 16}, 125 {16, 1, 17}, {17, 1, 18}, {18, 1, 19}, {19, 1, 20}, 126 {20, 1, 21}, {21, 1, 22}, {22, 1, 23}, {23, 1, 24}, 127 {24, 1, 25}, {25, 1, 26}, 128 129 /* bit8: /128 */ 130 {256, 1, 1 * 128}, {257, 1, 2 * 128}, {258, 1, 3 * 128}, {259, 1, 4 * 128}, 131 {260, 1, 5 * 128}, {261, 1, 6 * 128}, {262, 1, 7 * 128}, {263, 1, 8 * 128}, 132 {264, 1, 9 * 128}, {265, 1, 10 * 128}, {266, 1, 11 * 128}, {267, 1, 12 * 128}, 133 {268, 1, 13 * 128}, {269, 1, 14 * 128}, {270, 1, 15 * 128}, {271, 1, 16 * 128}, 134 {272, 1, 17 * 128}, {273, 1, 18 * 128}, {274, 1, 19 * 128}, {275, 1, 20 * 128}, 135 {276, 1, 21 * 128}, {277, 1, 22 * 128}, {278, 1, 23 * 128}, {279, 1, 24 * 128}, 136 {280, 1, 25 * 128}, {281, 1, 26 * 128}, 137 138 {0, 0}, 139 }; 140 141 static struct clk_factor_table lcd_factor_table[] = { 142 /* bit0 ~ 3 */ 143 {0, 1, 1}, {1, 1, 2}, {2, 1, 3}, {3, 1, 4}, 144 {4, 1, 5}, {5, 1, 6}, {6, 1, 7}, {7, 1, 8}, 145 {8, 1, 9}, {9, 1, 10}, {10, 1, 11}, {11, 1, 12}, 146 147 /* bit8: /7 */ 148 {256, 1, 1 * 7}, {257, 1, 2 * 7}, {258, 1, 3 * 7}, {259, 1, 4 * 7}, 149 {260, 1, 5 * 7}, {261, 1, 6 * 7}, {262, 1, 7 * 7}, {263, 1, 8 * 7}, 150 {264, 1, 9 * 7}, {265, 1, 10 * 7}, {266, 1, 11 * 7}, {267, 1, 12 * 7}, 151 {0, 0}, 152 }; 153 154 static struct clk_div_table hdmia_div_table[] = { 155 {0, 1}, {1, 2}, {2, 3}, {3, 4}, 156 {4, 6}, {5, 8}, {6, 12}, {7, 16}, 157 {8, 24}, 158 {0, 0}, 159 }; 160 161 static struct clk_div_table rmii_div_table[] = { 162 {0, 4}, {1, 10}, 163 }; 164 165 /* divider clocks */ 166 static OWL_DIVIDER(clk_noc0, "noc0_clk", "noc0_clk_mux", CMU_BUSCLK, 16, 2, NULL, 0, 0); 167 static OWL_DIVIDER(clk_noc1, "noc1_clk", "noc1_clk_mux", CMU_BUSCLK1, 16, 2, NULL, 0, 0); 168 static OWL_DIVIDER(clk_noc1_clk_div, "noc1_clk_div", "noc1_clk", CMU_BUSCLK1, 20, 1, NULL, 0, 0); 169 static OWL_DIVIDER(clk_hp_clk_div, "hp_clk_div", "hp_clk_mux", CMU_BUSCLK1, 12, 2, NULL, 0, 0); 170 static OWL_DIVIDER(clk_ahb, "ahb_clk", "hp_clk_div", CMU_BUSCLK1, 2, 2, NULL, 0, 0); 171 static OWL_DIVIDER(clk_apb, "apb_clk", "ahb_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0); 172 static OWL_DIVIDER(clk_sensor0, "sensor0", "sensor_src", CMU_SENSORCLK, 0, 4, NULL, 0, 0); 173 static OWL_DIVIDER(clk_sensor1, "sensor1", "sensor_src", CMU_SENSORCLK, 8, 4, NULL, 0, 0); 174 static OWL_DIVIDER(clk_rmii_ref, "rmii_ref", "ethernet_pll", CMU_ETHERNETPLL, 2, 1, rmii_div_table, 0, 0); 175 176 static struct clk_factor_table de_factor_table[] = { 177 {0, 1, 1}, {1, 2, 3}, {2, 1, 2}, {3, 2, 5}, 178 {4, 1, 3}, {5, 1, 4}, {6, 1, 6}, {7, 1, 8}, 179 {8, 1, 12}, {0, 0, 0}, 180 }; 181 182 static struct clk_factor_table hde_factor_table[] = { 183 {0, 1, 1}, {1, 2, 3}, {2, 1, 2}, {3, 2, 5}, 184 {4, 1, 3}, {5, 1, 4}, {6, 1, 6}, {7, 1, 8}, 185 {0, 0, 0}, 186 }; 187 188 /* gate clocks */ 189 static OWL_GATE(clk_gpio, "gpio", "apb_clk", CMU_DEVCLKEN1, 25, 0, 0); 190 static OWL_GATE(clk_dmac, "dmac", "hp_clk_div", CMU_DEVCLKEN0, 17, 0, 0); 191 static OWL_GATE(clk_timer, "timer", "hosc", CMU_DEVCLKEN1, 22, 0, 0); 192 static OWL_GATE_NO_PARENT(clk_dsi, "dsi_clk", CMU_DEVCLKEN0, 2, 0, 0); 193 static OWL_GATE_NO_PARENT(clk_tvout, "tvout_clk", CMU_DEVCLKEN0, 3, 0, 0); 194 static OWL_GATE_NO_PARENT(clk_hdmi_dev, "hdmi_dev", CMU_DEVCLKEN0, 5, 0, 0); 195 static OWL_GATE_NO_PARENT(clk_usb3_480mpll0, "usb3_480mpll0", CMU_USBPLL, 3, 0, 0); 196 static OWL_GATE_NO_PARENT(clk_usb3_480mphy0, "usb3_480mphy0", CMU_USBPLL, 2, 0, 0); 197 static OWL_GATE_NO_PARENT(clk_usb3_5gphy, "usb3_5gphy", CMU_USBPLL, 1, 0, 0); 198 static OWL_GATE_NO_PARENT(clk_usb3_cce, "usb3_cce", CMU_DEVCLKEN0, 25, 0, 0); 199 static OWL_GATE(clk_i2c0, "i2c0", "hosc", CMU_DEVCLKEN1, 0, 0, 0); 200 static OWL_GATE(clk_i2c1, "i2c1", "hosc", CMU_DEVCLKEN1, 1, 0, 0); 201 static OWL_GATE(clk_i2c2, "i2c2", "hosc", CMU_DEVCLKEN1, 2, 0, 0); 202 static OWL_GATE(clk_i2c3, "i2c3", "hosc", CMU_DEVCLKEN1, 3, 0, 0); 203 static OWL_GATE(clk_spi0, "spi0", "ahb_clk", CMU_DEVCLKEN1, 4, 0, 0); 204 static OWL_GATE(clk_spi1, "spi1", "ahb_clk", CMU_DEVCLKEN1, 5, 0, 0); 205 static OWL_GATE(clk_spi2, "spi2", "ahb_clk", CMU_DEVCLKEN1, 6, 0, 0); 206 static OWL_GATE(clk_spi3, "spi3", "ahb_clk", CMU_DEVCLKEN1, 7, 0, 0); 207 static OWL_GATE_NO_PARENT(clk_usb2h0_pllen, "usbh0_pllen", CMU_USBPLL, 12, 0, 0); 208 static OWL_GATE_NO_PARENT(clk_usb2h0_phy, "usbh0_phy", CMU_USBPLL, 10, 0, 0); 209 static OWL_GATE_NO_PARENT(clk_usb2h0_cce, "usbh0_cce", CMU_DEVCLKEN0, 26, 0, 0); 210 static OWL_GATE_NO_PARENT(clk_usb2h1_pllen, "usbh1_pllen", CMU_USBPLL, 13, 0, 0); 211 static OWL_GATE_NO_PARENT(clk_usb2h1_phy, "usbh1_phy", CMU_USBPLL, 11, 0, 0); 212 static OWL_GATE_NO_PARENT(clk_usb2h1_cce, "usbh1_cce", CMU_DEVCLKEN0, 27, 0, 0); 213 static OWL_GATE_NO_PARENT(clk_irc_switch, "irc_switch", CMU_DEVCLKEN1, 15, 0, 0); 214 215 /* composite clocks */ 216 217 static OWL_COMP_DIV(clk_csi, "csi", csi_clk_mux_p, 218 OWL_MUX_HW(CMU_CSICLK, 4, 1), 219 OWL_GATE_HW(CMU_DEVCLKEN0, 13, 0), 220 OWL_DIVIDER_HW(CMU_CSICLK, 0, 4, 0, NULL), 221 0); 222 223 static OWL_COMP_DIV(clk_si, "si", csi_clk_mux_p, 224 OWL_MUX_HW(CMU_SICLK, 4, 1), 225 OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0), 226 OWL_DIVIDER_HW(CMU_SICLK, 0, 4, 0, NULL), 227 0); 228 229 static OWL_COMP_FACTOR(clk_de, "de", de_clk_mux_p, 230 OWL_MUX_HW(CMU_DECLK, 12, 1), 231 OWL_GATE_HW(CMU_DEVCLKEN0, 0, 0), 232 OWL_FACTOR_HW(CMU_DECLK, 0, 3, 0, de_factor_table), 233 0); 234 235 static OWL_COMP_FACTOR(clk_hde, "hde", hde_clk_mux_p, 236 OWL_MUX_HW(CMU_HDECLK, 4, 2), 237 OWL_GATE_HW(CMU_DEVCLKEN0, 9, 0), 238 OWL_FACTOR_HW(CMU_HDECLK, 0, 3, 0, hde_factor_table), 239 0); 240 241 static OWL_COMP_FACTOR(clk_vde, "vde", hde_clk_mux_p, 242 OWL_MUX_HW(CMU_VDECLK, 4, 2), 243 OWL_GATE_HW(CMU_DEVCLKEN0, 10, 0), 244 OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, hde_factor_table), 245 0); 246 247 static OWL_COMP_FACTOR(clk_vce, "vce", hde_clk_mux_p, 248 OWL_MUX_HW(CMU_VCECLK, 4, 2), 249 OWL_GATE_HW(CMU_DEVCLKEN0, 11, 0), 250 OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, hde_factor_table), 251 0); 252 253 static OWL_COMP_DIV(clk_nand, "nand", nand_clk_mux_p, 254 OWL_MUX_HW(CMU_NANDCCLK, 8, 2), 255 OWL_GATE_HW(CMU_DEVCLKEN0, 21, 0), 256 OWL_DIVIDER_HW(CMU_NANDCCLK, 0, 3, 0, NULL), 257 CLK_SET_RATE_PARENT); 258 259 static OWL_COMP_FACTOR(clk_sd0, "sd0", sd_clk_mux_p, 260 OWL_MUX_HW(CMU_SD0CLK, 9, 1), 261 OWL_GATE_HW(CMU_DEVCLKEN0, 22, 0), 262 OWL_FACTOR_HW(CMU_SD0CLK, 0, 9, 0, sd_factor_table), 263 0); 264 265 static OWL_COMP_FACTOR(clk_sd1, "sd1", sd_clk_mux_p, 266 OWL_MUX_HW(CMU_SD1CLK, 9, 1), 267 OWL_GATE_HW(CMU_DEVCLKEN0, 23, 0), 268 OWL_FACTOR_HW(CMU_SD1CLK, 0, 9, 0, sd_factor_table), 269 0); 270 271 static OWL_COMP_FACTOR(clk_sd2, "sd2", sd_clk_mux_p, 272 OWL_MUX_HW(CMU_SD2CLK, 9, 1), 273 OWL_GATE_HW(CMU_DEVCLKEN0, 24, 0), 274 OWL_FACTOR_HW(CMU_SD2CLK, 0, 9, 0, sd_factor_table), 275 0); 276 277 static OWL_COMP_DIV(clk_uart0, "uart0", uart_clk_mux_p, 278 OWL_MUX_HW(CMU_UART0CLK, 16, 1), 279 OWL_GATE_HW(CMU_DEVCLKEN1, 8, 0), 280 OWL_DIVIDER_HW(CMU_UART0CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL), 281 0); 282 283 static OWL_COMP_DIV(clk_uart1, "uart1", uart_clk_mux_p, 284 OWL_MUX_HW(CMU_UART1CLK, 16, 1), 285 OWL_GATE_HW(CMU_DEVCLKEN1, 9, 0), 286 OWL_DIVIDER_HW(CMU_UART1CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL), 287 0); 288 289 static OWL_COMP_DIV(clk_uart2, "uart2", uart_clk_mux_p, 290 OWL_MUX_HW(CMU_UART2CLK, 16, 1), 291 OWL_GATE_HW(CMU_DEVCLKEN1, 10, 0), 292 OWL_DIVIDER_HW(CMU_UART2CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL), 293 0); 294 295 static OWL_COMP_DIV(clk_uart3, "uart3", uart_clk_mux_p, 296 OWL_MUX_HW(CMU_UART3CLK, 16, 1), 297 OWL_GATE_HW(CMU_DEVCLKEN1, 11, 0), 298 OWL_DIVIDER_HW(CMU_UART3CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL), 299 0); 300 301 static OWL_COMP_DIV(clk_uart4, "uart4", uart_clk_mux_p, 302 OWL_MUX_HW(CMU_UART4CLK, 16, 1), 303 OWL_GATE_HW(CMU_DEVCLKEN1, 12, 0), 304 OWL_DIVIDER_HW(CMU_UART4CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL), 305 0); 306 307 static OWL_COMP_DIV(clk_uart5, "uart5", uart_clk_mux_p, 308 OWL_MUX_HW(CMU_UART5CLK, 16, 1), 309 OWL_GATE_HW(CMU_DEVCLKEN1, 13, 0), 310 OWL_DIVIDER_HW(CMU_UART5CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL), 311 0); 312 313 static OWL_COMP_DIV(clk_uart6, "uart6", uart_clk_mux_p, 314 OWL_MUX_HW(CMU_UART6CLK, 16, 1), 315 OWL_GATE_HW(CMU_DEVCLKEN1, 14, 0), 316 OWL_DIVIDER_HW(CMU_UART6CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL), 317 0); 318 319 static OWL_COMP_DIV(clk_pwm0, "pwm0", pwm_clk_mux_p, 320 OWL_MUX_HW(CMU_PWM0CLK, 12, 1), 321 OWL_GATE_HW(CMU_DEVCLKEN1, 16, 0), 322 OWL_DIVIDER_HW(CMU_PWM0CLK, 0, 10, 0, NULL), 323 CLK_IGNORE_UNUSED); 324 325 static OWL_COMP_DIV(clk_pwm1, "pwm1", pwm_clk_mux_p, 326 OWL_MUX_HW(CMU_PWM1CLK, 12, 1), 327 OWL_GATE_HW(CMU_DEVCLKEN1, 17, 0), 328 OWL_DIVIDER_HW(CMU_PWM1CLK, 0, 10, 0, NULL), 329 0); 330 331 static OWL_COMP_DIV(clk_pwm2, "pwm2", pwm_clk_mux_p, 332 OWL_MUX_HW(CMU_PWM2CLK, 12, 1), 333 OWL_GATE_HW(CMU_DEVCLKEN1, 18, 0), 334 OWL_DIVIDER_HW(CMU_PWM2CLK, 0, 10, 0, NULL), 335 0); 336 337 static OWL_COMP_DIV(clk_pwm3, "pwm3", pwm_clk_mux_p, 338 OWL_MUX_HW(CMU_PWM3CLK, 12, 1), 339 OWL_GATE_HW(CMU_DEVCLKEN1, 19, 0), 340 OWL_DIVIDER_HW(CMU_PWM3CLK, 0, 10, 0, NULL), 341 0); 342 343 static OWL_COMP_DIV(clk_pwm4, "pwm4", pwm_clk_mux_p, 344 OWL_MUX_HW(CMU_PWM4CLK, 12, 1), 345 OWL_GATE_HW(CMU_DEVCLKEN1, 20, 0), 346 OWL_DIVIDER_HW(CMU_PWM4CLK, 0, 10, 0, NULL), 347 0); 348 349 static OWL_COMP_DIV(clk_pwm5, "pwm5", pwm_clk_mux_p, 350 OWL_MUX_HW(CMU_PWM5CLK, 12, 1), 351 OWL_GATE_HW(CMU_DEVCLKEN1, 21, 0), 352 OWL_DIVIDER_HW(CMU_PWM5CLK, 0, 10, 0, NULL), 353 0); 354 355 static OWL_COMP_FACTOR(clk_gpu3d, "gpu3d", gpu_clk_mux_p, 356 OWL_MUX_HW(CMU_GPU3DCLK, 4, 3), 357 OWL_GATE_HW(CMU_DEVCLKEN0, 8, 0), 358 OWL_FACTOR_HW(CMU_GPU3DCLK, 0, 3, 0, hde_factor_table), 359 0); 360 361 static OWL_COMP_FACTOR(clk_lcd, "lcd", lcd_clk_mux_p, 362 OWL_MUX_HW(CMU_LCDCLK, 12, 2), 363 OWL_GATE_HW(CMU_DEVCLKEN0, 1, 0), 364 OWL_FACTOR_HW(CMU_LCDCLK, 0, 9, 0, lcd_factor_table), 365 0); 366 367 static OWL_COMP_DIV(clk_hdmi_audio, "hdmia", i2s_clk_mux_p, 368 OWL_MUX_HW(CMU_AUDIOPLL, 24, 1), /*CMU_AUDIOPLL 24,1 unused*/ 369 OWL_GATE_HW(CMU_DEVCLKEN1, 28, 0), 370 OWL_DIVIDER_HW(CMU_AUDIOPLL, 24, 4, 0, hdmia_div_table), 371 0); 372 373 static OWL_COMP_DIV(clk_i2srx, "i2srx", i2s_clk_mux_p, 374 OWL_MUX_HW(CMU_AUDIOPLL, 24, 1), 375 OWL_GATE_HW(CMU_DEVCLKEN1, 27, 0), 376 OWL_DIVIDER_HW(CMU_AUDIOPLL, 20, 4, 0, hdmia_div_table), 377 0); 378 379 static OWL_COMP_DIV(clk_i2stx, "i2stx", i2s_clk_mux_p, 380 OWL_MUX_HW(CMU_AUDIOPLL, 24, 1), 381 OWL_GATE_HW(CMU_DEVCLKEN1, 26, 0), 382 OWL_DIVIDER_HW(CMU_AUDIOPLL, 16, 4, 0, hdmia_div_table), 383 0); 384 385 /* for bluetooth pcm communication */ 386 static OWL_COMP_FIXED_FACTOR(clk_pcm1, "pcm1", "audio_pll", 387 OWL_GATE_HW(CMU_DEVCLKEN1, 31, 0), 388 1, 2, 0); 389 390 static OWL_COMP_DIV(clk_sensor_src, "sensor_src", sensor_clk_mux_p, 391 OWL_MUX_HW(CMU_SENSORCLK, 4, 1), 392 {0}, 393 OWL_DIVIDER_HW(CMU_SENSORCLK, 5, 2, 0, NULL), 394 0); 395 396 static OWL_COMP_FIXED_FACTOR(clk_ethernet, "ethernet", "ethernet_pll", 397 OWL_GATE_HW(CMU_DEVCLKEN1, 23, 0), 398 1, 20, 0); 399 400 static OWL_COMP_DIV_FIXED(clk_thermal_sensor, "thermal_sensor", "hosc", 401 OWL_GATE_HW(CMU_DEVCLKEN0, 31, 0), 402 OWL_DIVIDER_HW(CMU_SSTSCLK, 20, 10, 0, NULL), 403 0); 404 405 static struct owl_clk_common *s700_clks[] = { 406 &clk_core_pll.common, 407 &clk_dev_pll.common, 408 &clk_ddr_pll.common, 409 &clk_nand_pll.common, 410 &clk_display_pll.common, 411 &clk_cvbs_pll .common, 412 &clk_audio_pll.common, 413 &clk_ethernet_pll.common, 414 &clk_cpu.common, 415 &clk_dev.common, 416 &clk_ahb.common, 417 &clk_apb.common, 418 &clk_dmac.common, 419 &clk_noc0_clk_mux.common, 420 &clk_noc1_clk_mux.common, 421 &clk_hp_clk_mux.common, 422 &clk_hp_clk_div.common, 423 &clk_noc1_clk_div.common, 424 &clk_noc0.common, 425 &clk_noc1.common, 426 &clk_sensor_src.common, 427 &clk_gpio.common, 428 &clk_timer.common, 429 &clk_dsi.common, 430 &clk_csi.common, 431 &clk_si.common, 432 &clk_de.common, 433 &clk_hde.common, 434 &clk_vde.common, 435 &clk_vce.common, 436 &clk_nand.common, 437 &clk_sd0.common, 438 &clk_sd1.common, 439 &clk_sd2.common, 440 &clk_uart0.common, 441 &clk_uart1.common, 442 &clk_uart2.common, 443 &clk_uart3.common, 444 &clk_uart4.common, 445 &clk_uart5.common, 446 &clk_uart6.common, 447 &clk_pwm0.common, 448 &clk_pwm1.common, 449 &clk_pwm2.common, 450 &clk_pwm3.common, 451 &clk_pwm4.common, 452 &clk_pwm5.common, 453 &clk_gpu3d.common, 454 &clk_i2c0.common, 455 &clk_i2c1.common, 456 &clk_i2c2.common, 457 &clk_i2c3.common, 458 &clk_spi0.common, 459 &clk_spi1.common, 460 &clk_spi2.common, 461 &clk_spi3.common, 462 &clk_usb3_480mpll0.common, 463 &clk_usb3_480mphy0.common, 464 &clk_usb3_5gphy.common, 465 &clk_usb3_cce.common, 466 &clk_lcd.common, 467 &clk_hdmi_audio.common, 468 &clk_i2srx.common, 469 &clk_i2stx.common, 470 &clk_sensor0.common, 471 &clk_sensor1.common, 472 &clk_hdmi_dev.common, 473 &clk_ethernet.common, 474 &clk_rmii_ref.common, 475 &clk_usb2h0_pllen.common, 476 &clk_usb2h0_phy.common, 477 &clk_usb2h0_cce.common, 478 &clk_usb2h1_pllen.common, 479 &clk_usb2h1_phy.common, 480 &clk_usb2h1_cce.common, 481 &clk_tvout.common, 482 &clk_thermal_sensor.common, 483 &clk_irc_switch.common, 484 &clk_pcm1.common, 485 }; 486 487 static struct clk_hw_onecell_data s700_hw_clks = { 488 .hws = { 489 [CLK_CORE_PLL] = &clk_core_pll.common.hw, 490 [CLK_DEV_PLL] = &clk_dev_pll.common.hw, 491 [CLK_DDR_PLL] = &clk_ddr_pll.common.hw, 492 [CLK_NAND_PLL] = &clk_nand_pll.common.hw, 493 [CLK_DISPLAY_PLL] = &clk_display_pll.common.hw, 494 [CLK_CVBS_PLL] = &clk_cvbs_pll .common.hw, 495 [CLK_AUDIO_PLL] = &clk_audio_pll.common.hw, 496 [CLK_ETHERNET_PLL] = &clk_ethernet_pll.common.hw, 497 [CLK_CPU] = &clk_cpu.common.hw, 498 [CLK_DEV] = &clk_dev.common.hw, 499 [CLK_AHB] = &clk_ahb.common.hw, 500 [CLK_APB] = &clk_apb.common.hw, 501 [CLK_DMAC] = &clk_dmac.common.hw, 502 [CLK_NOC0_CLK_MUX] = &clk_noc0_clk_mux.common.hw, 503 [CLK_NOC1_CLK_MUX] = &clk_noc1_clk_mux.common.hw, 504 [CLK_HP_CLK_MUX] = &clk_hp_clk_mux.common.hw, 505 [CLK_HP_CLK_DIV] = &clk_hp_clk_div.common.hw, 506 [CLK_NOC1_CLK_DIV] = &clk_noc1_clk_div.common.hw, 507 [CLK_NOC0] = &clk_noc0.common.hw, 508 [CLK_NOC1] = &clk_noc1.common.hw, 509 [CLK_SENOR_SRC] = &clk_sensor_src.common.hw, 510 [CLK_GPIO] = &clk_gpio.common.hw, 511 [CLK_TIMER] = &clk_timer.common.hw, 512 [CLK_DSI] = &clk_dsi.common.hw, 513 [CLK_CSI] = &clk_csi.common.hw, 514 [CLK_SI] = &clk_si.common.hw, 515 [CLK_DE] = &clk_de.common.hw, 516 [CLK_HDE] = &clk_hde.common.hw, 517 [CLK_VDE] = &clk_vde.common.hw, 518 [CLK_VCE] = &clk_vce.common.hw, 519 [CLK_NAND] = &clk_nand.common.hw, 520 [CLK_SD0] = &clk_sd0.common.hw, 521 [CLK_SD1] = &clk_sd1.common.hw, 522 [CLK_SD2] = &clk_sd2.common.hw, 523 [CLK_UART0] = &clk_uart0.common.hw, 524 [CLK_UART1] = &clk_uart1.common.hw, 525 [CLK_UART2] = &clk_uart2.common.hw, 526 [CLK_UART3] = &clk_uart3.common.hw, 527 [CLK_UART4] = &clk_uart4.common.hw, 528 [CLK_UART5] = &clk_uart5.common.hw, 529 [CLK_UART6] = &clk_uart6.common.hw, 530 [CLK_PWM0] = &clk_pwm0.common.hw, 531 [CLK_PWM1] = &clk_pwm1.common.hw, 532 [CLK_PWM2] = &clk_pwm2.common.hw, 533 [CLK_PWM3] = &clk_pwm3.common.hw, 534 [CLK_PWM4] = &clk_pwm4.common.hw, 535 [CLK_PWM5] = &clk_pwm5.common.hw, 536 [CLK_GPU3D] = &clk_gpu3d.common.hw, 537 [CLK_I2C0] = &clk_i2c0.common.hw, 538 [CLK_I2C1] = &clk_i2c1.common.hw, 539 [CLK_I2C2] = &clk_i2c2.common.hw, 540 [CLK_I2C3] = &clk_i2c3.common.hw, 541 [CLK_SPI0] = &clk_spi0.common.hw, 542 [CLK_SPI1] = &clk_spi1.common.hw, 543 [CLK_SPI2] = &clk_spi2.common.hw, 544 [CLK_SPI3] = &clk_spi3.common.hw, 545 [CLK_USB3_480MPLL0] = &clk_usb3_480mpll0.common.hw, 546 [CLK_USB3_480MPHY0] = &clk_usb3_480mphy0.common.hw, 547 [CLK_USB3_5GPHY] = &clk_usb3_5gphy.common.hw, 548 [CLK_USB3_CCE] = &clk_usb3_cce.common.hw, 549 [CLK_LCD] = &clk_lcd.common.hw, 550 [CLK_HDMI_AUDIO] = &clk_hdmi_audio.common.hw, 551 [CLK_I2SRX] = &clk_i2srx.common.hw, 552 [CLK_I2STX] = &clk_i2stx.common.hw, 553 [CLK_SENSOR0] = &clk_sensor0.common.hw, 554 [CLK_SENSOR1] = &clk_sensor1.common.hw, 555 [CLK_HDMI_DEV] = &clk_hdmi_dev.common.hw, 556 [CLK_ETHERNET] = &clk_ethernet.common.hw, 557 [CLK_RMII_REF] = &clk_rmii_ref.common.hw, 558 [CLK_USB2H0_PLLEN] = &clk_usb2h0_pllen.common.hw, 559 [CLK_USB2H0_PHY] = &clk_usb2h0_phy.common.hw, 560 [CLK_USB2H0_CCE] = &clk_usb2h0_cce.common.hw, 561 [CLK_USB2H1_PLLEN] = &clk_usb2h1_pllen.common.hw, 562 [CLK_USB2H1_PHY] = &clk_usb2h1_phy.common.hw, 563 [CLK_USB2H1_CCE] = &clk_usb2h1_cce.common.hw, 564 [CLK_TVOUT] = &clk_tvout.common.hw, 565 [CLK_THERMAL_SENSOR] = &clk_thermal_sensor.common.hw, 566 [CLK_IRC_SWITCH] = &clk_irc_switch.common.hw, 567 [CLK_PCM1] = &clk_pcm1.common.hw, 568 }, 569 .num = CLK_NR_CLKS, 570 }; 571 572 static const struct owl_clk_desc s700_clk_desc = { 573 .clks = s700_clks, 574 .num_clks = ARRAY_SIZE(s700_clks), 575 576 .hw_clks = &s700_hw_clks, 577 }; 578 579 static int s700_clk_probe(struct platform_device *pdev) 580 { 581 const struct owl_clk_desc *desc; 582 583 desc = &s700_clk_desc; 584 owl_clk_regmap_init(pdev, desc); 585 586 return owl_clk_probe(&pdev->dev, desc->hw_clks); 587 } 588 589 static const struct of_device_id s700_clk_of_match[] = { 590 { .compatible = "actions,s700-cmu", }, 591 { /* sentinel */ } 592 }; 593 594 static struct platform_driver s700_clk_driver = { 595 .probe = s700_clk_probe, 596 .driver = { 597 .name = "s700-cmu", 598 .of_match_table = s700_clk_of_match 599 }, 600 }; 601 602 static int __init s700_clk_init(void) 603 { 604 return platform_driver_register(&s700_clk_driver); 605 } 606 core_initcall(s700_clk_init); 607