1 /***************************************************************************** 2 * 3 * Author: Xilinx, Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2 of the License, or (at your 8 * option) any later version. 9 * 10 * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" 11 * AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND 12 * SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, 13 * OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, 14 * APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION 15 * THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, 16 * AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE 17 * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY 18 * WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE 19 * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR 20 * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF 21 * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 22 * FOR A PARTICULAR PURPOSE. 23 * 24 * Xilinx products are not intended for use in life support appliances, 25 * devices, or systems. Use in such applications is expressly prohibited. 26 * 27 * (c) Copyright 2003-2007 Xilinx Inc. 28 * All rights reserved. 29 * 30 * You should have received a copy of the GNU General Public License along 31 * with this program; if not, write to the Free Software Foundation, Inc., 32 * 675 Mass Ave, Cambridge, MA 02139, USA. 33 * 34 *****************************************************************************/ 35 36 #ifndef XILINX_HWICAP_H_ /* prevent circular inclusions */ 37 #define XILINX_HWICAP_H_ /* by using protection macros */ 38 39 #include <linux/types.h> 40 #include <linux/cdev.h> 41 #include <linux/platform_device.h> 42 43 #include <asm/io.h> 44 45 struct hwicap_drvdata { 46 u32 write_buffer_in_use; /* Always in [0,3] */ 47 u8 write_buffer[4]; 48 u32 read_buffer_in_use; /* Always in [0,3] */ 49 u8 read_buffer[4]; 50 resource_size_t mem_start;/* phys. address of the control registers */ 51 resource_size_t mem_end; /* phys. address of the control registers */ 52 resource_size_t mem_size; 53 void __iomem *base_address;/* virt. address of the control registers */ 54 55 struct device *dev; 56 struct cdev cdev; /* Char device structure */ 57 dev_t devt; 58 59 const struct hwicap_driver_config *config; 60 const struct config_registers *config_regs; 61 void *private_data; 62 bool is_open; 63 struct mutex sem; 64 }; 65 66 struct hwicap_driver_config { 67 /* Read configuration data given by size into the data buffer. 68 Return 0 if successful. */ 69 int (*get_configuration)(struct hwicap_drvdata *drvdata, u32 *data, 70 u32 size); 71 /* Write configuration data given by size from the data buffer. 72 Return 0 if successful. */ 73 int (*set_configuration)(struct hwicap_drvdata *drvdata, u32 *data, 74 u32 size); 75 /* Get the status register, bit pattern given by: 76 * D8 - 0 = configuration error 77 * D7 - 1 = alignment found 78 * D6 - 1 = readback in progress 79 * D5 - 0 = abort in progress 80 * D4 - Always 1 81 * D3 - Always 1 82 * D2 - Always 1 83 * D1 - Always 1 84 * D0 - 1 = operation completed 85 */ 86 u32 (*get_status)(struct hwicap_drvdata *drvdata); 87 /* Reset the hw */ 88 void (*reset)(struct hwicap_drvdata *drvdata); 89 }; 90 91 /* Number of times to poll the done regsiter */ 92 #define XHI_MAX_RETRIES 10 93 94 /************ Constant Definitions *************/ 95 96 #define XHI_PAD_FRAMES 0x1 97 98 /* Mask for calculating configuration packet headers */ 99 #define XHI_WORD_COUNT_MASK_TYPE_1 0x7FFUL 100 #define XHI_WORD_COUNT_MASK_TYPE_2 0x1FFFFFUL 101 #define XHI_TYPE_MASK 0x7 102 #define XHI_REGISTER_MASK 0xF 103 #define XHI_OP_MASK 0x3 104 105 #define XHI_TYPE_SHIFT 29 106 #define XHI_REGISTER_SHIFT 13 107 #define XHI_OP_SHIFT 27 108 109 #define XHI_TYPE_1 1 110 #define XHI_TYPE_2 2 111 #define XHI_OP_WRITE 2 112 #define XHI_OP_READ 1 113 114 /* Address Block Types */ 115 #define XHI_FAR_CLB_BLOCK 0 116 #define XHI_FAR_BRAM_BLOCK 1 117 #define XHI_FAR_BRAM_INT_BLOCK 2 118 119 struct config_registers { 120 u32 CRC; 121 u32 FAR; 122 u32 FDRI; 123 u32 FDRO; 124 u32 CMD; 125 u32 CTL; 126 u32 MASK; 127 u32 STAT; 128 u32 LOUT; 129 u32 COR; 130 u32 MFWR; 131 u32 FLR; 132 u32 KEY; 133 u32 CBC; 134 u32 IDCODE; 135 u32 AXSS; 136 u32 C0R_1; 137 u32 CSOB; 138 u32 WBSTAR; 139 u32 TIMER; 140 u32 BOOTSTS; 141 u32 CTL_1; 142 }; 143 144 /* Configuration Commands */ 145 #define XHI_CMD_NULL 0 146 #define XHI_CMD_WCFG 1 147 #define XHI_CMD_MFW 2 148 #define XHI_CMD_DGHIGH 3 149 #define XHI_CMD_RCFG 4 150 #define XHI_CMD_START 5 151 #define XHI_CMD_RCAP 6 152 #define XHI_CMD_RCRC 7 153 #define XHI_CMD_AGHIGH 8 154 #define XHI_CMD_SWITCH 9 155 #define XHI_CMD_GRESTORE 10 156 #define XHI_CMD_SHUTDOWN 11 157 #define XHI_CMD_GCAPTURE 12 158 #define XHI_CMD_DESYNCH 13 159 #define XHI_CMD_IPROG 15 /* Only in Virtex5 */ 160 #define XHI_CMD_CRCC 16 /* Only in Virtex5 */ 161 #define XHI_CMD_LTIMER 17 /* Only in Virtex5 */ 162 163 /* Packet constants */ 164 #define XHI_SYNC_PACKET 0xAA995566UL 165 #define XHI_DUMMY_PACKET 0xFFFFFFFFUL 166 #define XHI_NOOP_PACKET (XHI_TYPE_1 << XHI_TYPE_SHIFT) 167 #define XHI_TYPE_2_READ ((XHI_TYPE_2 << XHI_TYPE_SHIFT) | \ 168 (XHI_OP_READ << XHI_OP_SHIFT)) 169 170 #define XHI_TYPE_2_WRITE ((XHI_TYPE_2 << XHI_TYPE_SHIFT) | \ 171 (XHI_OP_WRITE << XHI_OP_SHIFT)) 172 173 #define XHI_TYPE2_CNT_MASK 0x07FFFFFF 174 175 #define XHI_TYPE_1_PACKET_MAX_WORDS 2047UL 176 #define XHI_TYPE_1_HEADER_BYTES 4 177 #define XHI_TYPE_2_HEADER_BYTES 8 178 179 /* Constant to use for CRC check when CRC has been disabled */ 180 #define XHI_DISABLED_AUTO_CRC 0x0000DEFCUL 181 182 /* Meanings of the bits returned by get_status */ 183 #define XHI_SR_CFGERR_N_MASK 0x00000100 /* Config Error Mask */ 184 #define XHI_SR_DALIGN_MASK 0x00000080 /* Data Alignment Mask */ 185 #define XHI_SR_RIP_MASK 0x00000040 /* Read back Mask */ 186 #define XHI_SR_IN_ABORT_N_MASK 0x00000020 /* Select Map Abort Mask */ 187 #define XHI_SR_DONE_MASK 0x00000001 /* Done bit Mask */ 188 189 /** 190 * hwicap_type_1_read - Generates a Type 1 read packet header. 191 * @reg: is the address of the register to be read back. 192 * 193 * Generates a Type 1 read packet header, which is used to indirectly 194 * read registers in the configuration logic. This packet must then 195 * be sent through the icap device, and a return packet received with 196 * the information. 197 **/ 198 static inline u32 hwicap_type_1_read(u32 reg) 199 { 200 return (XHI_TYPE_1 << XHI_TYPE_SHIFT) | 201 (reg << XHI_REGISTER_SHIFT) | 202 (XHI_OP_READ << XHI_OP_SHIFT); 203 } 204 205 /** 206 * hwicap_type_1_write - Generates a Type 1 write packet header 207 * @reg: is the address of the register to be read back. 208 **/ 209 static inline u32 hwicap_type_1_write(u32 reg) 210 { 211 return (XHI_TYPE_1 << XHI_TYPE_SHIFT) | 212 (reg << XHI_REGISTER_SHIFT) | 213 (XHI_OP_WRITE << XHI_OP_SHIFT); 214 } 215 216 #endif 217