1797c0113SAndrey Pronin // SPDX-License-Identifier: GPL-2.0 2797c0113SAndrey Pronin /* 3797c0113SAndrey Pronin * Copyright (C) 2016 Google, Inc 4797c0113SAndrey Pronin * 5797c0113SAndrey Pronin * This device driver implements a TCG PTP FIFO interface over SPI for chips 6797c0113SAndrey Pronin * with Cr50 firmware. 7797c0113SAndrey Pronin * It is based on tpm_tis_spi driver by Peter Huewe and Christophe Ricard. 8797c0113SAndrey Pronin */ 9797c0113SAndrey Pronin 10797c0113SAndrey Pronin #include <linux/completion.h> 11797c0113SAndrey Pronin #include <linux/interrupt.h> 12797c0113SAndrey Pronin #include <linux/module.h> 13797c0113SAndrey Pronin #include <linux/of.h> 14797c0113SAndrey Pronin #include <linux/pm.h> 15797c0113SAndrey Pronin #include <linux/spi/spi.h> 16797c0113SAndrey Pronin #include <linux/wait.h> 17797c0113SAndrey Pronin 18797c0113SAndrey Pronin #include "tpm_tis_core.h" 19797c0113SAndrey Pronin #include "tpm_tis_spi.h" 20797c0113SAndrey Pronin 21797c0113SAndrey Pronin /* 22797c0113SAndrey Pronin * Cr50 timing constants: 23797c0113SAndrey Pronin * - can go to sleep not earlier than after CR50_SLEEP_DELAY_MSEC. 24797c0113SAndrey Pronin * - needs up to CR50_WAKE_START_DELAY_USEC to wake after sleep. 25797c0113SAndrey Pronin * - requires waiting for "ready" IRQ, if supported; or waiting for at least 26797c0113SAndrey Pronin * CR50_NOIRQ_ACCESS_DELAY_MSEC between transactions, if IRQ is not supported. 27797c0113SAndrey Pronin * - waits for up to CR50_FLOW_CONTROL for flow control 'ready' indication. 28797c0113SAndrey Pronin */ 29797c0113SAndrey Pronin #define CR50_SLEEP_DELAY_MSEC 1000 30797c0113SAndrey Pronin #define CR50_WAKE_START_DELAY_USEC 1000 31797c0113SAndrey Pronin #define CR50_NOIRQ_ACCESS_DELAY msecs_to_jiffies(2) 32797c0113SAndrey Pronin #define CR50_READY_IRQ_TIMEOUT msecs_to_jiffies(TPM2_TIMEOUT_A) 33797c0113SAndrey Pronin #define CR50_FLOW_CONTROL msecs_to_jiffies(TPM2_TIMEOUT_A) 34797c0113SAndrey Pronin #define MAX_IRQ_CONFIRMATION_ATTEMPTS 3 35797c0113SAndrey Pronin 36797c0113SAndrey Pronin #define TPM_CR50_FW_VER(l) (0x0f90 | ((l) << 12)) 37797c0113SAndrey Pronin #define TPM_CR50_MAX_FW_VER_LEN 64 38797c0113SAndrey Pronin 39d2704808SAngeloGioacchino Del Regno /* Default quality for hwrng. */ 40d2704808SAngeloGioacchino Del Regno #define TPM_CR50_DEFAULT_RNG_QUALITY 700 41d2704808SAngeloGioacchino Del Regno 42797c0113SAndrey Pronin struct cr50_spi_phy { 43797c0113SAndrey Pronin struct tpm_tis_spi_phy spi_phy; 44797c0113SAndrey Pronin 45797c0113SAndrey Pronin struct mutex time_track_mutex; 46797c0113SAndrey Pronin unsigned long last_access; 47797c0113SAndrey Pronin 48797c0113SAndrey Pronin unsigned long access_delay; 49797c0113SAndrey Pronin 50797c0113SAndrey Pronin unsigned int irq_confirmation_attempt; 51797c0113SAndrey Pronin bool irq_needs_confirmation; 52797c0113SAndrey Pronin bool irq_confirmed; 53797c0113SAndrey Pronin }; 54797c0113SAndrey Pronin 55797c0113SAndrey Pronin static inline struct cr50_spi_phy *to_cr50_spi_phy(struct tpm_tis_spi_phy *phy) 56797c0113SAndrey Pronin { 57797c0113SAndrey Pronin return container_of(phy, struct cr50_spi_phy, spi_phy); 58797c0113SAndrey Pronin } 59797c0113SAndrey Pronin 60797c0113SAndrey Pronin /* 61797c0113SAndrey Pronin * The cr50 interrupt handler just signals waiting threads that the 62797c0113SAndrey Pronin * interrupt was asserted. It does not do any processing triggered 63797c0113SAndrey Pronin * by interrupts but is instead used to avoid fixed delays. 64797c0113SAndrey Pronin */ 65797c0113SAndrey Pronin static irqreturn_t cr50_spi_irq_handler(int dummy, void *dev_id) 66797c0113SAndrey Pronin { 67797c0113SAndrey Pronin struct cr50_spi_phy *cr50_phy = dev_id; 68797c0113SAndrey Pronin 69797c0113SAndrey Pronin cr50_phy->irq_confirmed = true; 70797c0113SAndrey Pronin complete(&cr50_phy->spi_phy.ready); 71797c0113SAndrey Pronin 72797c0113SAndrey Pronin return IRQ_HANDLED; 73797c0113SAndrey Pronin } 74797c0113SAndrey Pronin 75797c0113SAndrey Pronin /* 76797c0113SAndrey Pronin * Cr50 needs to have at least some delay between consecutive 77797c0113SAndrey Pronin * transactions. Make sure we wait. 78797c0113SAndrey Pronin */ 79797c0113SAndrey Pronin static void cr50_ensure_access_delay(struct cr50_spi_phy *phy) 80797c0113SAndrey Pronin { 81797c0113SAndrey Pronin unsigned long allowed_access = phy->last_access + phy->access_delay; 82797c0113SAndrey Pronin unsigned long time_now = jiffies; 83797c0113SAndrey Pronin struct device *dev = &phy->spi_phy.spi_device->dev; 84797c0113SAndrey Pronin 85797c0113SAndrey Pronin /* 86797c0113SAndrey Pronin * Note: There is a small chance, if Cr50 is not accessed in a few days, 87797c0113SAndrey Pronin * that time_in_range will not provide the correct result after the wrap 88797c0113SAndrey Pronin * around for jiffies. In this case, we'll have an unneeded short delay, 89797c0113SAndrey Pronin * which is fine. 90797c0113SAndrey Pronin */ 91797c0113SAndrey Pronin if (time_in_range_open(time_now, phy->last_access, allowed_access)) { 92797c0113SAndrey Pronin unsigned long remaining, timeout = allowed_access - time_now; 93797c0113SAndrey Pronin 94797c0113SAndrey Pronin remaining = wait_for_completion_timeout(&phy->spi_phy.ready, 95797c0113SAndrey Pronin timeout); 96797c0113SAndrey Pronin if (!remaining && phy->irq_confirmed) 97797c0113SAndrey Pronin dev_warn(dev, "Timeout waiting for TPM ready IRQ\n"); 98797c0113SAndrey Pronin } 99797c0113SAndrey Pronin 100797c0113SAndrey Pronin if (phy->irq_needs_confirmation) { 101797c0113SAndrey Pronin unsigned int attempt = ++phy->irq_confirmation_attempt; 102797c0113SAndrey Pronin 103797c0113SAndrey Pronin if (phy->irq_confirmed) { 104797c0113SAndrey Pronin phy->irq_needs_confirmation = false; 105797c0113SAndrey Pronin phy->access_delay = CR50_READY_IRQ_TIMEOUT; 106797c0113SAndrey Pronin dev_info(dev, "TPM ready IRQ confirmed on attempt %u\n", 107797c0113SAndrey Pronin attempt); 108797c0113SAndrey Pronin } else if (attempt > MAX_IRQ_CONFIRMATION_ATTEMPTS) { 109797c0113SAndrey Pronin phy->irq_needs_confirmation = false; 110797c0113SAndrey Pronin dev_warn(dev, "IRQ not confirmed - will use delays\n"); 111797c0113SAndrey Pronin } 112797c0113SAndrey Pronin } 113797c0113SAndrey Pronin } 114797c0113SAndrey Pronin 115797c0113SAndrey Pronin /* 116797c0113SAndrey Pronin * Cr50 might go to sleep if there is no SPI activity for some time and 117797c0113SAndrey Pronin * miss the first few bits/bytes on the bus. In such case, wake it up 118797c0113SAndrey Pronin * by asserting CS and give it time to start up. 119797c0113SAndrey Pronin */ 120797c0113SAndrey Pronin static bool cr50_needs_waking(struct cr50_spi_phy *phy) 121797c0113SAndrey Pronin { 122797c0113SAndrey Pronin /* 123797c0113SAndrey Pronin * Note: There is a small chance, if Cr50 is not accessed in a few days, 124797c0113SAndrey Pronin * that time_in_range will not provide the correct result after the wrap 125797c0113SAndrey Pronin * around for jiffies. In this case, we'll probably timeout or read 126797c0113SAndrey Pronin * incorrect value from TPM_STS and just retry the operation. 127797c0113SAndrey Pronin */ 128797c0113SAndrey Pronin return !time_in_range_open(jiffies, phy->last_access, 129797c0113SAndrey Pronin phy->spi_phy.wake_after); 130797c0113SAndrey Pronin } 131797c0113SAndrey Pronin 132797c0113SAndrey Pronin static void cr50_wake_if_needed(struct cr50_spi_phy *cr50_phy) 133797c0113SAndrey Pronin { 134797c0113SAndrey Pronin struct tpm_tis_spi_phy *phy = &cr50_phy->spi_phy; 135797c0113SAndrey Pronin 136797c0113SAndrey Pronin if (cr50_needs_waking(cr50_phy)) { 137797c0113SAndrey Pronin /* Assert CS, wait 1 msec, deassert CS */ 138ac97b06fSSergiu Cuciurean struct spi_transfer spi_cs_wake = { 139ac97b06fSSergiu Cuciurean .delay = { 140ac97b06fSSergiu Cuciurean .value = 1000, 141ac97b06fSSergiu Cuciurean .unit = SPI_DELAY_UNIT_USECS 142ac97b06fSSergiu Cuciurean } 143ac97b06fSSergiu Cuciurean }; 144797c0113SAndrey Pronin 145797c0113SAndrey Pronin spi_sync_transfer(phy->spi_device, &spi_cs_wake, 1); 146797c0113SAndrey Pronin /* Wait for it to fully wake */ 147797c0113SAndrey Pronin usleep_range(CR50_WAKE_START_DELAY_USEC, 148797c0113SAndrey Pronin CR50_WAKE_START_DELAY_USEC * 2); 149797c0113SAndrey Pronin } 150797c0113SAndrey Pronin 151797c0113SAndrey Pronin /* Reset the time when we need to wake Cr50 again */ 152797c0113SAndrey Pronin phy->wake_after = jiffies + msecs_to_jiffies(CR50_SLEEP_DELAY_MSEC); 153797c0113SAndrey Pronin } 154797c0113SAndrey Pronin 155797c0113SAndrey Pronin /* 156797c0113SAndrey Pronin * Flow control: clock the bus and wait for cr50 to set LSB before 157797c0113SAndrey Pronin * sending/receiving data. TCG PTP spec allows it to happen during 158797c0113SAndrey Pronin * the last byte of header, but cr50 never does that in practice, 159797c0113SAndrey Pronin * and earlier versions had a bug when it was set too early, so don't 160797c0113SAndrey Pronin * check for it during header transfer. 161797c0113SAndrey Pronin */ 162797c0113SAndrey Pronin static int cr50_spi_flow_control(struct tpm_tis_spi_phy *phy, 163797c0113SAndrey Pronin struct spi_transfer *spi_xfer) 164797c0113SAndrey Pronin { 165797c0113SAndrey Pronin struct device *dev = &phy->spi_device->dev; 166797c0113SAndrey Pronin unsigned long timeout = jiffies + CR50_FLOW_CONTROL; 167797c0113SAndrey Pronin struct spi_message m; 168797c0113SAndrey Pronin int ret; 169797c0113SAndrey Pronin 170797c0113SAndrey Pronin spi_xfer->len = 1; 171797c0113SAndrey Pronin 172797c0113SAndrey Pronin do { 173797c0113SAndrey Pronin spi_message_init(&m); 174797c0113SAndrey Pronin spi_message_add_tail(spi_xfer, &m); 175797c0113SAndrey Pronin ret = spi_sync_locked(phy->spi_device, &m); 176797c0113SAndrey Pronin if (ret < 0) 177797c0113SAndrey Pronin return ret; 178797c0113SAndrey Pronin 179797c0113SAndrey Pronin if (time_after(jiffies, timeout)) { 180797c0113SAndrey Pronin dev_warn(dev, "Timeout during flow control\n"); 181797c0113SAndrey Pronin return -EBUSY; 182797c0113SAndrey Pronin } 183797c0113SAndrey Pronin } while (!(phy->iobuf[0] & 0x01)); 184797c0113SAndrey Pronin 185797c0113SAndrey Pronin return 0; 186797c0113SAndrey Pronin } 187797c0113SAndrey Pronin 188*5887d7f4SRob Barnes static bool tpm_cr50_spi_is_firmware_power_managed(struct device *dev) 189*5887d7f4SRob Barnes { 190*5887d7f4SRob Barnes u8 val; 191*5887d7f4SRob Barnes int ret; 192*5887d7f4SRob Barnes 193*5887d7f4SRob Barnes /* This flag should default true when the device property is not present */ 194*5887d7f4SRob Barnes ret = device_property_read_u8(dev, "firmware-power-managed", &val); 195*5887d7f4SRob Barnes if (ret) 196*5887d7f4SRob Barnes return true; 197*5887d7f4SRob Barnes 198*5887d7f4SRob Barnes return val; 199*5887d7f4SRob Barnes } 200*5887d7f4SRob Barnes 201797c0113SAndrey Pronin static int tpm_tis_spi_cr50_transfer(struct tpm_tis_data *data, u32 addr, u16 len, 202797c0113SAndrey Pronin u8 *in, const u8 *out) 203797c0113SAndrey Pronin { 204797c0113SAndrey Pronin struct tpm_tis_spi_phy *phy = to_tpm_tis_spi_phy(data); 205797c0113SAndrey Pronin struct cr50_spi_phy *cr50_phy = to_cr50_spi_phy(phy); 206797c0113SAndrey Pronin int ret; 207797c0113SAndrey Pronin 208797c0113SAndrey Pronin mutex_lock(&cr50_phy->time_track_mutex); 209797c0113SAndrey Pronin /* 210797c0113SAndrey Pronin * Do this outside of spi_bus_lock in case cr50 is not the 211797c0113SAndrey Pronin * only device on that spi bus. 212797c0113SAndrey Pronin */ 213797c0113SAndrey Pronin cr50_ensure_access_delay(cr50_phy); 214797c0113SAndrey Pronin cr50_wake_if_needed(cr50_phy); 215797c0113SAndrey Pronin 216797c0113SAndrey Pronin ret = tpm_tis_spi_transfer(data, addr, len, in, out); 217797c0113SAndrey Pronin 218797c0113SAndrey Pronin cr50_phy->last_access = jiffies; 219797c0113SAndrey Pronin mutex_unlock(&cr50_phy->time_track_mutex); 220797c0113SAndrey Pronin 221797c0113SAndrey Pronin return ret; 222797c0113SAndrey Pronin } 223797c0113SAndrey Pronin 224797c0113SAndrey Pronin static int tpm_tis_spi_cr50_read_bytes(struct tpm_tis_data *data, u32 addr, 225797c0113SAndrey Pronin u16 len, u8 *result) 226797c0113SAndrey Pronin { 227797c0113SAndrey Pronin return tpm_tis_spi_cr50_transfer(data, addr, len, result, NULL); 228797c0113SAndrey Pronin } 229797c0113SAndrey Pronin 230797c0113SAndrey Pronin static int tpm_tis_spi_cr50_write_bytes(struct tpm_tis_data *data, u32 addr, 231797c0113SAndrey Pronin u16 len, const u8 *value) 232797c0113SAndrey Pronin { 233797c0113SAndrey Pronin return tpm_tis_spi_cr50_transfer(data, addr, len, NULL, value); 234797c0113SAndrey Pronin } 235797c0113SAndrey Pronin 236797c0113SAndrey Pronin static const struct tpm_tis_phy_ops tpm_spi_cr50_phy_ops = { 237797c0113SAndrey Pronin .read_bytes = tpm_tis_spi_cr50_read_bytes, 238797c0113SAndrey Pronin .write_bytes = tpm_tis_spi_cr50_write_bytes, 239797c0113SAndrey Pronin .read16 = tpm_tis_spi_read16, 240797c0113SAndrey Pronin .read32 = tpm_tis_spi_read32, 241797c0113SAndrey Pronin .write32 = tpm_tis_spi_write32, 242797c0113SAndrey Pronin }; 243797c0113SAndrey Pronin 244797c0113SAndrey Pronin static void cr50_print_fw_version(struct tpm_tis_data *data) 245797c0113SAndrey Pronin { 246797c0113SAndrey Pronin struct tpm_tis_spi_phy *phy = to_tpm_tis_spi_phy(data); 247797c0113SAndrey Pronin int i, len = 0; 248797c0113SAndrey Pronin char fw_ver[TPM_CR50_MAX_FW_VER_LEN + 1]; 249797c0113SAndrey Pronin char fw_ver_block[4]; 250797c0113SAndrey Pronin 251797c0113SAndrey Pronin /* 252797c0113SAndrey Pronin * Write anything to TPM_CR50_FW_VER to start from the beginning 253797c0113SAndrey Pronin * of the version string 254797c0113SAndrey Pronin */ 255797c0113SAndrey Pronin tpm_tis_write8(data, TPM_CR50_FW_VER(data->locality), 0); 256797c0113SAndrey Pronin 257797c0113SAndrey Pronin /* Read the string, 4 bytes at a time, until we get '\0' */ 258797c0113SAndrey Pronin do { 259797c0113SAndrey Pronin tpm_tis_read_bytes(data, TPM_CR50_FW_VER(data->locality), 4, 260797c0113SAndrey Pronin fw_ver_block); 261797c0113SAndrey Pronin for (i = 0; i < 4 && fw_ver_block[i]; ++len, ++i) 262797c0113SAndrey Pronin fw_ver[len] = fw_ver_block[i]; 263797c0113SAndrey Pronin } while (i == 4 && len < TPM_CR50_MAX_FW_VER_LEN); 264797c0113SAndrey Pronin fw_ver[len] = '\0'; 265797c0113SAndrey Pronin 266797c0113SAndrey Pronin dev_info(&phy->spi_device->dev, "Cr50 firmware version: %s\n", fw_ver); 267797c0113SAndrey Pronin } 268797c0113SAndrey Pronin 269797c0113SAndrey Pronin int cr50_spi_probe(struct spi_device *spi) 270797c0113SAndrey Pronin { 271797c0113SAndrey Pronin struct tpm_tis_spi_phy *phy; 272797c0113SAndrey Pronin struct cr50_spi_phy *cr50_phy; 273797c0113SAndrey Pronin int ret; 274797c0113SAndrey Pronin struct tpm_chip *chip; 275797c0113SAndrey Pronin 276797c0113SAndrey Pronin cr50_phy = devm_kzalloc(&spi->dev, sizeof(*cr50_phy), GFP_KERNEL); 277797c0113SAndrey Pronin if (!cr50_phy) 278797c0113SAndrey Pronin return -ENOMEM; 279797c0113SAndrey Pronin 280797c0113SAndrey Pronin phy = &cr50_phy->spi_phy; 281797c0113SAndrey Pronin phy->flow_control = cr50_spi_flow_control; 282797c0113SAndrey Pronin phy->wake_after = jiffies; 283d2704808SAngeloGioacchino Del Regno phy->priv.rng_quality = TPM_CR50_DEFAULT_RNG_QUALITY; 284797c0113SAndrey Pronin init_completion(&phy->ready); 285797c0113SAndrey Pronin 286797c0113SAndrey Pronin cr50_phy->access_delay = CR50_NOIRQ_ACCESS_DELAY; 287797c0113SAndrey Pronin cr50_phy->last_access = jiffies; 288797c0113SAndrey Pronin mutex_init(&cr50_phy->time_track_mutex); 289797c0113SAndrey Pronin 290797c0113SAndrey Pronin if (spi->irq > 0) { 291797c0113SAndrey Pronin ret = devm_request_irq(&spi->dev, spi->irq, 292797c0113SAndrey Pronin cr50_spi_irq_handler, 293797c0113SAndrey Pronin IRQF_TRIGGER_RISING | IRQF_ONESHOT, 294797c0113SAndrey Pronin "cr50_spi", cr50_phy); 295797c0113SAndrey Pronin if (ret < 0) { 296797c0113SAndrey Pronin if (ret == -EPROBE_DEFER) 297797c0113SAndrey Pronin return ret; 298797c0113SAndrey Pronin dev_warn(&spi->dev, "Requesting IRQ %d failed: %d\n", 299797c0113SAndrey Pronin spi->irq, ret); 300797c0113SAndrey Pronin /* 301797c0113SAndrey Pronin * This is not fatal, the driver will fall back to 302797c0113SAndrey Pronin * delays automatically, since ready will never 303797c0113SAndrey Pronin * be completed without a registered irq handler. 304797c0113SAndrey Pronin * So, just fall through. 305797c0113SAndrey Pronin */ 306797c0113SAndrey Pronin } else { 307797c0113SAndrey Pronin /* 308797c0113SAndrey Pronin * IRQ requested, let's verify that it is actually 309797c0113SAndrey Pronin * triggered, before relying on it. 310797c0113SAndrey Pronin */ 311797c0113SAndrey Pronin cr50_phy->irq_needs_confirmation = true; 312797c0113SAndrey Pronin } 313797c0113SAndrey Pronin } else { 314797c0113SAndrey Pronin dev_warn(&spi->dev, 315797c0113SAndrey Pronin "No IRQ - will use delays between transactions.\n"); 316797c0113SAndrey Pronin } 317797c0113SAndrey Pronin 318797c0113SAndrey Pronin ret = tpm_tis_spi_init(spi, phy, -1, &tpm_spi_cr50_phy_ops); 319797c0113SAndrey Pronin if (ret) 320797c0113SAndrey Pronin return ret; 321797c0113SAndrey Pronin 322797c0113SAndrey Pronin cr50_print_fw_version(&phy->priv); 323797c0113SAndrey Pronin 324797c0113SAndrey Pronin chip = dev_get_drvdata(&spi->dev); 325*5887d7f4SRob Barnes if (tpm_cr50_spi_is_firmware_power_managed(&spi->dev)) 326797c0113SAndrey Pronin chip->flags |= TPM_CHIP_FLAG_FIRMWARE_POWER_MANAGED; 327797c0113SAndrey Pronin 328797c0113SAndrey Pronin return 0; 329797c0113SAndrey Pronin } 330797c0113SAndrey Pronin 331797c0113SAndrey Pronin #ifdef CONFIG_PM_SLEEP 332797c0113SAndrey Pronin int tpm_tis_spi_resume(struct device *dev) 333797c0113SAndrey Pronin { 334797c0113SAndrey Pronin struct tpm_chip *chip = dev_get_drvdata(dev); 335797c0113SAndrey Pronin struct tpm_tis_data *data = dev_get_drvdata(&chip->dev); 336797c0113SAndrey Pronin struct tpm_tis_spi_phy *phy = to_tpm_tis_spi_phy(data); 337797c0113SAndrey Pronin /* 338797c0113SAndrey Pronin * Jiffies not increased during suspend, so we need to reset 339797c0113SAndrey Pronin * the time to wake Cr50 after resume. 340797c0113SAndrey Pronin */ 341797c0113SAndrey Pronin phy->wake_after = jiffies; 342797c0113SAndrey Pronin 343797c0113SAndrey Pronin return tpm_tis_resume(dev); 344797c0113SAndrey Pronin } 345797c0113SAndrey Pronin #endif 346