1 /* 2 * Copyright (C) 2004 IBM Corporation 3 * 4 * Authors: 5 * Leendert van Doorn <leendert@watson.ibm.com> 6 * Dave Safford <safford@watson.ibm.com> 7 * Reiner Sailer <sailer@watson.ibm.com> 8 * Kylene Hall <kjhall@us.ibm.com> 9 * 10 * Maintained by: <tpmdd-devel@lists.sourceforge.net> 11 * 12 * Device driver for TCG/TCPA TPM (trusted platform module). 13 * Specifications at www.trustedcomputinggroup.org 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation, version 2 of the 18 * License. 19 * 20 */ 21 22 #include <linux/platform_device.h> 23 #include <linux/slab.h> 24 #include "tpm.h" 25 26 /* National definitions */ 27 enum tpm_nsc_addr{ 28 TPM_NSC_IRQ = 0x07, 29 TPM_NSC_BASE0_HI = 0x60, 30 TPM_NSC_BASE0_LO = 0x61, 31 TPM_NSC_BASE1_HI = 0x62, 32 TPM_NSC_BASE1_LO = 0x63 33 }; 34 35 enum tpm_nsc_index { 36 NSC_LDN_INDEX = 0x07, 37 NSC_SID_INDEX = 0x20, 38 NSC_LDC_INDEX = 0x30, 39 NSC_DIO_INDEX = 0x60, 40 NSC_CIO_INDEX = 0x62, 41 NSC_IRQ_INDEX = 0x70, 42 NSC_ITS_INDEX = 0x71 43 }; 44 45 enum tpm_nsc_status_loc { 46 NSC_STATUS = 0x01, 47 NSC_COMMAND = 0x01, 48 NSC_DATA = 0x00 49 }; 50 51 /* status bits */ 52 enum tpm_nsc_status { 53 NSC_STATUS_OBF = 0x01, /* output buffer full */ 54 NSC_STATUS_IBF = 0x02, /* input buffer full */ 55 NSC_STATUS_F0 = 0x04, /* F0 */ 56 NSC_STATUS_A2 = 0x08, /* A2 */ 57 NSC_STATUS_RDY = 0x10, /* ready to receive command */ 58 NSC_STATUS_IBR = 0x20 /* ready to receive data */ 59 }; 60 61 /* command bits */ 62 enum tpm_nsc_cmd_mode { 63 NSC_COMMAND_NORMAL = 0x01, /* normal mode */ 64 NSC_COMMAND_EOC = 0x03, 65 NSC_COMMAND_CANCEL = 0x22 66 }; 67 68 struct tpm_nsc_priv { 69 unsigned long base; 70 }; 71 72 /* 73 * Wait for a certain status to appear 74 */ 75 static int wait_for_stat(struct tpm_chip *chip, u8 mask, u8 val, u8 * data) 76 { 77 struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev); 78 unsigned long stop; 79 80 /* status immediately available check */ 81 *data = inb(priv->base + NSC_STATUS); 82 if ((*data & mask) == val) 83 return 0; 84 85 /* wait for status */ 86 stop = jiffies + 10 * HZ; 87 do { 88 msleep(TPM_TIMEOUT); 89 *data = inb(priv->base + 1); 90 if ((*data & mask) == val) 91 return 0; 92 } 93 while (time_before(jiffies, stop)); 94 95 return -EBUSY; 96 } 97 98 static int nsc_wait_for_ready(struct tpm_chip *chip) 99 { 100 struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev); 101 int status; 102 unsigned long stop; 103 104 /* status immediately available check */ 105 status = inb(priv->base + NSC_STATUS); 106 if (status & NSC_STATUS_OBF) 107 status = inb(priv->base + NSC_DATA); 108 if (status & NSC_STATUS_RDY) 109 return 0; 110 111 /* wait for status */ 112 stop = jiffies + 100; 113 do { 114 msleep(TPM_TIMEOUT); 115 status = inb(priv->base + NSC_STATUS); 116 if (status & NSC_STATUS_OBF) 117 status = inb(priv->base + NSC_DATA); 118 if (status & NSC_STATUS_RDY) 119 return 0; 120 } 121 while (time_before(jiffies, stop)); 122 123 dev_info(&chip->dev, "wait for ready failed\n"); 124 return -EBUSY; 125 } 126 127 128 static int tpm_nsc_recv(struct tpm_chip *chip, u8 * buf, size_t count) 129 { 130 struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev); 131 u8 *buffer = buf; 132 u8 data, *p; 133 u32 size; 134 __be32 *native_size; 135 136 if (count < 6) 137 return -EIO; 138 139 if (wait_for_stat(chip, NSC_STATUS_F0, NSC_STATUS_F0, &data) < 0) { 140 dev_err(&chip->dev, "F0 timeout\n"); 141 return -EIO; 142 } 143 144 data = inb(priv->base + NSC_DATA); 145 if (data != NSC_COMMAND_NORMAL) { 146 dev_err(&chip->dev, "not in normal mode (0x%x)\n", 147 data); 148 return -EIO; 149 } 150 151 /* read the whole packet */ 152 for (p = buffer; p < &buffer[count]; p++) { 153 if (wait_for_stat 154 (chip, NSC_STATUS_OBF, NSC_STATUS_OBF, &data) < 0) { 155 dev_err(&chip->dev, 156 "OBF timeout (while reading data)\n"); 157 return -EIO; 158 } 159 if (data & NSC_STATUS_F0) 160 break; 161 *p = inb(priv->base + NSC_DATA); 162 } 163 164 if ((data & NSC_STATUS_F0) == 0 && 165 (wait_for_stat(chip, NSC_STATUS_F0, NSC_STATUS_F0, &data) < 0)) { 166 dev_err(&chip->dev, "F0 not set\n"); 167 return -EIO; 168 } 169 170 data = inb(priv->base + NSC_DATA); 171 if (data != NSC_COMMAND_EOC) { 172 dev_err(&chip->dev, 173 "expected end of command(0x%x)\n", data); 174 return -EIO; 175 } 176 177 native_size = (__force __be32 *) (buf + 2); 178 size = be32_to_cpu(*native_size); 179 180 if (count < size) 181 return -EIO; 182 183 return size; 184 } 185 186 static int tpm_nsc_send(struct tpm_chip *chip, u8 * buf, size_t count) 187 { 188 struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev); 189 u8 data; 190 int i; 191 192 /* 193 * If we hit the chip with back to back commands it locks up 194 * and never set IBF. Hitting it with this "hammer" seems to 195 * fix it. Not sure why this is needed, we followed the flow 196 * chart in the manual to the letter. 197 */ 198 outb(NSC_COMMAND_CANCEL, priv->base + NSC_COMMAND); 199 200 if (nsc_wait_for_ready(chip) != 0) 201 return -EIO; 202 203 if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) { 204 dev_err(&chip->dev, "IBF timeout\n"); 205 return -EIO; 206 } 207 208 outb(NSC_COMMAND_NORMAL, priv->base + NSC_COMMAND); 209 if (wait_for_stat(chip, NSC_STATUS_IBR, NSC_STATUS_IBR, &data) < 0) { 210 dev_err(&chip->dev, "IBR timeout\n"); 211 return -EIO; 212 } 213 214 for (i = 0; i < count; i++) { 215 if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) { 216 dev_err(&chip->dev, 217 "IBF timeout (while writing data)\n"); 218 return -EIO; 219 } 220 outb(buf[i], priv->base + NSC_DATA); 221 } 222 223 if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) { 224 dev_err(&chip->dev, "IBF timeout\n"); 225 return -EIO; 226 } 227 outb(NSC_COMMAND_EOC, priv->base + NSC_COMMAND); 228 229 return count; 230 } 231 232 static void tpm_nsc_cancel(struct tpm_chip *chip) 233 { 234 struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev); 235 236 outb(NSC_COMMAND_CANCEL, priv->base + NSC_COMMAND); 237 } 238 239 static u8 tpm_nsc_status(struct tpm_chip *chip) 240 { 241 struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev); 242 243 return inb(priv->base + NSC_STATUS); 244 } 245 246 static bool tpm_nsc_req_canceled(struct tpm_chip *chip, u8 status) 247 { 248 return (status == NSC_STATUS_RDY); 249 } 250 251 static const struct tpm_class_ops tpm_nsc = { 252 .recv = tpm_nsc_recv, 253 .send = tpm_nsc_send, 254 .cancel = tpm_nsc_cancel, 255 .status = tpm_nsc_status, 256 .req_complete_mask = NSC_STATUS_OBF, 257 .req_complete_val = NSC_STATUS_OBF, 258 .req_canceled = tpm_nsc_req_canceled, 259 }; 260 261 static struct platform_device *pdev = NULL; 262 263 static void tpm_nsc_remove(struct device *dev) 264 { 265 struct tpm_chip *chip = dev_get_drvdata(dev); 266 struct tpm_nsc_priv *priv = dev_get_drvdata(&chip->dev); 267 268 tpm_chip_unregister(chip); 269 release_region(priv->base, 2); 270 } 271 272 static SIMPLE_DEV_PM_OPS(tpm_nsc_pm, tpm_pm_suspend, tpm_pm_resume); 273 274 static struct platform_driver nsc_drv = { 275 .driver = { 276 .name = "tpm_nsc", 277 .pm = &tpm_nsc_pm, 278 }, 279 }; 280 281 static inline int tpm_read_index(int base, int index) 282 { 283 outb(index, base); 284 return inb(base+1) & 0xFF; 285 } 286 287 static inline void tpm_write_index(int base, int index, int value) 288 { 289 outb(index, base); 290 outb(value & 0xFF, base+1); 291 } 292 293 static int __init init_nsc(void) 294 { 295 int rc = 0; 296 int lo, hi, err; 297 int nscAddrBase = TPM_ADDR; 298 struct tpm_chip *chip; 299 unsigned long base; 300 struct tpm_nsc_priv *priv; 301 302 /* verify that it is a National part (SID) */ 303 if (tpm_read_index(TPM_ADDR, NSC_SID_INDEX) != 0xEF) { 304 nscAddrBase = (tpm_read_index(TPM_SUPERIO_ADDR, 0x2C)<<8)| 305 (tpm_read_index(TPM_SUPERIO_ADDR, 0x2B)&0xFE); 306 if (tpm_read_index(nscAddrBase, NSC_SID_INDEX) != 0xF6) 307 return -ENODEV; 308 } 309 310 err = platform_driver_register(&nsc_drv); 311 if (err) 312 return err; 313 314 hi = tpm_read_index(nscAddrBase, TPM_NSC_BASE0_HI); 315 lo = tpm_read_index(nscAddrBase, TPM_NSC_BASE0_LO); 316 base = (hi<<8) | lo; 317 318 /* enable the DPM module */ 319 tpm_write_index(nscAddrBase, NSC_LDC_INDEX, 0x01); 320 321 pdev = platform_device_alloc("tpm_nscl0", -1); 322 if (!pdev) { 323 rc = -ENOMEM; 324 goto err_unreg_drv; 325 } 326 327 pdev->num_resources = 0; 328 pdev->dev.driver = &nsc_drv.driver; 329 pdev->dev.release = tpm_nsc_remove; 330 331 if ((rc = platform_device_add(pdev)) < 0) 332 goto err_put_dev; 333 334 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 335 if (!priv) { 336 rc = -ENOMEM; 337 goto err_del_dev; 338 } 339 340 priv->base = base; 341 342 if (request_region(base, 2, "tpm_nsc0") == NULL ) { 343 rc = -EBUSY; 344 goto err_del_dev; 345 } 346 347 chip = tpmm_chip_alloc(&pdev->dev, &tpm_nsc); 348 if (IS_ERR(chip)) { 349 rc = -ENODEV; 350 goto err_rel_reg; 351 } 352 353 dev_set_drvdata(&chip->dev, priv); 354 355 rc = tpm_chip_register(chip); 356 if (rc) 357 goto err_rel_reg; 358 359 dev_dbg(&pdev->dev, "NSC TPM detected\n"); 360 dev_dbg(&pdev->dev, 361 "NSC LDN 0x%x, SID 0x%x, SRID 0x%x\n", 362 tpm_read_index(nscAddrBase,0x07), tpm_read_index(nscAddrBase,0x20), 363 tpm_read_index(nscAddrBase,0x27)); 364 dev_dbg(&pdev->dev, 365 "NSC SIOCF1 0x%x SIOCF5 0x%x SIOCF6 0x%x SIOCF8 0x%x\n", 366 tpm_read_index(nscAddrBase,0x21), tpm_read_index(nscAddrBase,0x25), 367 tpm_read_index(nscAddrBase,0x26), tpm_read_index(nscAddrBase,0x28)); 368 dev_dbg(&pdev->dev, "NSC IO Base0 0x%x\n", 369 (tpm_read_index(nscAddrBase,0x60) << 8) | tpm_read_index(nscAddrBase,0x61)); 370 dev_dbg(&pdev->dev, "NSC IO Base1 0x%x\n", 371 (tpm_read_index(nscAddrBase,0x62) << 8) | tpm_read_index(nscAddrBase,0x63)); 372 dev_dbg(&pdev->dev, "NSC Interrupt number and wakeup 0x%x\n", 373 tpm_read_index(nscAddrBase,0x70)); 374 dev_dbg(&pdev->dev, "NSC IRQ type select 0x%x\n", 375 tpm_read_index(nscAddrBase,0x71)); 376 dev_dbg(&pdev->dev, 377 "NSC DMA channel select0 0x%x, select1 0x%x\n", 378 tpm_read_index(nscAddrBase,0x74), tpm_read_index(nscAddrBase,0x75)); 379 dev_dbg(&pdev->dev, 380 "NSC Config " 381 "0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 382 tpm_read_index(nscAddrBase,0xF0), tpm_read_index(nscAddrBase,0xF1), 383 tpm_read_index(nscAddrBase,0xF2), tpm_read_index(nscAddrBase,0xF3), 384 tpm_read_index(nscAddrBase,0xF4), tpm_read_index(nscAddrBase,0xF5), 385 tpm_read_index(nscAddrBase,0xF6), tpm_read_index(nscAddrBase,0xF7), 386 tpm_read_index(nscAddrBase,0xF8), tpm_read_index(nscAddrBase,0xF9)); 387 388 dev_info(&pdev->dev, 389 "NSC TPM revision %d\n", 390 tpm_read_index(nscAddrBase, 0x27) & 0x1F); 391 392 return 0; 393 394 err_rel_reg: 395 release_region(base, 2); 396 err_del_dev: 397 platform_device_del(pdev); 398 err_put_dev: 399 platform_device_put(pdev); 400 err_unreg_drv: 401 platform_driver_unregister(&nsc_drv); 402 return rc; 403 } 404 405 static void __exit cleanup_nsc(void) 406 { 407 if (pdev) { 408 tpm_nsc_remove(&pdev->dev); 409 platform_device_unregister(pdev); 410 } 411 412 platform_driver_unregister(&nsc_drv); 413 } 414 415 module_init(init_nsc); 416 module_exit(cleanup_nsc); 417 418 MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)"); 419 MODULE_DESCRIPTION("TPM Driver"); 420 MODULE_VERSION("2.0"); 421 MODULE_LICENSE("GPL"); 422