1 /*
2  * APM X-Gene SoC RNG Driver
3  *
4  * Copyright (c) 2014, Applied Micro Circuits Corporation
5  * Author: Rameshwar Prasad Sahu <rsahu@apm.com>
6  *	   Shamal Winchurkar <swinchurkar@apm.com>
7  *	   Feng Kan <fkan@apm.com>
8  *
9  * This program is free software; you can redistribute  it and/or modify it
10  * under  the terms of  the GNU General  Public License as published by the
11  * Free Software Foundation;  either version 2 of the  License, or (at your
12  * option) any later version.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
21  *
22  */
23 
24 #include <linux/acpi.h>
25 #include <linux/clk.h>
26 #include <linux/delay.h>
27 #include <linux/hw_random.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/module.h>
31 #include <linux/of_platform.h>
32 #include <linux/of_irq.h>
33 #include <linux/of_address.h>
34 #include <linux/timer.h>
35 
36 #define RNG_MAX_DATUM			4
37 #define MAX_TRY				100
38 #define XGENE_RNG_RETRY_COUNT		20
39 #define XGENE_RNG_RETRY_INTERVAL	10
40 
41 /* RNG  Registers */
42 #define RNG_INOUT_0			0x00
43 #define RNG_INTR_STS_ACK		0x10
44 #define RNG_CONTROL			0x14
45 #define RNG_CONFIG			0x18
46 #define RNG_ALARMCNT			0x1c
47 #define RNG_FROENABLE			0x20
48 #define RNG_FRODETUNE			0x24
49 #define RNG_ALARMMASK			0x28
50 #define RNG_ALARMSTOP			0x2c
51 #define RNG_OPTIONS			0x78
52 #define RNG_EIP_REV			0x7c
53 
54 #define MONOBIT_FAIL_MASK		BIT(7)
55 #define POKER_FAIL_MASK			BIT(6)
56 #define LONG_RUN_FAIL_MASK		BIT(5)
57 #define RUN_FAIL_MASK			BIT(4)
58 #define NOISE_FAIL_MASK			BIT(3)
59 #define STUCK_OUT_MASK			BIT(2)
60 #define SHUTDOWN_OFLO_MASK		BIT(1)
61 #define READY_MASK			BIT(0)
62 
63 #define MAJOR_HW_REV_RD(src)		(((src) & 0x0f000000) >> 24)
64 #define MINOR_HW_REV_RD(src)		(((src) & 0x00f00000) >> 20)
65 #define HW_PATCH_LEVEL_RD(src)		(((src) & 0x000f0000) >> 16)
66 #define MAX_REFILL_CYCLES_SET(dst, src) \
67 			((dst & ~0xffff0000) | (((u32)src << 16) & 0xffff0000))
68 #define MIN_REFILL_CYCLES_SET(dst, src) \
69 			((dst & ~0x000000ff) | (((u32)src) & 0x000000ff))
70 #define ALARM_THRESHOLD_SET(dst, src) \
71 			((dst & ~0x000000ff) | (((u32)src) & 0x000000ff))
72 #define ENABLE_RNG_SET(dst, src) \
73 			((dst & ~BIT(10)) | (((u32)src << 10) & BIT(10)))
74 #define REGSPEC_TEST_MODE_SET(dst, src) \
75 			((dst & ~BIT(8)) | (((u32)src << 8) & BIT(8)))
76 #define MONOBIT_FAIL_MASK_SET(dst, src) \
77 			((dst & ~BIT(7)) | (((u32)src << 7) & BIT(7)))
78 #define POKER_FAIL_MASK_SET(dst, src) \
79 			((dst & ~BIT(6)) | (((u32)src << 6) & BIT(6)))
80 #define LONG_RUN_FAIL_MASK_SET(dst, src) \
81 			((dst & ~BIT(5)) | (((u32)src << 5) & BIT(5)))
82 #define RUN_FAIL_MASK_SET(dst, src) \
83 			((dst & ~BIT(4)) | (((u32)src << 4) & BIT(4)))
84 #define NOISE_FAIL_MASK_SET(dst, src) \
85 			((dst & ~BIT(3)) | (((u32)src << 3) & BIT(3)))
86 #define STUCK_OUT_MASK_SET(dst, src) \
87 			((dst & ~BIT(2)) | (((u32)src << 2) & BIT(2)))
88 #define SHUTDOWN_OFLO_MASK_SET(dst, src) \
89 			((dst & ~BIT(1)) | (((u32)src << 1) & BIT(1)))
90 
91 struct xgene_rng_dev {
92 	u32 irq;
93 	void  __iomem *csr_base;
94 	u32 revision;
95 	u32 datum_size;
96 	u32 failure_cnt;	/* Failure count last minute */
97 	unsigned long failure_ts;/* First failure timestamp */
98 	struct timer_list failure_timer;
99 	struct device *dev;
100 	struct clk *clk;
101 };
102 
103 static void xgene_rng_expired_timer(unsigned long arg)
104 {
105 	struct xgene_rng_dev *ctx = (struct xgene_rng_dev *) arg;
106 
107 	/* Clear failure counter as timer expired */
108 	disable_irq(ctx->irq);
109 	ctx->failure_cnt = 0;
110 	del_timer(&ctx->failure_timer);
111 	enable_irq(ctx->irq);
112 }
113 
114 static void xgene_rng_start_timer(struct xgene_rng_dev *ctx)
115 {
116 	ctx->failure_timer.data = (unsigned long) ctx;
117 	ctx->failure_timer.function = xgene_rng_expired_timer;
118 	ctx->failure_timer.expires = jiffies + 120 * HZ;
119 	add_timer(&ctx->failure_timer);
120 }
121 
122 /*
123  * Initialize or reinit free running oscillators (FROs)
124  */
125 static void xgene_rng_init_fro(struct xgene_rng_dev *ctx, u32 fro_val)
126 {
127 	writel(fro_val, ctx->csr_base + RNG_FRODETUNE);
128 	writel(0x00000000, ctx->csr_base + RNG_ALARMMASK);
129 	writel(0x00000000, ctx->csr_base + RNG_ALARMSTOP);
130 	writel(0xFFFFFFFF, ctx->csr_base + RNG_FROENABLE);
131 }
132 
133 static void xgene_rng_chk_overflow(struct xgene_rng_dev *ctx)
134 {
135 	u32 val;
136 
137 	val = readl(ctx->csr_base + RNG_INTR_STS_ACK);
138 	if (val & MONOBIT_FAIL_MASK)
139 		/*
140 		 * LFSR detected an out-of-bounds number of 1s after
141 		 * checking 20,000 bits (test T1 as specified in the
142 		 * AIS-31 standard)
143 		 */
144 		dev_err(ctx->dev, "test monobit failure error 0x%08X\n", val);
145 	if (val & POKER_FAIL_MASK)
146 		/*
147 		 * LFSR detected an out-of-bounds value in at least one
148 		 * of the 16 poker_count_X counters or an out of bounds sum
149 		 * of squares value after checking 20,000 bits (test T2 as
150 		 * specified in the AIS-31 standard)
151 		 */
152 		dev_err(ctx->dev, "test poker failure error 0x%08X\n", val);
153 	if (val & LONG_RUN_FAIL_MASK)
154 		/*
155 		 * LFSR detected a sequence of 34 identical bits
156 		 * (test T4 as specified in the AIS-31 standard)
157 		 */
158 		dev_err(ctx->dev, "test long run failure error 0x%08X\n", val);
159 	if (val & RUN_FAIL_MASK)
160 		/*
161 		 * LFSR detected an outof-bounds value for at least one
162 		 * of the running counters after checking 20,000 bits
163 		 * (test T3 as specified in the AIS-31 standard)
164 		 */
165 		dev_err(ctx->dev, "test run failure error 0x%08X\n", val);
166 	if (val & NOISE_FAIL_MASK)
167 		/* LFSR detected a sequence of 48 identical bits */
168 		dev_err(ctx->dev, "noise failure error 0x%08X\n", val);
169 	if (val & STUCK_OUT_MASK)
170 		/*
171 		 * Detected output data registers generated same value twice
172 		 * in a row
173 		 */
174 		dev_err(ctx->dev, "stuck out failure error 0x%08X\n", val);
175 
176 	if (val & SHUTDOWN_OFLO_MASK) {
177 		u32 frostopped;
178 
179 		/* FROs shut down after a second error event. Try recover. */
180 		if (++ctx->failure_cnt == 1) {
181 			/* 1st time, just recover */
182 			ctx->failure_ts = jiffies;
183 			frostopped = readl(ctx->csr_base + RNG_ALARMSTOP);
184 			xgene_rng_init_fro(ctx, frostopped);
185 
186 			/*
187 			 * We must start a timer to clear out this error
188 			 * in case the system timer wrap around
189 			 */
190 			xgene_rng_start_timer(ctx);
191 		} else {
192 			/* 2nd time failure in lesser than 1 minute? */
193 			if (time_after(ctx->failure_ts + 60 * HZ, jiffies)) {
194 				dev_err(ctx->dev,
195 					"FRO shutdown failure error 0x%08X\n",
196 					val);
197 			} else {
198 				/* 2nd time failure after 1 minutes, recover */
199 				ctx->failure_ts = jiffies;
200 				ctx->failure_cnt = 1;
201 				/*
202 				 * We must start a timer to clear out this
203 				 * error in case the system timer wrap
204 				 * around
205 				 */
206 				xgene_rng_start_timer(ctx);
207 			}
208 			frostopped = readl(ctx->csr_base + RNG_ALARMSTOP);
209 			xgene_rng_init_fro(ctx, frostopped);
210 		}
211 	}
212 	/* Clear them all */
213 	writel(val, ctx->csr_base + RNG_INTR_STS_ACK);
214 }
215 
216 static irqreturn_t xgene_rng_irq_handler(int irq, void *id)
217 {
218 	struct xgene_rng_dev *ctx = (struct xgene_rng_dev *) id;
219 
220 	/* RNG Alarm Counter overflow */
221 	xgene_rng_chk_overflow(ctx);
222 
223 	return IRQ_HANDLED;
224 }
225 
226 static int xgene_rng_data_present(struct hwrng *rng, int wait)
227 {
228 	struct xgene_rng_dev *ctx = (struct xgene_rng_dev *) rng->priv;
229 	u32 i, val = 0;
230 
231 	for (i = 0; i < XGENE_RNG_RETRY_COUNT; i++) {
232 		val = readl(ctx->csr_base + RNG_INTR_STS_ACK);
233 		if ((val & READY_MASK) || !wait)
234 			break;
235 		udelay(XGENE_RNG_RETRY_INTERVAL);
236 	}
237 
238 	return (val & READY_MASK);
239 }
240 
241 static int xgene_rng_data_read(struct hwrng *rng, u32 *data)
242 {
243 	struct xgene_rng_dev *ctx = (struct xgene_rng_dev *) rng->priv;
244 	int i;
245 
246 	for (i = 0; i < ctx->datum_size; i++)
247 		data[i] = readl(ctx->csr_base + RNG_INOUT_0 + i * 4);
248 
249 	/* Clear ready bit to start next transaction */
250 	writel(READY_MASK, ctx->csr_base + RNG_INTR_STS_ACK);
251 
252 	return ctx->datum_size << 2;
253 }
254 
255 static void xgene_rng_init_internal(struct xgene_rng_dev *ctx)
256 {
257 	u32 val;
258 
259 	writel(0x00000000, ctx->csr_base + RNG_CONTROL);
260 
261 	val = MAX_REFILL_CYCLES_SET(0, 10);
262 	val = MIN_REFILL_CYCLES_SET(val, 10);
263 	writel(val, ctx->csr_base + RNG_CONFIG);
264 
265 	val = ALARM_THRESHOLD_SET(0, 0xFF);
266 	writel(val, ctx->csr_base + RNG_ALARMCNT);
267 
268 	xgene_rng_init_fro(ctx, 0);
269 
270 	writel(MONOBIT_FAIL_MASK |
271 		POKER_FAIL_MASK	|
272 		LONG_RUN_FAIL_MASK |
273 		RUN_FAIL_MASK |
274 		NOISE_FAIL_MASK |
275 		STUCK_OUT_MASK |
276 		SHUTDOWN_OFLO_MASK |
277 		READY_MASK, ctx->csr_base + RNG_INTR_STS_ACK);
278 
279 	val = ENABLE_RNG_SET(0, 1);
280 	val = MONOBIT_FAIL_MASK_SET(val, 1);
281 	val = POKER_FAIL_MASK_SET(val, 1);
282 	val = LONG_RUN_FAIL_MASK_SET(val, 1);
283 	val = RUN_FAIL_MASK_SET(val, 1);
284 	val = NOISE_FAIL_MASK_SET(val, 1);
285 	val = STUCK_OUT_MASK_SET(val, 1);
286 	val = SHUTDOWN_OFLO_MASK_SET(val, 1);
287 	writel(val, ctx->csr_base + RNG_CONTROL);
288 }
289 
290 static int xgene_rng_init(struct hwrng *rng)
291 {
292 	struct xgene_rng_dev *ctx = (struct xgene_rng_dev *) rng->priv;
293 
294 	ctx->failure_cnt = 0;
295 	init_timer(&ctx->failure_timer);
296 
297 	ctx->revision = readl(ctx->csr_base + RNG_EIP_REV);
298 
299 	dev_dbg(ctx->dev, "Rev %d.%d.%d\n",
300 		MAJOR_HW_REV_RD(ctx->revision),
301 		MINOR_HW_REV_RD(ctx->revision),
302 		HW_PATCH_LEVEL_RD(ctx->revision));
303 
304 	dev_dbg(ctx->dev, "Options 0x%08X",
305 		readl(ctx->csr_base + RNG_OPTIONS));
306 
307 	xgene_rng_init_internal(ctx);
308 
309 	ctx->datum_size = RNG_MAX_DATUM;
310 
311 	return 0;
312 }
313 
314 #ifdef CONFIG_ACPI
315 static const struct acpi_device_id xgene_rng_acpi_match[] = {
316 	{ "APMC0D18", },
317 	{ }
318 };
319 MODULE_DEVICE_TABLE(acpi, xgene_rng_acpi_match);
320 #endif
321 
322 static struct hwrng xgene_rng_func = {
323 	.name		= "xgene-rng",
324 	.init		= xgene_rng_init,
325 	.data_present	= xgene_rng_data_present,
326 	.data_read	= xgene_rng_data_read,
327 };
328 
329 static int xgene_rng_probe(struct platform_device *pdev)
330 {
331 	struct resource *res;
332 	struct xgene_rng_dev *ctx;
333 	int rc = 0;
334 
335 	ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
336 	if (!ctx)
337 		return -ENOMEM;
338 
339 	ctx->dev = &pdev->dev;
340 	platform_set_drvdata(pdev, ctx);
341 
342 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
343 	ctx->csr_base = devm_ioremap_resource(&pdev->dev, res);
344 	if (IS_ERR(ctx->csr_base))
345 		return PTR_ERR(ctx->csr_base);
346 
347 	rc = platform_get_irq(pdev, 0);
348 	if (rc < 0) {
349 		dev_err(&pdev->dev, "No IRQ resource\n");
350 		return rc;
351 	}
352 	ctx->irq = rc;
353 
354 	dev_dbg(&pdev->dev, "APM X-Gene RNG BASE %p ALARM IRQ %d",
355 		ctx->csr_base, ctx->irq);
356 
357 	rc = devm_request_irq(&pdev->dev, ctx->irq, xgene_rng_irq_handler, 0,
358 				dev_name(&pdev->dev), ctx);
359 	if (rc) {
360 		dev_err(&pdev->dev, "Could not request RNG alarm IRQ\n");
361 		return rc;
362 	}
363 
364 	/* Enable IP clock */
365 	ctx->clk = devm_clk_get(&pdev->dev, NULL);
366 	if (IS_ERR(ctx->clk)) {
367 		dev_warn(&pdev->dev, "Couldn't get the clock for RNG\n");
368 	} else {
369 		rc = clk_prepare_enable(ctx->clk);
370 		if (rc) {
371 			dev_warn(&pdev->dev,
372 				 "clock prepare enable failed for RNG");
373 			return rc;
374 		}
375 	}
376 
377 	xgene_rng_func.priv = (unsigned long) ctx;
378 
379 	rc = hwrng_register(&xgene_rng_func);
380 	if (rc) {
381 		dev_err(&pdev->dev, "RNG registering failed error %d\n", rc);
382 		if (!IS_ERR(ctx->clk))
383 			clk_disable_unprepare(ctx->clk);
384 		return rc;
385 	}
386 
387 	rc = device_init_wakeup(&pdev->dev, 1);
388 	if (rc) {
389 		dev_err(&pdev->dev, "RNG device_init_wakeup failed error %d\n",
390 			rc);
391 		if (!IS_ERR(ctx->clk))
392 			clk_disable_unprepare(ctx->clk);
393 		hwrng_unregister(&xgene_rng_func);
394 		return rc;
395 	}
396 
397 	return 0;
398 }
399 
400 static int xgene_rng_remove(struct platform_device *pdev)
401 {
402 	struct xgene_rng_dev *ctx = platform_get_drvdata(pdev);
403 	int rc;
404 
405 	rc = device_init_wakeup(&pdev->dev, 0);
406 	if (rc)
407 		dev_err(&pdev->dev, "RNG init wakeup failed error %d\n", rc);
408 	if (!IS_ERR(ctx->clk))
409 		clk_disable_unprepare(ctx->clk);
410 	hwrng_unregister(&xgene_rng_func);
411 
412 	return rc;
413 }
414 
415 static const struct of_device_id xgene_rng_of_match[] = {
416 	{ .compatible = "apm,xgene-rng" },
417 	{ }
418 };
419 
420 MODULE_DEVICE_TABLE(of, xgene_rng_of_match);
421 
422 static struct platform_driver xgene_rng_driver = {
423 	.probe = xgene_rng_probe,
424 	.remove	= xgene_rng_remove,
425 	.driver = {
426 		.name		= "xgene-rng",
427 		.of_match_table = xgene_rng_of_match,
428 		.acpi_match_table = ACPI_PTR(xgene_rng_acpi_match),
429 	},
430 };
431 
432 module_platform_driver(xgene_rng_driver);
433 MODULE_DESCRIPTION("APM X-Gene RNG driver");
434 MODULE_LICENSE("GPL");
435