11ccea77eSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
2a91ae4ebSFeng Kan /*
3a91ae4ebSFeng Kan * APM X-Gene SoC RNG Driver
4a91ae4ebSFeng Kan *
5a91ae4ebSFeng Kan * Copyright (c) 2014, Applied Micro Circuits Corporation
6a91ae4ebSFeng Kan * Author: Rameshwar Prasad Sahu <rsahu@apm.com>
7a91ae4ebSFeng Kan * Shamal Winchurkar <swinchurkar@apm.com>
8a91ae4ebSFeng Kan * Feng Kan <fkan@apm.com>
9a91ae4ebSFeng Kan */
10a91ae4ebSFeng Kan
11a508412bSFeng Kan #include <linux/acpi.h>
12a91ae4ebSFeng Kan #include <linux/clk.h>
13a91ae4ebSFeng Kan #include <linux/delay.h>
14a91ae4ebSFeng Kan #include <linux/hw_random.h>
15a91ae4ebSFeng Kan #include <linux/init.h>
16a91ae4ebSFeng Kan #include <linux/interrupt.h>
17*b9a281f1SRob Herring #include <linux/io.h>
18a91ae4ebSFeng Kan #include <linux/module.h>
190788257aSRob Herring #include <linux/mod_devicetable.h>
200788257aSRob Herring #include <linux/platform_device.h>
21a91ae4ebSFeng Kan #include <linux/timer.h>
22a91ae4ebSFeng Kan
23a91ae4ebSFeng Kan #define RNG_MAX_DATUM 4
24a91ae4ebSFeng Kan #define MAX_TRY 100
25a91ae4ebSFeng Kan #define XGENE_RNG_RETRY_COUNT 20
26a91ae4ebSFeng Kan #define XGENE_RNG_RETRY_INTERVAL 10
27a91ae4ebSFeng Kan
28a91ae4ebSFeng Kan /* RNG Registers */
29a91ae4ebSFeng Kan #define RNG_INOUT_0 0x00
30a91ae4ebSFeng Kan #define RNG_INTR_STS_ACK 0x10
31a91ae4ebSFeng Kan #define RNG_CONTROL 0x14
32a91ae4ebSFeng Kan #define RNG_CONFIG 0x18
33a91ae4ebSFeng Kan #define RNG_ALARMCNT 0x1c
34a91ae4ebSFeng Kan #define RNG_FROENABLE 0x20
35a91ae4ebSFeng Kan #define RNG_FRODETUNE 0x24
36a91ae4ebSFeng Kan #define RNG_ALARMMASK 0x28
37a91ae4ebSFeng Kan #define RNG_ALARMSTOP 0x2c
38a91ae4ebSFeng Kan #define RNG_OPTIONS 0x78
39a91ae4ebSFeng Kan #define RNG_EIP_REV 0x7c
40a91ae4ebSFeng Kan
41a91ae4ebSFeng Kan #define MONOBIT_FAIL_MASK BIT(7)
42a91ae4ebSFeng Kan #define POKER_FAIL_MASK BIT(6)
43a91ae4ebSFeng Kan #define LONG_RUN_FAIL_MASK BIT(5)
44a91ae4ebSFeng Kan #define RUN_FAIL_MASK BIT(4)
45a91ae4ebSFeng Kan #define NOISE_FAIL_MASK BIT(3)
46a91ae4ebSFeng Kan #define STUCK_OUT_MASK BIT(2)
47a91ae4ebSFeng Kan #define SHUTDOWN_OFLO_MASK BIT(1)
48a91ae4ebSFeng Kan #define READY_MASK BIT(0)
49a91ae4ebSFeng Kan
50a91ae4ebSFeng Kan #define MAJOR_HW_REV_RD(src) (((src) & 0x0f000000) >> 24)
51a91ae4ebSFeng Kan #define MINOR_HW_REV_RD(src) (((src) & 0x00f00000) >> 20)
52a91ae4ebSFeng Kan #define HW_PATCH_LEVEL_RD(src) (((src) & 0x000f0000) >> 16)
53a91ae4ebSFeng Kan #define MAX_REFILL_CYCLES_SET(dst, src) \
54a91ae4ebSFeng Kan ((dst & ~0xffff0000) | (((u32)src << 16) & 0xffff0000))
55a91ae4ebSFeng Kan #define MIN_REFILL_CYCLES_SET(dst, src) \
56a91ae4ebSFeng Kan ((dst & ~0x000000ff) | (((u32)src) & 0x000000ff))
57a91ae4ebSFeng Kan #define ALARM_THRESHOLD_SET(dst, src) \
58a91ae4ebSFeng Kan ((dst & ~0x000000ff) | (((u32)src) & 0x000000ff))
59a91ae4ebSFeng Kan #define ENABLE_RNG_SET(dst, src) \
60a91ae4ebSFeng Kan ((dst & ~BIT(10)) | (((u32)src << 10) & BIT(10)))
61a91ae4ebSFeng Kan #define REGSPEC_TEST_MODE_SET(dst, src) \
62a91ae4ebSFeng Kan ((dst & ~BIT(8)) | (((u32)src << 8) & BIT(8)))
63a91ae4ebSFeng Kan #define MONOBIT_FAIL_MASK_SET(dst, src) \
64a91ae4ebSFeng Kan ((dst & ~BIT(7)) | (((u32)src << 7) & BIT(7)))
65a91ae4ebSFeng Kan #define POKER_FAIL_MASK_SET(dst, src) \
66a91ae4ebSFeng Kan ((dst & ~BIT(6)) | (((u32)src << 6) & BIT(6)))
67a91ae4ebSFeng Kan #define LONG_RUN_FAIL_MASK_SET(dst, src) \
68a91ae4ebSFeng Kan ((dst & ~BIT(5)) | (((u32)src << 5) & BIT(5)))
69a91ae4ebSFeng Kan #define RUN_FAIL_MASK_SET(dst, src) \
70a91ae4ebSFeng Kan ((dst & ~BIT(4)) | (((u32)src << 4) & BIT(4)))
71a91ae4ebSFeng Kan #define NOISE_FAIL_MASK_SET(dst, src) \
72a91ae4ebSFeng Kan ((dst & ~BIT(3)) | (((u32)src << 3) & BIT(3)))
73a91ae4ebSFeng Kan #define STUCK_OUT_MASK_SET(dst, src) \
74a91ae4ebSFeng Kan ((dst & ~BIT(2)) | (((u32)src << 2) & BIT(2)))
75a91ae4ebSFeng Kan #define SHUTDOWN_OFLO_MASK_SET(dst, src) \
76a91ae4ebSFeng Kan ((dst & ~BIT(1)) | (((u32)src << 1) & BIT(1)))
77a91ae4ebSFeng Kan
78a91ae4ebSFeng Kan struct xgene_rng_dev {
79a91ae4ebSFeng Kan u32 irq;
80a91ae4ebSFeng Kan void __iomem *csr_base;
81a91ae4ebSFeng Kan u32 revision;
82a91ae4ebSFeng Kan u32 datum_size;
83a91ae4ebSFeng Kan u32 failure_cnt; /* Failure count last minute */
84a91ae4ebSFeng Kan unsigned long failure_ts;/* First failure timestamp */
85a91ae4ebSFeng Kan struct timer_list failure_timer;
86a91ae4ebSFeng Kan struct device *dev;
87a91ae4ebSFeng Kan };
88a91ae4ebSFeng Kan
xgene_rng_expired_timer(struct timer_list * t)89200d24d6SKees Cook static void xgene_rng_expired_timer(struct timer_list *t)
90a91ae4ebSFeng Kan {
91200d24d6SKees Cook struct xgene_rng_dev *ctx = from_timer(ctx, t, failure_timer);
92a91ae4ebSFeng Kan
93a91ae4ebSFeng Kan /* Clear failure counter as timer expired */
94a91ae4ebSFeng Kan disable_irq(ctx->irq);
95a91ae4ebSFeng Kan ctx->failure_cnt = 0;
96a91ae4ebSFeng Kan del_timer(&ctx->failure_timer);
97a91ae4ebSFeng Kan enable_irq(ctx->irq);
98a91ae4ebSFeng Kan }
99a91ae4ebSFeng Kan
xgene_rng_start_timer(struct xgene_rng_dev * ctx)100a91ae4ebSFeng Kan static void xgene_rng_start_timer(struct xgene_rng_dev *ctx)
101a91ae4ebSFeng Kan {
102a91ae4ebSFeng Kan ctx->failure_timer.expires = jiffies + 120 * HZ;
103a91ae4ebSFeng Kan add_timer(&ctx->failure_timer);
104a91ae4ebSFeng Kan }
105a91ae4ebSFeng Kan
106a91ae4ebSFeng Kan /*
107a91ae4ebSFeng Kan * Initialize or reinit free running oscillators (FROs)
108a91ae4ebSFeng Kan */
xgene_rng_init_fro(struct xgene_rng_dev * ctx,u32 fro_val)109a91ae4ebSFeng Kan static void xgene_rng_init_fro(struct xgene_rng_dev *ctx, u32 fro_val)
110a91ae4ebSFeng Kan {
111a91ae4ebSFeng Kan writel(fro_val, ctx->csr_base + RNG_FRODETUNE);
112a91ae4ebSFeng Kan writel(0x00000000, ctx->csr_base + RNG_ALARMMASK);
113a91ae4ebSFeng Kan writel(0x00000000, ctx->csr_base + RNG_ALARMSTOP);
114a91ae4ebSFeng Kan writel(0xFFFFFFFF, ctx->csr_base + RNG_FROENABLE);
115a91ae4ebSFeng Kan }
116a91ae4ebSFeng Kan
xgene_rng_chk_overflow(struct xgene_rng_dev * ctx)117a91ae4ebSFeng Kan static void xgene_rng_chk_overflow(struct xgene_rng_dev *ctx)
118a91ae4ebSFeng Kan {
119a91ae4ebSFeng Kan u32 val;
120a91ae4ebSFeng Kan
121a91ae4ebSFeng Kan val = readl(ctx->csr_base + RNG_INTR_STS_ACK);
122a91ae4ebSFeng Kan if (val & MONOBIT_FAIL_MASK)
123a91ae4ebSFeng Kan /*
124a91ae4ebSFeng Kan * LFSR detected an out-of-bounds number of 1s after
125a91ae4ebSFeng Kan * checking 20,000 bits (test T1 as specified in the
126a91ae4ebSFeng Kan * AIS-31 standard)
127a91ae4ebSFeng Kan */
128a91ae4ebSFeng Kan dev_err(ctx->dev, "test monobit failure error 0x%08X\n", val);
129a91ae4ebSFeng Kan if (val & POKER_FAIL_MASK)
130a91ae4ebSFeng Kan /*
131a91ae4ebSFeng Kan * LFSR detected an out-of-bounds value in at least one
132a91ae4ebSFeng Kan * of the 16 poker_count_X counters or an out of bounds sum
133a91ae4ebSFeng Kan * of squares value after checking 20,000 bits (test T2 as
134a91ae4ebSFeng Kan * specified in the AIS-31 standard)
135a91ae4ebSFeng Kan */
136a91ae4ebSFeng Kan dev_err(ctx->dev, "test poker failure error 0x%08X\n", val);
137a91ae4ebSFeng Kan if (val & LONG_RUN_FAIL_MASK)
138a91ae4ebSFeng Kan /*
139a91ae4ebSFeng Kan * LFSR detected a sequence of 34 identical bits
140a91ae4ebSFeng Kan * (test T4 as specified in the AIS-31 standard)
141a91ae4ebSFeng Kan */
142a91ae4ebSFeng Kan dev_err(ctx->dev, "test long run failure error 0x%08X\n", val);
143a91ae4ebSFeng Kan if (val & RUN_FAIL_MASK)
144a91ae4ebSFeng Kan /*
145a91ae4ebSFeng Kan * LFSR detected an outof-bounds value for at least one
146a91ae4ebSFeng Kan * of the running counters after checking 20,000 bits
147a91ae4ebSFeng Kan * (test T3 as specified in the AIS-31 standard)
148a91ae4ebSFeng Kan */
149a91ae4ebSFeng Kan dev_err(ctx->dev, "test run failure error 0x%08X\n", val);
150a91ae4ebSFeng Kan if (val & NOISE_FAIL_MASK)
151a91ae4ebSFeng Kan /* LFSR detected a sequence of 48 identical bits */
152a91ae4ebSFeng Kan dev_err(ctx->dev, "noise failure error 0x%08X\n", val);
153a91ae4ebSFeng Kan if (val & STUCK_OUT_MASK)
154a91ae4ebSFeng Kan /*
155a91ae4ebSFeng Kan * Detected output data registers generated same value twice
156a91ae4ebSFeng Kan * in a row
157a91ae4ebSFeng Kan */
158a91ae4ebSFeng Kan dev_err(ctx->dev, "stuck out failure error 0x%08X\n", val);
159a91ae4ebSFeng Kan
160a91ae4ebSFeng Kan if (val & SHUTDOWN_OFLO_MASK) {
161a91ae4ebSFeng Kan u32 frostopped;
162a91ae4ebSFeng Kan
163a91ae4ebSFeng Kan /* FROs shut down after a second error event. Try recover. */
164a91ae4ebSFeng Kan if (++ctx->failure_cnt == 1) {
165a91ae4ebSFeng Kan /* 1st time, just recover */
166a91ae4ebSFeng Kan ctx->failure_ts = jiffies;
167a91ae4ebSFeng Kan frostopped = readl(ctx->csr_base + RNG_ALARMSTOP);
168a91ae4ebSFeng Kan xgene_rng_init_fro(ctx, frostopped);
169a91ae4ebSFeng Kan
170a91ae4ebSFeng Kan /*
171a91ae4ebSFeng Kan * We must start a timer to clear out this error
172a91ae4ebSFeng Kan * in case the system timer wrap around
173a91ae4ebSFeng Kan */
174a91ae4ebSFeng Kan xgene_rng_start_timer(ctx);
175a91ae4ebSFeng Kan } else {
176a91ae4ebSFeng Kan /* 2nd time failure in lesser than 1 minute? */
177a91ae4ebSFeng Kan if (time_after(ctx->failure_ts + 60 * HZ, jiffies)) {
178a91ae4ebSFeng Kan dev_err(ctx->dev,
179a91ae4ebSFeng Kan "FRO shutdown failure error 0x%08X\n",
180a91ae4ebSFeng Kan val);
181a91ae4ebSFeng Kan } else {
182a91ae4ebSFeng Kan /* 2nd time failure after 1 minutes, recover */
183a91ae4ebSFeng Kan ctx->failure_ts = jiffies;
184a91ae4ebSFeng Kan ctx->failure_cnt = 1;
185a91ae4ebSFeng Kan /*
186a91ae4ebSFeng Kan * We must start a timer to clear out this
187a91ae4ebSFeng Kan * error in case the system timer wrap
188a91ae4ebSFeng Kan * around
189a91ae4ebSFeng Kan */
190a91ae4ebSFeng Kan xgene_rng_start_timer(ctx);
191a91ae4ebSFeng Kan }
192a91ae4ebSFeng Kan frostopped = readl(ctx->csr_base + RNG_ALARMSTOP);
193a91ae4ebSFeng Kan xgene_rng_init_fro(ctx, frostopped);
194a91ae4ebSFeng Kan }
195a91ae4ebSFeng Kan }
196a91ae4ebSFeng Kan /* Clear them all */
197a91ae4ebSFeng Kan writel(val, ctx->csr_base + RNG_INTR_STS_ACK);
198a91ae4ebSFeng Kan }
199a91ae4ebSFeng Kan
xgene_rng_irq_handler(int irq,void * id)200a91ae4ebSFeng Kan static irqreturn_t xgene_rng_irq_handler(int irq, void *id)
201a91ae4ebSFeng Kan {
2026faacef0SYu Zhe struct xgene_rng_dev *ctx = id;
203a91ae4ebSFeng Kan
204a91ae4ebSFeng Kan /* RNG Alarm Counter overflow */
205a91ae4ebSFeng Kan xgene_rng_chk_overflow(ctx);
206a91ae4ebSFeng Kan
207a91ae4ebSFeng Kan return IRQ_HANDLED;
208a91ae4ebSFeng Kan }
209a91ae4ebSFeng Kan
xgene_rng_data_present(struct hwrng * rng,int wait)210a91ae4ebSFeng Kan static int xgene_rng_data_present(struct hwrng *rng, int wait)
211a91ae4ebSFeng Kan {
212a91ae4ebSFeng Kan struct xgene_rng_dev *ctx = (struct xgene_rng_dev *) rng->priv;
213a91ae4ebSFeng Kan u32 i, val = 0;
214a91ae4ebSFeng Kan
215a91ae4ebSFeng Kan for (i = 0; i < XGENE_RNG_RETRY_COUNT; i++) {
216a91ae4ebSFeng Kan val = readl(ctx->csr_base + RNG_INTR_STS_ACK);
217a91ae4ebSFeng Kan if ((val & READY_MASK) || !wait)
218a91ae4ebSFeng Kan break;
219a91ae4ebSFeng Kan udelay(XGENE_RNG_RETRY_INTERVAL);
220a91ae4ebSFeng Kan }
221a91ae4ebSFeng Kan
222a91ae4ebSFeng Kan return (val & READY_MASK);
223a91ae4ebSFeng Kan }
224a91ae4ebSFeng Kan
xgene_rng_data_read(struct hwrng * rng,u32 * data)225a91ae4ebSFeng Kan static int xgene_rng_data_read(struct hwrng *rng, u32 *data)
226a91ae4ebSFeng Kan {
227a91ae4ebSFeng Kan struct xgene_rng_dev *ctx = (struct xgene_rng_dev *) rng->priv;
228a91ae4ebSFeng Kan int i;
229a91ae4ebSFeng Kan
230a91ae4ebSFeng Kan for (i = 0; i < ctx->datum_size; i++)
231a91ae4ebSFeng Kan data[i] = readl(ctx->csr_base + RNG_INOUT_0 + i * 4);
232a91ae4ebSFeng Kan
233a91ae4ebSFeng Kan /* Clear ready bit to start next transaction */
234a91ae4ebSFeng Kan writel(READY_MASK, ctx->csr_base + RNG_INTR_STS_ACK);
235a91ae4ebSFeng Kan
236a91ae4ebSFeng Kan return ctx->datum_size << 2;
237a91ae4ebSFeng Kan }
238a91ae4ebSFeng Kan
xgene_rng_init_internal(struct xgene_rng_dev * ctx)239a91ae4ebSFeng Kan static void xgene_rng_init_internal(struct xgene_rng_dev *ctx)
240a91ae4ebSFeng Kan {
241a91ae4ebSFeng Kan u32 val;
242a91ae4ebSFeng Kan
243a91ae4ebSFeng Kan writel(0x00000000, ctx->csr_base + RNG_CONTROL);
244a91ae4ebSFeng Kan
245a91ae4ebSFeng Kan val = MAX_REFILL_CYCLES_SET(0, 10);
246a91ae4ebSFeng Kan val = MIN_REFILL_CYCLES_SET(val, 10);
247a91ae4ebSFeng Kan writel(val, ctx->csr_base + RNG_CONFIG);
248a91ae4ebSFeng Kan
249a91ae4ebSFeng Kan val = ALARM_THRESHOLD_SET(0, 0xFF);
250a91ae4ebSFeng Kan writel(val, ctx->csr_base + RNG_ALARMCNT);
251a91ae4ebSFeng Kan
252a91ae4ebSFeng Kan xgene_rng_init_fro(ctx, 0);
253a91ae4ebSFeng Kan
254a91ae4ebSFeng Kan writel(MONOBIT_FAIL_MASK |
255a91ae4ebSFeng Kan POKER_FAIL_MASK |
256a91ae4ebSFeng Kan LONG_RUN_FAIL_MASK |
257a91ae4ebSFeng Kan RUN_FAIL_MASK |
258a91ae4ebSFeng Kan NOISE_FAIL_MASK |
259a91ae4ebSFeng Kan STUCK_OUT_MASK |
260a91ae4ebSFeng Kan SHUTDOWN_OFLO_MASK |
261a91ae4ebSFeng Kan READY_MASK, ctx->csr_base + RNG_INTR_STS_ACK);
262a91ae4ebSFeng Kan
263a91ae4ebSFeng Kan val = ENABLE_RNG_SET(0, 1);
264a91ae4ebSFeng Kan val = MONOBIT_FAIL_MASK_SET(val, 1);
265a91ae4ebSFeng Kan val = POKER_FAIL_MASK_SET(val, 1);
266a91ae4ebSFeng Kan val = LONG_RUN_FAIL_MASK_SET(val, 1);
267a91ae4ebSFeng Kan val = RUN_FAIL_MASK_SET(val, 1);
268a91ae4ebSFeng Kan val = NOISE_FAIL_MASK_SET(val, 1);
269a91ae4ebSFeng Kan val = STUCK_OUT_MASK_SET(val, 1);
270a91ae4ebSFeng Kan val = SHUTDOWN_OFLO_MASK_SET(val, 1);
271a91ae4ebSFeng Kan writel(val, ctx->csr_base + RNG_CONTROL);
272a91ae4ebSFeng Kan }
273a91ae4ebSFeng Kan
xgene_rng_init(struct hwrng * rng)274a91ae4ebSFeng Kan static int xgene_rng_init(struct hwrng *rng)
275a91ae4ebSFeng Kan {
276a91ae4ebSFeng Kan struct xgene_rng_dev *ctx = (struct xgene_rng_dev *) rng->priv;
277a91ae4ebSFeng Kan
278a91ae4ebSFeng Kan ctx->failure_cnt = 0;
279200d24d6SKees Cook timer_setup(&ctx->failure_timer, xgene_rng_expired_timer, 0);
280a91ae4ebSFeng Kan
281a91ae4ebSFeng Kan ctx->revision = readl(ctx->csr_base + RNG_EIP_REV);
282a91ae4ebSFeng Kan
283a91ae4ebSFeng Kan dev_dbg(ctx->dev, "Rev %d.%d.%d\n",
284a91ae4ebSFeng Kan MAJOR_HW_REV_RD(ctx->revision),
285a91ae4ebSFeng Kan MINOR_HW_REV_RD(ctx->revision),
286a91ae4ebSFeng Kan HW_PATCH_LEVEL_RD(ctx->revision));
287a91ae4ebSFeng Kan
288a91ae4ebSFeng Kan dev_dbg(ctx->dev, "Options 0x%08X",
289a91ae4ebSFeng Kan readl(ctx->csr_base + RNG_OPTIONS));
290a91ae4ebSFeng Kan
291a91ae4ebSFeng Kan xgene_rng_init_internal(ctx);
292a91ae4ebSFeng Kan
293a91ae4ebSFeng Kan ctx->datum_size = RNG_MAX_DATUM;
294a91ae4ebSFeng Kan
295a91ae4ebSFeng Kan return 0;
296a91ae4ebSFeng Kan }
297a91ae4ebSFeng Kan
298a508412bSFeng Kan #ifdef CONFIG_ACPI
299a508412bSFeng Kan static const struct acpi_device_id xgene_rng_acpi_match[] = {
300a508412bSFeng Kan { "APMC0D18", },
301a508412bSFeng Kan { }
302a508412bSFeng Kan };
303a508412bSFeng Kan MODULE_DEVICE_TABLE(acpi, xgene_rng_acpi_match);
304a508412bSFeng Kan #endif
305a508412bSFeng Kan
306a91ae4ebSFeng Kan static struct hwrng xgene_rng_func = {
307a91ae4ebSFeng Kan .name = "xgene-rng",
308a91ae4ebSFeng Kan .init = xgene_rng_init,
309a91ae4ebSFeng Kan .data_present = xgene_rng_data_present,
310a91ae4ebSFeng Kan .data_read = xgene_rng_data_read,
311a91ae4ebSFeng Kan };
312a91ae4ebSFeng Kan
xgene_rng_probe(struct platform_device * pdev)313a91ae4ebSFeng Kan static int xgene_rng_probe(struct platform_device *pdev)
314a91ae4ebSFeng Kan {
315a91ae4ebSFeng Kan struct xgene_rng_dev *ctx;
31667fb1e29SUwe Kleine-König struct clk *clk;
317a91ae4ebSFeng Kan int rc = 0;
318a91ae4ebSFeng Kan
319a91ae4ebSFeng Kan ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
320a91ae4ebSFeng Kan if (!ctx)
321a91ae4ebSFeng Kan return -ENOMEM;
322a91ae4ebSFeng Kan
323a91ae4ebSFeng Kan ctx->dev = &pdev->dev;
324a91ae4ebSFeng Kan platform_set_drvdata(pdev, ctx);
325a91ae4ebSFeng Kan
3264c747d4dSYueHaibing ctx->csr_base = devm_platform_ioremap_resource(pdev, 0);
327a91ae4ebSFeng Kan if (IS_ERR(ctx->csr_base))
328a91ae4ebSFeng Kan return PTR_ERR(ctx->csr_base);
329a91ae4ebSFeng Kan
33009185e27SAndrzej Hajda rc = platform_get_irq(pdev, 0);
331f72fed86SMarkus Elfring if (rc < 0)
33209185e27SAndrzej Hajda return rc;
33309185e27SAndrzej Hajda ctx->irq = rc;
334a91ae4ebSFeng Kan
335a91ae4ebSFeng Kan dev_dbg(&pdev->dev, "APM X-Gene RNG BASE %p ALARM IRQ %d",
336a91ae4ebSFeng Kan ctx->csr_base, ctx->irq);
337a91ae4ebSFeng Kan
338a91ae4ebSFeng Kan rc = devm_request_irq(&pdev->dev, ctx->irq, xgene_rng_irq_handler, 0,
339a91ae4ebSFeng Kan dev_name(&pdev->dev), ctx);
34011f92a13SUwe Kleine-König if (rc)
34111f92a13SUwe Kleine-König return dev_err_probe(&pdev->dev, rc, "Could not request RNG alarm IRQ\n");
342a91ae4ebSFeng Kan
343a91ae4ebSFeng Kan /* Enable IP clock */
34467fb1e29SUwe Kleine-König clk = devm_clk_get_optional_enabled(&pdev->dev, NULL);
34567fb1e29SUwe Kleine-König if (IS_ERR(clk))
34667fb1e29SUwe Kleine-König return dev_err_probe(&pdev->dev, PTR_ERR(clk), "Couldn't get the clock for RNG\n");
347a91ae4ebSFeng Kan
348a91ae4ebSFeng Kan xgene_rng_func.priv = (unsigned long) ctx;
349a91ae4ebSFeng Kan
3503e75241bSChuhong Yuan rc = devm_hwrng_register(&pdev->dev, &xgene_rng_func);
35167fb1e29SUwe Kleine-König if (rc)
35211f92a13SUwe Kleine-König return dev_err_probe(&pdev->dev, rc, "RNG registering failed\n");
353a91ae4ebSFeng Kan
354a91ae4ebSFeng Kan rc = device_init_wakeup(&pdev->dev, 1);
35567fb1e29SUwe Kleine-König if (rc)
35611f92a13SUwe Kleine-König return dev_err_probe(&pdev->dev, rc, "RNG device_init_wakeup failed\n");
357a91ae4ebSFeng Kan
358a91ae4ebSFeng Kan return 0;
359a91ae4ebSFeng Kan }
360a91ae4ebSFeng Kan
xgene_rng_remove(struct platform_device * pdev)361a91ae4ebSFeng Kan static int xgene_rng_remove(struct platform_device *pdev)
362a91ae4ebSFeng Kan {
363a91ae4ebSFeng Kan int rc;
364a91ae4ebSFeng Kan
365a91ae4ebSFeng Kan rc = device_init_wakeup(&pdev->dev, 0);
366a91ae4ebSFeng Kan if (rc)
367a91ae4ebSFeng Kan dev_err(&pdev->dev, "RNG init wakeup failed error %d\n", rc);
368a91ae4ebSFeng Kan
3690e44db95SUwe Kleine-König return 0;
370a91ae4ebSFeng Kan }
371a91ae4ebSFeng Kan
372a91ae4ebSFeng Kan static const struct of_device_id xgene_rng_of_match[] = {
373a91ae4ebSFeng Kan { .compatible = "apm,xgene-rng" },
374a91ae4ebSFeng Kan { }
375a91ae4ebSFeng Kan };
376a91ae4ebSFeng Kan
377a91ae4ebSFeng Kan MODULE_DEVICE_TABLE(of, xgene_rng_of_match);
378a91ae4ebSFeng Kan
379a91ae4ebSFeng Kan static struct platform_driver xgene_rng_driver = {
380a91ae4ebSFeng Kan .probe = xgene_rng_probe,
381a91ae4ebSFeng Kan .remove = xgene_rng_remove,
382a91ae4ebSFeng Kan .driver = {
383a91ae4ebSFeng Kan .name = "xgene-rng",
384a91ae4ebSFeng Kan .of_match_table = xgene_rng_of_match,
385a508412bSFeng Kan .acpi_match_table = ACPI_PTR(xgene_rng_acpi_match),
386a91ae4ebSFeng Kan },
387a91ae4ebSFeng Kan };
388a91ae4ebSFeng Kan
389a91ae4ebSFeng Kan module_platform_driver(xgene_rng_driver);
390a91ae4ebSFeng Kan MODULE_DESCRIPTION("APM X-Gene RNG driver");
391a91ae4ebSFeng Kan MODULE_LICENSE("GPL");
392