1 /* n2-drv.c: Niagara-2 RNG driver. 2 * 3 * Copyright (C) 2008, 2011 David S. Miller <davem@davemloft.net> 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/module.h> 8 #include <linux/types.h> 9 #include <linux/delay.h> 10 #include <linux/slab.h> 11 #include <linux/workqueue.h> 12 #include <linux/preempt.h> 13 #include <linux/hw_random.h> 14 15 #include <linux/of.h> 16 #include <linux/of_device.h> 17 18 #include <asm/hypervisor.h> 19 20 #include "n2rng.h" 21 22 #define DRV_MODULE_NAME "n2rng" 23 #define PFX DRV_MODULE_NAME ": " 24 #define DRV_MODULE_VERSION "0.3" 25 #define DRV_MODULE_RELDATE "Jan 7, 2017" 26 27 static char version[] = 28 DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; 29 30 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)"); 31 MODULE_DESCRIPTION("Niagara2 RNG driver"); 32 MODULE_LICENSE("GPL"); 33 MODULE_VERSION(DRV_MODULE_VERSION); 34 35 /* The Niagara2 RNG provides a 64-bit read-only random number 36 * register, plus a control register. Access to the RNG is 37 * virtualized through the hypervisor so that both guests and control 38 * nodes can access the device. 39 * 40 * The entropy source consists of raw entropy sources, each 41 * constructed from a voltage controlled oscillator whose phase is 42 * jittered by thermal noise sources. 43 * 44 * The oscillator in each of the three raw entropy sources run at 45 * different frequencies. Normally, all three generator outputs are 46 * gathered, xored together, and fed into a CRC circuit, the output of 47 * which is the 64-bit read-only register. 48 * 49 * Some time is necessary for all the necessary entropy to build up 50 * such that a full 64-bits of entropy are available in the register. 51 * In normal operating mode (RNG_CTL_LFSR is set), the chip implements 52 * an interlock which blocks register reads until sufficient entropy 53 * is available. 54 * 55 * A control register is provided for adjusting various aspects of RNG 56 * operation, and to enable diagnostic modes. Each of the three raw 57 * entropy sources has an enable bit (RNG_CTL_ES{1,2,3}). Also 58 * provided are fields for controlling the minimum time in cycles 59 * between read accesses to the register (RNG_CTL_WAIT, this controls 60 * the interlock described in the previous paragraph). 61 * 62 * The standard setting is to have the mode bit (RNG_CTL_LFSR) set, 63 * all three entropy sources enabled, and the interlock time set 64 * appropriately. 65 * 66 * The CRC polynomial used by the chip is: 67 * 68 * P(X) = x64 + x61 + x57 + x56 + x52 + x51 + x50 + x48 + x47 + x46 + 69 * x43 + x42 + x41 + x39 + x38 + x37 + x35 + x32 + x28 + x25 + 70 * x22 + x21 + x17 + x15 + x13 + x12 + x11 + x7 + x5 + x + 1 71 * 72 * The RNG_CTL_VCO value of each noise cell must be programmed 73 * separately. This is why 4 control register values must be provided 74 * to the hypervisor. During a write, the hypervisor writes them all, 75 * one at a time, to the actual RNG_CTL register. The first three 76 * values are used to setup the desired RNG_CTL_VCO for each entropy 77 * source, for example: 78 * 79 * control 0: (1 << RNG_CTL_VCO_SHIFT) | RNG_CTL_ES1 80 * control 1: (2 << RNG_CTL_VCO_SHIFT) | RNG_CTL_ES2 81 * control 2: (3 << RNG_CTL_VCO_SHIFT) | RNG_CTL_ES3 82 * 83 * And then the fourth value sets the final chip state and enables 84 * desired. 85 */ 86 87 static int n2rng_hv_err_trans(unsigned long hv_err) 88 { 89 switch (hv_err) { 90 case HV_EOK: 91 return 0; 92 case HV_EWOULDBLOCK: 93 return -EAGAIN; 94 case HV_ENOACCESS: 95 return -EPERM; 96 case HV_EIO: 97 return -EIO; 98 case HV_EBUSY: 99 return -EBUSY; 100 case HV_EBADALIGN: 101 case HV_ENORADDR: 102 return -EFAULT; 103 default: 104 return -EINVAL; 105 } 106 } 107 108 static unsigned long n2rng_generic_read_control_v2(unsigned long ra, 109 unsigned long unit) 110 { 111 unsigned long hv_err, state, ticks, watchdog_delta, watchdog_status; 112 int block = 0, busy = 0; 113 114 while (1) { 115 hv_err = sun4v_rng_ctl_read_v2(ra, unit, &state, 116 &ticks, 117 &watchdog_delta, 118 &watchdog_status); 119 if (hv_err == HV_EOK) 120 break; 121 122 if (hv_err == HV_EBUSY) { 123 if (++busy >= N2RNG_BUSY_LIMIT) 124 break; 125 126 udelay(1); 127 } else if (hv_err == HV_EWOULDBLOCK) { 128 if (++block >= N2RNG_BLOCK_LIMIT) 129 break; 130 131 __delay(ticks); 132 } else 133 break; 134 } 135 136 return hv_err; 137 } 138 139 /* In multi-socket situations, the hypervisor might need to 140 * queue up the RNG control register write if it's for a unit 141 * that is on a cpu socket other than the one we are executing on. 142 * 143 * We poll here waiting for a successful read of that control 144 * register to make sure the write has been actually performed. 145 */ 146 static unsigned long n2rng_control_settle_v2(struct n2rng *np, int unit) 147 { 148 unsigned long ra = __pa(&np->scratch_control[0]); 149 150 return n2rng_generic_read_control_v2(ra, unit); 151 } 152 153 static unsigned long n2rng_write_ctl_one(struct n2rng *np, int unit, 154 unsigned long state, 155 unsigned long control_ra, 156 unsigned long watchdog_timeout, 157 unsigned long *ticks) 158 { 159 unsigned long hv_err; 160 161 if (np->hvapi_major == 1) { 162 hv_err = sun4v_rng_ctl_write_v1(control_ra, state, 163 watchdog_timeout, ticks); 164 } else { 165 hv_err = sun4v_rng_ctl_write_v2(control_ra, state, 166 watchdog_timeout, unit); 167 if (hv_err == HV_EOK) 168 hv_err = n2rng_control_settle_v2(np, unit); 169 *ticks = N2RNG_ACCUM_CYCLES_DEFAULT; 170 } 171 172 return hv_err; 173 } 174 175 static int n2rng_generic_read_data(unsigned long data_ra) 176 { 177 unsigned long ticks, hv_err; 178 int block = 0, hcheck = 0; 179 180 while (1) { 181 hv_err = sun4v_rng_data_read(data_ra, &ticks); 182 if (hv_err == HV_EOK) 183 return 0; 184 185 if (hv_err == HV_EWOULDBLOCK) { 186 if (++block >= N2RNG_BLOCK_LIMIT) 187 return -EWOULDBLOCK; 188 __delay(ticks); 189 } else if (hv_err == HV_ENOACCESS) { 190 return -EPERM; 191 } else if (hv_err == HV_EIO) { 192 if (++hcheck >= N2RNG_HCHECK_LIMIT) 193 return -EIO; 194 udelay(10000); 195 } else 196 return -ENODEV; 197 } 198 } 199 200 static unsigned long n2rng_read_diag_data_one(struct n2rng *np, 201 unsigned long unit, 202 unsigned long data_ra, 203 unsigned long data_len, 204 unsigned long *ticks) 205 { 206 unsigned long hv_err; 207 208 if (np->hvapi_major == 1) { 209 hv_err = sun4v_rng_data_read_diag_v1(data_ra, data_len, ticks); 210 } else { 211 hv_err = sun4v_rng_data_read_diag_v2(data_ra, data_len, 212 unit, ticks); 213 if (!*ticks) 214 *ticks = N2RNG_ACCUM_CYCLES_DEFAULT; 215 } 216 return hv_err; 217 } 218 219 static int n2rng_generic_read_diag_data(struct n2rng *np, 220 unsigned long unit, 221 unsigned long data_ra, 222 unsigned long data_len) 223 { 224 unsigned long ticks, hv_err; 225 int block = 0; 226 227 while (1) { 228 hv_err = n2rng_read_diag_data_one(np, unit, 229 data_ra, data_len, 230 &ticks); 231 if (hv_err == HV_EOK) 232 return 0; 233 234 if (hv_err == HV_EWOULDBLOCK) { 235 if (++block >= N2RNG_BLOCK_LIMIT) 236 return -EWOULDBLOCK; 237 __delay(ticks); 238 } else if (hv_err == HV_ENOACCESS) { 239 return -EPERM; 240 } else if (hv_err == HV_EIO) { 241 return -EIO; 242 } else 243 return -ENODEV; 244 } 245 } 246 247 248 static int n2rng_generic_write_control(struct n2rng *np, 249 unsigned long control_ra, 250 unsigned long unit, 251 unsigned long state) 252 { 253 unsigned long hv_err, ticks; 254 int block = 0, busy = 0; 255 256 while (1) { 257 hv_err = n2rng_write_ctl_one(np, unit, state, control_ra, 258 np->wd_timeo, &ticks); 259 if (hv_err == HV_EOK) 260 return 0; 261 262 if (hv_err == HV_EWOULDBLOCK) { 263 if (++block >= N2RNG_BLOCK_LIMIT) 264 return -EWOULDBLOCK; 265 __delay(ticks); 266 } else if (hv_err == HV_EBUSY) { 267 if (++busy >= N2RNG_BUSY_LIMIT) 268 return -EBUSY; 269 udelay(1); 270 } else 271 return -ENODEV; 272 } 273 } 274 275 /* Just try to see if we can successfully access the control register 276 * of the RNG on the domain on which we are currently executing. 277 */ 278 static int n2rng_try_read_ctl(struct n2rng *np) 279 { 280 unsigned long hv_err; 281 unsigned long x; 282 283 if (np->hvapi_major == 1) { 284 hv_err = sun4v_rng_get_diag_ctl(); 285 } else { 286 /* We purposefully give invalid arguments, HV_NOACCESS 287 * is higher priority than the errors we'd get from 288 * these other cases, and that's the error we are 289 * truly interested in. 290 */ 291 hv_err = sun4v_rng_ctl_read_v2(0UL, ~0UL, &x, &x, &x, &x); 292 switch (hv_err) { 293 case HV_EWOULDBLOCK: 294 case HV_ENOACCESS: 295 break; 296 default: 297 hv_err = HV_EOK; 298 break; 299 } 300 } 301 302 return n2rng_hv_err_trans(hv_err); 303 } 304 305 static u64 n2rng_control_default(struct n2rng *np, int ctl) 306 { 307 u64 val = 0; 308 309 if (np->data->chip_version == 1) { 310 val = ((2 << RNG_v1_CTL_ASEL_SHIFT) | 311 (N2RNG_ACCUM_CYCLES_DEFAULT << RNG_v1_CTL_WAIT_SHIFT) | 312 RNG_CTL_LFSR); 313 314 switch (ctl) { 315 case 0: 316 val |= (1 << RNG_v1_CTL_VCO_SHIFT) | RNG_CTL_ES1; 317 break; 318 case 1: 319 val |= (2 << RNG_v1_CTL_VCO_SHIFT) | RNG_CTL_ES2; 320 break; 321 case 2: 322 val |= (3 << RNG_v1_CTL_VCO_SHIFT) | RNG_CTL_ES3; 323 break; 324 case 3: 325 val |= RNG_CTL_ES1 | RNG_CTL_ES2 | RNG_CTL_ES3; 326 break; 327 default: 328 break; 329 } 330 331 } else { 332 val = ((2 << RNG_v2_CTL_ASEL_SHIFT) | 333 (N2RNG_ACCUM_CYCLES_DEFAULT << RNG_v2_CTL_WAIT_SHIFT) | 334 RNG_CTL_LFSR); 335 336 switch (ctl) { 337 case 0: 338 val |= (1 << RNG_v2_CTL_VCO_SHIFT) | RNG_CTL_ES1; 339 break; 340 case 1: 341 val |= (2 << RNG_v2_CTL_VCO_SHIFT) | RNG_CTL_ES2; 342 break; 343 case 2: 344 val |= (3 << RNG_v2_CTL_VCO_SHIFT) | RNG_CTL_ES3; 345 break; 346 case 3: 347 val |= RNG_CTL_ES1 | RNG_CTL_ES2 | RNG_CTL_ES3; 348 break; 349 default: 350 break; 351 } 352 } 353 354 return val; 355 } 356 357 static void n2rng_control_swstate_init(struct n2rng *np) 358 { 359 int i; 360 361 np->flags |= N2RNG_FLAG_CONTROL; 362 363 np->health_check_sec = N2RNG_HEALTH_CHECK_SEC_DEFAULT; 364 np->accum_cycles = N2RNG_ACCUM_CYCLES_DEFAULT; 365 np->wd_timeo = N2RNG_WD_TIMEO_DEFAULT; 366 367 for (i = 0; i < np->num_units; i++) { 368 struct n2rng_unit *up = &np->units[i]; 369 370 up->control[0] = n2rng_control_default(np, 0); 371 up->control[1] = n2rng_control_default(np, 1); 372 up->control[2] = n2rng_control_default(np, 2); 373 up->control[3] = n2rng_control_default(np, 3); 374 } 375 376 np->hv_state = HV_RNG_STATE_UNCONFIGURED; 377 } 378 379 static int n2rng_grab_diag_control(struct n2rng *np) 380 { 381 int i, busy_count, err = -ENODEV; 382 383 busy_count = 0; 384 for (i = 0; i < 100; i++) { 385 err = n2rng_try_read_ctl(np); 386 if (err != -EAGAIN) 387 break; 388 389 if (++busy_count > 100) { 390 dev_err(&np->op->dev, 391 "Grab diag control timeout.\n"); 392 return -ENODEV; 393 } 394 395 udelay(1); 396 } 397 398 return err; 399 } 400 401 static int n2rng_init_control(struct n2rng *np) 402 { 403 int err = n2rng_grab_diag_control(np); 404 405 /* Not in the control domain, that's OK we are only a consumer 406 * of the RNG data, we don't setup and program it. 407 */ 408 if (err == -EPERM) 409 return 0; 410 if (err) 411 return err; 412 413 n2rng_control_swstate_init(np); 414 415 return 0; 416 } 417 418 static int n2rng_data_read(struct hwrng *rng, u32 *data) 419 { 420 struct n2rng *np = (struct n2rng *) rng->priv; 421 unsigned long ra = __pa(&np->test_data); 422 int len; 423 424 if (!(np->flags & N2RNG_FLAG_READY)) { 425 len = 0; 426 } else if (np->flags & N2RNG_FLAG_BUFFER_VALID) { 427 np->flags &= ~N2RNG_FLAG_BUFFER_VALID; 428 *data = np->buffer; 429 len = 4; 430 } else { 431 int err = n2rng_generic_read_data(ra); 432 if (!err) { 433 np->flags |= N2RNG_FLAG_BUFFER_VALID; 434 np->buffer = np->test_data >> 32; 435 *data = np->test_data & 0xffffffff; 436 len = 4; 437 } else { 438 dev_err(&np->op->dev, "RNG error, retesting\n"); 439 np->flags &= ~N2RNG_FLAG_READY; 440 if (!(np->flags & N2RNG_FLAG_SHUTDOWN)) 441 schedule_delayed_work(&np->work, 0); 442 len = 0; 443 } 444 } 445 446 return len; 447 } 448 449 /* On a guest node, just make sure we can read random data properly. 450 * If a control node reboots or reloads it's n2rng driver, this won't 451 * work during that time. So we have to keep probing until the device 452 * becomes usable. 453 */ 454 static int n2rng_guest_check(struct n2rng *np) 455 { 456 unsigned long ra = __pa(&np->test_data); 457 458 return n2rng_generic_read_data(ra); 459 } 460 461 static int n2rng_entropy_diag_read(struct n2rng *np, unsigned long unit, 462 u64 *pre_control, u64 pre_state, 463 u64 *buffer, unsigned long buf_len, 464 u64 *post_control, u64 post_state) 465 { 466 unsigned long post_ctl_ra = __pa(post_control); 467 unsigned long pre_ctl_ra = __pa(pre_control); 468 unsigned long buffer_ra = __pa(buffer); 469 int err; 470 471 err = n2rng_generic_write_control(np, pre_ctl_ra, unit, pre_state); 472 if (err) 473 return err; 474 475 err = n2rng_generic_read_diag_data(np, unit, 476 buffer_ra, buf_len); 477 478 (void) n2rng_generic_write_control(np, post_ctl_ra, unit, 479 post_state); 480 481 return err; 482 } 483 484 static u64 advance_polynomial(u64 poly, u64 val, int count) 485 { 486 int i; 487 488 for (i = 0; i < count; i++) { 489 int highbit_set = ((s64)val < 0); 490 491 val <<= 1; 492 if (highbit_set) 493 val ^= poly; 494 } 495 496 return val; 497 } 498 499 static int n2rng_test_buffer_find(struct n2rng *np, u64 val) 500 { 501 int i, count = 0; 502 503 /* Purposefully skip over the first word. */ 504 for (i = 1; i < SELFTEST_BUFFER_WORDS; i++) { 505 if (np->test_buffer[i] == val) 506 count++; 507 } 508 return count; 509 } 510 511 static void n2rng_dump_test_buffer(struct n2rng *np) 512 { 513 int i; 514 515 for (i = 0; i < SELFTEST_BUFFER_WORDS; i++) 516 dev_err(&np->op->dev, "Test buffer slot %d [0x%016llx]\n", 517 i, np->test_buffer[i]); 518 } 519 520 static int n2rng_check_selftest_buffer(struct n2rng *np, unsigned long unit) 521 { 522 u64 val; 523 int err, matches, limit; 524 525 switch (np->data->id) { 526 case N2_n2_rng: 527 case N2_vf_rng: 528 case N2_kt_rng: 529 case N2_m4_rng: /* yes, m4 uses the old value */ 530 val = RNG_v1_SELFTEST_VAL; 531 break; 532 default: 533 val = RNG_v2_SELFTEST_VAL; 534 break; 535 } 536 537 matches = 0; 538 for (limit = 0; limit < SELFTEST_LOOPS_MAX; limit++) { 539 matches += n2rng_test_buffer_find(np, val); 540 if (matches >= SELFTEST_MATCH_GOAL) 541 break; 542 val = advance_polynomial(SELFTEST_POLY, val, 1); 543 } 544 545 err = 0; 546 if (limit >= SELFTEST_LOOPS_MAX) { 547 err = -ENODEV; 548 dev_err(&np->op->dev, "Selftest failed on unit %lu\n", unit); 549 n2rng_dump_test_buffer(np); 550 } else 551 dev_info(&np->op->dev, "Selftest passed on unit %lu\n", unit); 552 553 return err; 554 } 555 556 static int n2rng_control_selftest(struct n2rng *np, unsigned long unit) 557 { 558 int err; 559 u64 base, base3; 560 561 switch (np->data->id) { 562 case N2_n2_rng: 563 case N2_vf_rng: 564 case N2_kt_rng: 565 base = RNG_v1_CTL_ASEL_NOOUT << RNG_v1_CTL_ASEL_SHIFT; 566 base3 = base | RNG_CTL_LFSR | 567 ((RNG_v1_SELFTEST_TICKS - 2) << RNG_v1_CTL_WAIT_SHIFT); 568 break; 569 case N2_m4_rng: 570 base = RNG_v2_CTL_ASEL_NOOUT << RNG_v2_CTL_ASEL_SHIFT; 571 base3 = base | RNG_CTL_LFSR | 572 ((RNG_v1_SELFTEST_TICKS - 2) << RNG_v2_CTL_WAIT_SHIFT); 573 break; 574 default: 575 base = RNG_v2_CTL_ASEL_NOOUT << RNG_v2_CTL_ASEL_SHIFT; 576 base3 = base | RNG_CTL_LFSR | 577 (RNG_v2_SELFTEST_TICKS << RNG_v2_CTL_WAIT_SHIFT); 578 break; 579 } 580 581 np->test_control[0] = base; 582 np->test_control[1] = base; 583 np->test_control[2] = base; 584 np->test_control[3] = base3; 585 586 err = n2rng_entropy_diag_read(np, unit, np->test_control, 587 HV_RNG_STATE_HEALTHCHECK, 588 np->test_buffer, 589 sizeof(np->test_buffer), 590 &np->units[unit].control[0], 591 np->hv_state); 592 if (err) 593 return err; 594 595 return n2rng_check_selftest_buffer(np, unit); 596 } 597 598 static int n2rng_control_check(struct n2rng *np) 599 { 600 int i; 601 602 for (i = 0; i < np->num_units; i++) { 603 int err = n2rng_control_selftest(np, i); 604 if (err) 605 return err; 606 } 607 return 0; 608 } 609 610 /* The sanity checks passed, install the final configuration into the 611 * chip, it's ready to use. 612 */ 613 static int n2rng_control_configure_units(struct n2rng *np) 614 { 615 int unit, err; 616 617 err = 0; 618 for (unit = 0; unit < np->num_units; unit++) { 619 struct n2rng_unit *up = &np->units[unit]; 620 unsigned long ctl_ra = __pa(&up->control[0]); 621 int esrc; 622 u64 base, shift; 623 624 if (np->data->chip_version == 1) { 625 base = ((np->accum_cycles << RNG_v1_CTL_WAIT_SHIFT) | 626 (RNG_v1_CTL_ASEL_NOOUT << RNG_v1_CTL_ASEL_SHIFT) | 627 RNG_CTL_LFSR); 628 shift = RNG_v1_CTL_VCO_SHIFT; 629 } else { 630 base = ((np->accum_cycles << RNG_v2_CTL_WAIT_SHIFT) | 631 (RNG_v2_CTL_ASEL_NOOUT << RNG_v2_CTL_ASEL_SHIFT) | 632 RNG_CTL_LFSR); 633 shift = RNG_v2_CTL_VCO_SHIFT; 634 } 635 636 /* XXX This isn't the best. We should fetch a bunch 637 * XXX of words using each entropy source combined XXX 638 * with each VCO setting, and see which combinations 639 * XXX give the best random data. 640 */ 641 for (esrc = 0; esrc < 3; esrc++) 642 up->control[esrc] = base | 643 (esrc << shift) | 644 (RNG_CTL_ES1 << esrc); 645 646 up->control[3] = base | 647 (RNG_CTL_ES1 | RNG_CTL_ES2 | RNG_CTL_ES3); 648 649 err = n2rng_generic_write_control(np, ctl_ra, unit, 650 HV_RNG_STATE_CONFIGURED); 651 if (err) 652 break; 653 } 654 655 return err; 656 } 657 658 static void n2rng_work(struct work_struct *work) 659 { 660 struct n2rng *np = container_of(work, struct n2rng, work.work); 661 int err = 0; 662 static int retries = 4; 663 664 if (!(np->flags & N2RNG_FLAG_CONTROL)) { 665 err = n2rng_guest_check(np); 666 } else { 667 preempt_disable(); 668 err = n2rng_control_check(np); 669 preempt_enable(); 670 671 if (!err) 672 err = n2rng_control_configure_units(np); 673 } 674 675 if (!err) { 676 np->flags |= N2RNG_FLAG_READY; 677 dev_info(&np->op->dev, "RNG ready\n"); 678 } 679 680 if (--retries == 0) 681 dev_err(&np->op->dev, "Self-test retries failed, RNG not ready\n"); 682 else if (err && !(np->flags & N2RNG_FLAG_SHUTDOWN)) 683 schedule_delayed_work(&np->work, HZ * 2); 684 } 685 686 static void n2rng_driver_version(void) 687 { 688 static int n2rng_version_printed; 689 690 if (n2rng_version_printed++ == 0) 691 pr_info("%s", version); 692 } 693 694 static const struct of_device_id n2rng_match[]; 695 static int n2rng_probe(struct platform_device *op) 696 { 697 const struct of_device_id *match; 698 int err = -ENOMEM; 699 struct n2rng *np; 700 701 match = of_match_device(n2rng_match, &op->dev); 702 if (!match) 703 return -EINVAL; 704 705 n2rng_driver_version(); 706 np = devm_kzalloc(&op->dev, sizeof(*np), GFP_KERNEL); 707 if (!np) 708 goto out; 709 np->op = op; 710 np->data = (struct n2rng_template *)match->data; 711 712 INIT_DELAYED_WORK(&np->work, n2rng_work); 713 714 if (np->data->multi_capable) 715 np->flags |= N2RNG_FLAG_MULTI; 716 717 err = -ENODEV; 718 np->hvapi_major = 2; 719 if (sun4v_hvapi_register(HV_GRP_RNG, 720 np->hvapi_major, 721 &np->hvapi_minor)) { 722 np->hvapi_major = 1; 723 if (sun4v_hvapi_register(HV_GRP_RNG, 724 np->hvapi_major, 725 &np->hvapi_minor)) { 726 dev_err(&op->dev, "Cannot register suitable " 727 "HVAPI version.\n"); 728 goto out; 729 } 730 } 731 732 if (np->flags & N2RNG_FLAG_MULTI) { 733 if (np->hvapi_major < 2) { 734 dev_err(&op->dev, "multi-unit-capable RNG requires " 735 "HVAPI major version 2 or later, got %lu\n", 736 np->hvapi_major); 737 goto out_hvapi_unregister; 738 } 739 np->num_units = of_getintprop_default(op->dev.of_node, 740 "rng-#units", 0); 741 if (!np->num_units) { 742 dev_err(&op->dev, "VF RNG lacks rng-#units property\n"); 743 goto out_hvapi_unregister; 744 } 745 } else { 746 np->num_units = 1; 747 } 748 749 dev_info(&op->dev, "Registered RNG HVAPI major %lu minor %lu\n", 750 np->hvapi_major, np->hvapi_minor); 751 np->units = devm_kcalloc(&op->dev, np->num_units, sizeof(*np->units), 752 GFP_KERNEL); 753 err = -ENOMEM; 754 if (!np->units) 755 goto out_hvapi_unregister; 756 757 err = n2rng_init_control(np); 758 if (err) 759 goto out_hvapi_unregister; 760 761 dev_info(&op->dev, "Found %s RNG, units: %d\n", 762 ((np->flags & N2RNG_FLAG_MULTI) ? 763 "multi-unit-capable" : "single-unit"), 764 np->num_units); 765 766 np->hwrng.name = DRV_MODULE_NAME; 767 np->hwrng.data_read = n2rng_data_read; 768 np->hwrng.priv = (unsigned long) np; 769 770 err = hwrng_register(&np->hwrng); 771 if (err) 772 goto out_hvapi_unregister; 773 774 platform_set_drvdata(op, np); 775 776 schedule_delayed_work(&np->work, 0); 777 778 return 0; 779 780 out_hvapi_unregister: 781 sun4v_hvapi_unregister(HV_GRP_RNG); 782 783 out: 784 return err; 785 } 786 787 static int n2rng_remove(struct platform_device *op) 788 { 789 struct n2rng *np = platform_get_drvdata(op); 790 791 np->flags |= N2RNG_FLAG_SHUTDOWN; 792 793 cancel_delayed_work_sync(&np->work); 794 795 hwrng_unregister(&np->hwrng); 796 797 sun4v_hvapi_unregister(HV_GRP_RNG); 798 799 return 0; 800 } 801 802 static struct n2rng_template n2_template = { 803 .id = N2_n2_rng, 804 .multi_capable = 0, 805 .chip_version = 1, 806 }; 807 808 static struct n2rng_template vf_template = { 809 .id = N2_vf_rng, 810 .multi_capable = 1, 811 .chip_version = 1, 812 }; 813 814 static struct n2rng_template kt_template = { 815 .id = N2_kt_rng, 816 .multi_capable = 1, 817 .chip_version = 1, 818 }; 819 820 static struct n2rng_template m4_template = { 821 .id = N2_m4_rng, 822 .multi_capable = 1, 823 .chip_version = 2, 824 }; 825 826 static struct n2rng_template m7_template = { 827 .id = N2_m7_rng, 828 .multi_capable = 1, 829 .chip_version = 2, 830 }; 831 832 static const struct of_device_id n2rng_match[] = { 833 { 834 .name = "random-number-generator", 835 .compatible = "SUNW,n2-rng", 836 .data = &n2_template, 837 }, 838 { 839 .name = "random-number-generator", 840 .compatible = "SUNW,vf-rng", 841 .data = &vf_template, 842 }, 843 { 844 .name = "random-number-generator", 845 .compatible = "SUNW,kt-rng", 846 .data = &kt_template, 847 }, 848 { 849 .name = "random-number-generator", 850 .compatible = "ORCL,m4-rng", 851 .data = &m4_template, 852 }, 853 { 854 .name = "random-number-generator", 855 .compatible = "ORCL,m7-rng", 856 .data = &m7_template, 857 }, 858 {}, 859 }; 860 MODULE_DEVICE_TABLE(of, n2rng_match); 861 862 static struct platform_driver n2rng_driver = { 863 .driver = { 864 .name = "n2rng", 865 .of_match_table = n2rng_match, 866 }, 867 .probe = n2rng_probe, 868 .remove = n2rng_remove, 869 }; 870 871 module_platform_driver(n2rng_driver); 872