1 // SPDX-License-Identifier: GPL-2.0-only 2 /* n2-drv.c: Niagara-2 RNG driver. 3 * 4 * Copyright (C) 2008, 2011 David S. Miller <davem@davemloft.net> 5 */ 6 7 #include <linux/kernel.h> 8 #include <linux/module.h> 9 #include <linux/types.h> 10 #include <linux/delay.h> 11 #include <linux/slab.h> 12 #include <linux/workqueue.h> 13 #include <linux/preempt.h> 14 #include <linux/hw_random.h> 15 16 #include <linux/of.h> 17 #include <linux/of_device.h> 18 19 #include <asm/hypervisor.h> 20 21 #include "n2rng.h" 22 23 #define DRV_MODULE_NAME "n2rng" 24 #define PFX DRV_MODULE_NAME ": " 25 #define DRV_MODULE_VERSION "0.3" 26 #define DRV_MODULE_RELDATE "Jan 7, 2017" 27 28 static char version[] = 29 DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; 30 31 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)"); 32 MODULE_DESCRIPTION("Niagara2 RNG driver"); 33 MODULE_LICENSE("GPL"); 34 MODULE_VERSION(DRV_MODULE_VERSION); 35 36 /* The Niagara2 RNG provides a 64-bit read-only random number 37 * register, plus a control register. Access to the RNG is 38 * virtualized through the hypervisor so that both guests and control 39 * nodes can access the device. 40 * 41 * The entropy source consists of raw entropy sources, each 42 * constructed from a voltage controlled oscillator whose phase is 43 * jittered by thermal noise sources. 44 * 45 * The oscillator in each of the three raw entropy sources run at 46 * different frequencies. Normally, all three generator outputs are 47 * gathered, xored together, and fed into a CRC circuit, the output of 48 * which is the 64-bit read-only register. 49 * 50 * Some time is necessary for all the necessary entropy to build up 51 * such that a full 64-bits of entropy are available in the register. 52 * In normal operating mode (RNG_CTL_LFSR is set), the chip implements 53 * an interlock which blocks register reads until sufficient entropy 54 * is available. 55 * 56 * A control register is provided for adjusting various aspects of RNG 57 * operation, and to enable diagnostic modes. Each of the three raw 58 * entropy sources has an enable bit (RNG_CTL_ES{1,2,3}). Also 59 * provided are fields for controlling the minimum time in cycles 60 * between read accesses to the register (RNG_CTL_WAIT, this controls 61 * the interlock described in the previous paragraph). 62 * 63 * The standard setting is to have the mode bit (RNG_CTL_LFSR) set, 64 * all three entropy sources enabled, and the interlock time set 65 * appropriately. 66 * 67 * The CRC polynomial used by the chip is: 68 * 69 * P(X) = x64 + x61 + x57 + x56 + x52 + x51 + x50 + x48 + x47 + x46 + 70 * x43 + x42 + x41 + x39 + x38 + x37 + x35 + x32 + x28 + x25 + 71 * x22 + x21 + x17 + x15 + x13 + x12 + x11 + x7 + x5 + x + 1 72 * 73 * The RNG_CTL_VCO value of each noise cell must be programmed 74 * separately. This is why 4 control register values must be provided 75 * to the hypervisor. During a write, the hypervisor writes them all, 76 * one at a time, to the actual RNG_CTL register. The first three 77 * values are used to setup the desired RNG_CTL_VCO for each entropy 78 * source, for example: 79 * 80 * control 0: (1 << RNG_CTL_VCO_SHIFT) | RNG_CTL_ES1 81 * control 1: (2 << RNG_CTL_VCO_SHIFT) | RNG_CTL_ES2 82 * control 2: (3 << RNG_CTL_VCO_SHIFT) | RNG_CTL_ES3 83 * 84 * And then the fourth value sets the final chip state and enables 85 * desired. 86 */ 87 88 static int n2rng_hv_err_trans(unsigned long hv_err) 89 { 90 switch (hv_err) { 91 case HV_EOK: 92 return 0; 93 case HV_EWOULDBLOCK: 94 return -EAGAIN; 95 case HV_ENOACCESS: 96 return -EPERM; 97 case HV_EIO: 98 return -EIO; 99 case HV_EBUSY: 100 return -EBUSY; 101 case HV_EBADALIGN: 102 case HV_ENORADDR: 103 return -EFAULT; 104 default: 105 return -EINVAL; 106 } 107 } 108 109 static unsigned long n2rng_generic_read_control_v2(unsigned long ra, 110 unsigned long unit) 111 { 112 unsigned long hv_err, state, ticks, watchdog_delta, watchdog_status; 113 int block = 0, busy = 0; 114 115 while (1) { 116 hv_err = sun4v_rng_ctl_read_v2(ra, unit, &state, 117 &ticks, 118 &watchdog_delta, 119 &watchdog_status); 120 if (hv_err == HV_EOK) 121 break; 122 123 if (hv_err == HV_EBUSY) { 124 if (++busy >= N2RNG_BUSY_LIMIT) 125 break; 126 127 udelay(1); 128 } else if (hv_err == HV_EWOULDBLOCK) { 129 if (++block >= N2RNG_BLOCK_LIMIT) 130 break; 131 132 __delay(ticks); 133 } else 134 break; 135 } 136 137 return hv_err; 138 } 139 140 /* In multi-socket situations, the hypervisor might need to 141 * queue up the RNG control register write if it's for a unit 142 * that is on a cpu socket other than the one we are executing on. 143 * 144 * We poll here waiting for a successful read of that control 145 * register to make sure the write has been actually performed. 146 */ 147 static unsigned long n2rng_control_settle_v2(struct n2rng *np, int unit) 148 { 149 unsigned long ra = __pa(&np->scratch_control[0]); 150 151 return n2rng_generic_read_control_v2(ra, unit); 152 } 153 154 static unsigned long n2rng_write_ctl_one(struct n2rng *np, int unit, 155 unsigned long state, 156 unsigned long control_ra, 157 unsigned long watchdog_timeout, 158 unsigned long *ticks) 159 { 160 unsigned long hv_err; 161 162 if (np->hvapi_major == 1) { 163 hv_err = sun4v_rng_ctl_write_v1(control_ra, state, 164 watchdog_timeout, ticks); 165 } else { 166 hv_err = sun4v_rng_ctl_write_v2(control_ra, state, 167 watchdog_timeout, unit); 168 if (hv_err == HV_EOK) 169 hv_err = n2rng_control_settle_v2(np, unit); 170 *ticks = N2RNG_ACCUM_CYCLES_DEFAULT; 171 } 172 173 return hv_err; 174 } 175 176 static int n2rng_generic_read_data(unsigned long data_ra) 177 { 178 unsigned long ticks, hv_err; 179 int block = 0, hcheck = 0; 180 181 while (1) { 182 hv_err = sun4v_rng_data_read(data_ra, &ticks); 183 if (hv_err == HV_EOK) 184 return 0; 185 186 if (hv_err == HV_EWOULDBLOCK) { 187 if (++block >= N2RNG_BLOCK_LIMIT) 188 return -EWOULDBLOCK; 189 __delay(ticks); 190 } else if (hv_err == HV_ENOACCESS) { 191 return -EPERM; 192 } else if (hv_err == HV_EIO) { 193 if (++hcheck >= N2RNG_HCHECK_LIMIT) 194 return -EIO; 195 udelay(10000); 196 } else 197 return -ENODEV; 198 } 199 } 200 201 static unsigned long n2rng_read_diag_data_one(struct n2rng *np, 202 unsigned long unit, 203 unsigned long data_ra, 204 unsigned long data_len, 205 unsigned long *ticks) 206 { 207 unsigned long hv_err; 208 209 if (np->hvapi_major == 1) { 210 hv_err = sun4v_rng_data_read_diag_v1(data_ra, data_len, ticks); 211 } else { 212 hv_err = sun4v_rng_data_read_diag_v2(data_ra, data_len, 213 unit, ticks); 214 if (!*ticks) 215 *ticks = N2RNG_ACCUM_CYCLES_DEFAULT; 216 } 217 return hv_err; 218 } 219 220 static int n2rng_generic_read_diag_data(struct n2rng *np, 221 unsigned long unit, 222 unsigned long data_ra, 223 unsigned long data_len) 224 { 225 unsigned long ticks, hv_err; 226 int block = 0; 227 228 while (1) { 229 hv_err = n2rng_read_diag_data_one(np, unit, 230 data_ra, data_len, 231 &ticks); 232 if (hv_err == HV_EOK) 233 return 0; 234 235 if (hv_err == HV_EWOULDBLOCK) { 236 if (++block >= N2RNG_BLOCK_LIMIT) 237 return -EWOULDBLOCK; 238 __delay(ticks); 239 } else if (hv_err == HV_ENOACCESS) { 240 return -EPERM; 241 } else if (hv_err == HV_EIO) { 242 return -EIO; 243 } else 244 return -ENODEV; 245 } 246 } 247 248 249 static int n2rng_generic_write_control(struct n2rng *np, 250 unsigned long control_ra, 251 unsigned long unit, 252 unsigned long state) 253 { 254 unsigned long hv_err, ticks; 255 int block = 0, busy = 0; 256 257 while (1) { 258 hv_err = n2rng_write_ctl_one(np, unit, state, control_ra, 259 np->wd_timeo, &ticks); 260 if (hv_err == HV_EOK) 261 return 0; 262 263 if (hv_err == HV_EWOULDBLOCK) { 264 if (++block >= N2RNG_BLOCK_LIMIT) 265 return -EWOULDBLOCK; 266 __delay(ticks); 267 } else if (hv_err == HV_EBUSY) { 268 if (++busy >= N2RNG_BUSY_LIMIT) 269 return -EBUSY; 270 udelay(1); 271 } else 272 return -ENODEV; 273 } 274 } 275 276 /* Just try to see if we can successfully access the control register 277 * of the RNG on the domain on which we are currently executing. 278 */ 279 static int n2rng_try_read_ctl(struct n2rng *np) 280 { 281 unsigned long hv_err; 282 unsigned long x; 283 284 if (np->hvapi_major == 1) { 285 hv_err = sun4v_rng_get_diag_ctl(); 286 } else { 287 /* We purposefully give invalid arguments, HV_NOACCESS 288 * is higher priority than the errors we'd get from 289 * these other cases, and that's the error we are 290 * truly interested in. 291 */ 292 hv_err = sun4v_rng_ctl_read_v2(0UL, ~0UL, &x, &x, &x, &x); 293 switch (hv_err) { 294 case HV_EWOULDBLOCK: 295 case HV_ENOACCESS: 296 break; 297 default: 298 hv_err = HV_EOK; 299 break; 300 } 301 } 302 303 return n2rng_hv_err_trans(hv_err); 304 } 305 306 static u64 n2rng_control_default(struct n2rng *np, int ctl) 307 { 308 u64 val = 0; 309 310 if (np->data->chip_version == 1) { 311 val = ((2 << RNG_v1_CTL_ASEL_SHIFT) | 312 (N2RNG_ACCUM_CYCLES_DEFAULT << RNG_v1_CTL_WAIT_SHIFT) | 313 RNG_CTL_LFSR); 314 315 switch (ctl) { 316 case 0: 317 val |= (1 << RNG_v1_CTL_VCO_SHIFT) | RNG_CTL_ES1; 318 break; 319 case 1: 320 val |= (2 << RNG_v1_CTL_VCO_SHIFT) | RNG_CTL_ES2; 321 break; 322 case 2: 323 val |= (3 << RNG_v1_CTL_VCO_SHIFT) | RNG_CTL_ES3; 324 break; 325 case 3: 326 val |= RNG_CTL_ES1 | RNG_CTL_ES2 | RNG_CTL_ES3; 327 break; 328 default: 329 break; 330 } 331 332 } else { 333 val = ((2 << RNG_v2_CTL_ASEL_SHIFT) | 334 (N2RNG_ACCUM_CYCLES_DEFAULT << RNG_v2_CTL_WAIT_SHIFT) | 335 RNG_CTL_LFSR); 336 337 switch (ctl) { 338 case 0: 339 val |= (1 << RNG_v2_CTL_VCO_SHIFT) | RNG_CTL_ES1; 340 break; 341 case 1: 342 val |= (2 << RNG_v2_CTL_VCO_SHIFT) | RNG_CTL_ES2; 343 break; 344 case 2: 345 val |= (3 << RNG_v2_CTL_VCO_SHIFT) | RNG_CTL_ES3; 346 break; 347 case 3: 348 val |= RNG_CTL_ES1 | RNG_CTL_ES2 | RNG_CTL_ES3; 349 break; 350 default: 351 break; 352 } 353 } 354 355 return val; 356 } 357 358 static void n2rng_control_swstate_init(struct n2rng *np) 359 { 360 int i; 361 362 np->flags |= N2RNG_FLAG_CONTROL; 363 364 np->health_check_sec = N2RNG_HEALTH_CHECK_SEC_DEFAULT; 365 np->accum_cycles = N2RNG_ACCUM_CYCLES_DEFAULT; 366 np->wd_timeo = N2RNG_WD_TIMEO_DEFAULT; 367 368 for (i = 0; i < np->num_units; i++) { 369 struct n2rng_unit *up = &np->units[i]; 370 371 up->control[0] = n2rng_control_default(np, 0); 372 up->control[1] = n2rng_control_default(np, 1); 373 up->control[2] = n2rng_control_default(np, 2); 374 up->control[3] = n2rng_control_default(np, 3); 375 } 376 377 np->hv_state = HV_RNG_STATE_UNCONFIGURED; 378 } 379 380 static int n2rng_grab_diag_control(struct n2rng *np) 381 { 382 int i, busy_count, err = -ENODEV; 383 384 busy_count = 0; 385 for (i = 0; i < 100; i++) { 386 err = n2rng_try_read_ctl(np); 387 if (err != -EAGAIN) 388 break; 389 390 if (++busy_count > 100) { 391 dev_err(&np->op->dev, 392 "Grab diag control timeout.\n"); 393 return -ENODEV; 394 } 395 396 udelay(1); 397 } 398 399 return err; 400 } 401 402 static int n2rng_init_control(struct n2rng *np) 403 { 404 int err = n2rng_grab_diag_control(np); 405 406 /* Not in the control domain, that's OK we are only a consumer 407 * of the RNG data, we don't setup and program it. 408 */ 409 if (err == -EPERM) 410 return 0; 411 if (err) 412 return err; 413 414 n2rng_control_swstate_init(np); 415 416 return 0; 417 } 418 419 static int n2rng_data_read(struct hwrng *rng, u32 *data) 420 { 421 struct n2rng *np = (struct n2rng *) rng->priv; 422 unsigned long ra = __pa(&np->test_data); 423 int len; 424 425 if (!(np->flags & N2RNG_FLAG_READY)) { 426 len = 0; 427 } else if (np->flags & N2RNG_FLAG_BUFFER_VALID) { 428 np->flags &= ~N2RNG_FLAG_BUFFER_VALID; 429 *data = np->buffer; 430 len = 4; 431 } else { 432 int err = n2rng_generic_read_data(ra); 433 if (!err) { 434 np->flags |= N2RNG_FLAG_BUFFER_VALID; 435 np->buffer = np->test_data >> 32; 436 *data = np->test_data & 0xffffffff; 437 len = 4; 438 } else { 439 dev_err(&np->op->dev, "RNG error, retesting\n"); 440 np->flags &= ~N2RNG_FLAG_READY; 441 if (!(np->flags & N2RNG_FLAG_SHUTDOWN)) 442 schedule_delayed_work(&np->work, 0); 443 len = 0; 444 } 445 } 446 447 return len; 448 } 449 450 /* On a guest node, just make sure we can read random data properly. 451 * If a control node reboots or reloads it's n2rng driver, this won't 452 * work during that time. So we have to keep probing until the device 453 * becomes usable. 454 */ 455 static int n2rng_guest_check(struct n2rng *np) 456 { 457 unsigned long ra = __pa(&np->test_data); 458 459 return n2rng_generic_read_data(ra); 460 } 461 462 static int n2rng_entropy_diag_read(struct n2rng *np, unsigned long unit, 463 u64 *pre_control, u64 pre_state, 464 u64 *buffer, unsigned long buf_len, 465 u64 *post_control, u64 post_state) 466 { 467 unsigned long post_ctl_ra = __pa(post_control); 468 unsigned long pre_ctl_ra = __pa(pre_control); 469 unsigned long buffer_ra = __pa(buffer); 470 int err; 471 472 err = n2rng_generic_write_control(np, pre_ctl_ra, unit, pre_state); 473 if (err) 474 return err; 475 476 err = n2rng_generic_read_diag_data(np, unit, 477 buffer_ra, buf_len); 478 479 (void) n2rng_generic_write_control(np, post_ctl_ra, unit, 480 post_state); 481 482 return err; 483 } 484 485 static u64 advance_polynomial(u64 poly, u64 val, int count) 486 { 487 int i; 488 489 for (i = 0; i < count; i++) { 490 int highbit_set = ((s64)val < 0); 491 492 val <<= 1; 493 if (highbit_set) 494 val ^= poly; 495 } 496 497 return val; 498 } 499 500 static int n2rng_test_buffer_find(struct n2rng *np, u64 val) 501 { 502 int i, count = 0; 503 504 /* Purposefully skip over the first word. */ 505 for (i = 1; i < SELFTEST_BUFFER_WORDS; i++) { 506 if (np->test_buffer[i] == val) 507 count++; 508 } 509 return count; 510 } 511 512 static void n2rng_dump_test_buffer(struct n2rng *np) 513 { 514 int i; 515 516 for (i = 0; i < SELFTEST_BUFFER_WORDS; i++) 517 dev_err(&np->op->dev, "Test buffer slot %d [0x%016llx]\n", 518 i, np->test_buffer[i]); 519 } 520 521 static int n2rng_check_selftest_buffer(struct n2rng *np, unsigned long unit) 522 { 523 u64 val; 524 int err, matches, limit; 525 526 switch (np->data->id) { 527 case N2_n2_rng: 528 case N2_vf_rng: 529 case N2_kt_rng: 530 case N2_m4_rng: /* yes, m4 uses the old value */ 531 val = RNG_v1_SELFTEST_VAL; 532 break; 533 default: 534 val = RNG_v2_SELFTEST_VAL; 535 break; 536 } 537 538 matches = 0; 539 for (limit = 0; limit < SELFTEST_LOOPS_MAX; limit++) { 540 matches += n2rng_test_buffer_find(np, val); 541 if (matches >= SELFTEST_MATCH_GOAL) 542 break; 543 val = advance_polynomial(SELFTEST_POLY, val, 1); 544 } 545 546 err = 0; 547 if (limit >= SELFTEST_LOOPS_MAX) { 548 err = -ENODEV; 549 dev_err(&np->op->dev, "Selftest failed on unit %lu\n", unit); 550 n2rng_dump_test_buffer(np); 551 } else 552 dev_info(&np->op->dev, "Selftest passed on unit %lu\n", unit); 553 554 return err; 555 } 556 557 static int n2rng_control_selftest(struct n2rng *np, unsigned long unit) 558 { 559 int err; 560 u64 base, base3; 561 562 switch (np->data->id) { 563 case N2_n2_rng: 564 case N2_vf_rng: 565 case N2_kt_rng: 566 base = RNG_v1_CTL_ASEL_NOOUT << RNG_v1_CTL_ASEL_SHIFT; 567 base3 = base | RNG_CTL_LFSR | 568 ((RNG_v1_SELFTEST_TICKS - 2) << RNG_v1_CTL_WAIT_SHIFT); 569 break; 570 case N2_m4_rng: 571 base = RNG_v2_CTL_ASEL_NOOUT << RNG_v2_CTL_ASEL_SHIFT; 572 base3 = base | RNG_CTL_LFSR | 573 ((RNG_v1_SELFTEST_TICKS - 2) << RNG_v2_CTL_WAIT_SHIFT); 574 break; 575 default: 576 base = RNG_v2_CTL_ASEL_NOOUT << RNG_v2_CTL_ASEL_SHIFT; 577 base3 = base | RNG_CTL_LFSR | 578 (RNG_v2_SELFTEST_TICKS << RNG_v2_CTL_WAIT_SHIFT); 579 break; 580 } 581 582 np->test_control[0] = base; 583 np->test_control[1] = base; 584 np->test_control[2] = base; 585 np->test_control[3] = base3; 586 587 err = n2rng_entropy_diag_read(np, unit, np->test_control, 588 HV_RNG_STATE_HEALTHCHECK, 589 np->test_buffer, 590 sizeof(np->test_buffer), 591 &np->units[unit].control[0], 592 np->hv_state); 593 if (err) 594 return err; 595 596 return n2rng_check_selftest_buffer(np, unit); 597 } 598 599 static int n2rng_control_check(struct n2rng *np) 600 { 601 int i; 602 603 for (i = 0; i < np->num_units; i++) { 604 int err = n2rng_control_selftest(np, i); 605 if (err) 606 return err; 607 } 608 return 0; 609 } 610 611 /* The sanity checks passed, install the final configuration into the 612 * chip, it's ready to use. 613 */ 614 static int n2rng_control_configure_units(struct n2rng *np) 615 { 616 int unit, err; 617 618 err = 0; 619 for (unit = 0; unit < np->num_units; unit++) { 620 struct n2rng_unit *up = &np->units[unit]; 621 unsigned long ctl_ra = __pa(&up->control[0]); 622 int esrc; 623 u64 base, shift; 624 625 if (np->data->chip_version == 1) { 626 base = ((np->accum_cycles << RNG_v1_CTL_WAIT_SHIFT) | 627 (RNG_v1_CTL_ASEL_NOOUT << RNG_v1_CTL_ASEL_SHIFT) | 628 RNG_CTL_LFSR); 629 shift = RNG_v1_CTL_VCO_SHIFT; 630 } else { 631 base = ((np->accum_cycles << RNG_v2_CTL_WAIT_SHIFT) | 632 (RNG_v2_CTL_ASEL_NOOUT << RNG_v2_CTL_ASEL_SHIFT) | 633 RNG_CTL_LFSR); 634 shift = RNG_v2_CTL_VCO_SHIFT; 635 } 636 637 /* XXX This isn't the best. We should fetch a bunch 638 * XXX of words using each entropy source combined XXX 639 * with each VCO setting, and see which combinations 640 * XXX give the best random data. 641 */ 642 for (esrc = 0; esrc < 3; esrc++) 643 up->control[esrc] = base | 644 (esrc << shift) | 645 (RNG_CTL_ES1 << esrc); 646 647 up->control[3] = base | 648 (RNG_CTL_ES1 | RNG_CTL_ES2 | RNG_CTL_ES3); 649 650 err = n2rng_generic_write_control(np, ctl_ra, unit, 651 HV_RNG_STATE_CONFIGURED); 652 if (err) 653 break; 654 } 655 656 return err; 657 } 658 659 static void n2rng_work(struct work_struct *work) 660 { 661 struct n2rng *np = container_of(work, struct n2rng, work.work); 662 int err = 0; 663 static int retries = 4; 664 665 if (!(np->flags & N2RNG_FLAG_CONTROL)) { 666 err = n2rng_guest_check(np); 667 } else { 668 preempt_disable(); 669 err = n2rng_control_check(np); 670 preempt_enable(); 671 672 if (!err) 673 err = n2rng_control_configure_units(np); 674 } 675 676 if (!err) { 677 np->flags |= N2RNG_FLAG_READY; 678 dev_info(&np->op->dev, "RNG ready\n"); 679 } 680 681 if (--retries == 0) 682 dev_err(&np->op->dev, "Self-test retries failed, RNG not ready\n"); 683 else if (err && !(np->flags & N2RNG_FLAG_SHUTDOWN)) 684 schedule_delayed_work(&np->work, HZ * 2); 685 } 686 687 static void n2rng_driver_version(void) 688 { 689 static int n2rng_version_printed; 690 691 if (n2rng_version_printed++ == 0) 692 pr_info("%s", version); 693 } 694 695 static const struct of_device_id n2rng_match[]; 696 static int n2rng_probe(struct platform_device *op) 697 { 698 const struct of_device_id *match; 699 int err = -ENOMEM; 700 struct n2rng *np; 701 702 match = of_match_device(n2rng_match, &op->dev); 703 if (!match) 704 return -EINVAL; 705 706 n2rng_driver_version(); 707 np = devm_kzalloc(&op->dev, sizeof(*np), GFP_KERNEL); 708 if (!np) 709 goto out; 710 np->op = op; 711 np->data = (struct n2rng_template *)match->data; 712 713 INIT_DELAYED_WORK(&np->work, n2rng_work); 714 715 if (np->data->multi_capable) 716 np->flags |= N2RNG_FLAG_MULTI; 717 718 err = -ENODEV; 719 np->hvapi_major = 2; 720 if (sun4v_hvapi_register(HV_GRP_RNG, 721 np->hvapi_major, 722 &np->hvapi_minor)) { 723 np->hvapi_major = 1; 724 if (sun4v_hvapi_register(HV_GRP_RNG, 725 np->hvapi_major, 726 &np->hvapi_minor)) { 727 dev_err(&op->dev, "Cannot register suitable " 728 "HVAPI version.\n"); 729 goto out; 730 } 731 } 732 733 if (np->flags & N2RNG_FLAG_MULTI) { 734 if (np->hvapi_major < 2) { 735 dev_err(&op->dev, "multi-unit-capable RNG requires " 736 "HVAPI major version 2 or later, got %lu\n", 737 np->hvapi_major); 738 goto out_hvapi_unregister; 739 } 740 np->num_units = of_getintprop_default(op->dev.of_node, 741 "rng-#units", 0); 742 if (!np->num_units) { 743 dev_err(&op->dev, "VF RNG lacks rng-#units property\n"); 744 goto out_hvapi_unregister; 745 } 746 } else { 747 np->num_units = 1; 748 } 749 750 dev_info(&op->dev, "Registered RNG HVAPI major %lu minor %lu\n", 751 np->hvapi_major, np->hvapi_minor); 752 np->units = devm_kcalloc(&op->dev, np->num_units, sizeof(*np->units), 753 GFP_KERNEL); 754 err = -ENOMEM; 755 if (!np->units) 756 goto out_hvapi_unregister; 757 758 err = n2rng_init_control(np); 759 if (err) 760 goto out_hvapi_unregister; 761 762 dev_info(&op->dev, "Found %s RNG, units: %d\n", 763 ((np->flags & N2RNG_FLAG_MULTI) ? 764 "multi-unit-capable" : "single-unit"), 765 np->num_units); 766 767 np->hwrng.name = DRV_MODULE_NAME; 768 np->hwrng.data_read = n2rng_data_read; 769 np->hwrng.priv = (unsigned long) np; 770 771 err = devm_hwrng_register(&op->dev, &np->hwrng); 772 if (err) 773 goto out_hvapi_unregister; 774 775 platform_set_drvdata(op, np); 776 777 schedule_delayed_work(&np->work, 0); 778 779 return 0; 780 781 out_hvapi_unregister: 782 sun4v_hvapi_unregister(HV_GRP_RNG); 783 784 out: 785 return err; 786 } 787 788 static int n2rng_remove(struct platform_device *op) 789 { 790 struct n2rng *np = platform_get_drvdata(op); 791 792 np->flags |= N2RNG_FLAG_SHUTDOWN; 793 794 cancel_delayed_work_sync(&np->work); 795 796 sun4v_hvapi_unregister(HV_GRP_RNG); 797 798 return 0; 799 } 800 801 static struct n2rng_template n2_template = { 802 .id = N2_n2_rng, 803 .multi_capable = 0, 804 .chip_version = 1, 805 }; 806 807 static struct n2rng_template vf_template = { 808 .id = N2_vf_rng, 809 .multi_capable = 1, 810 .chip_version = 1, 811 }; 812 813 static struct n2rng_template kt_template = { 814 .id = N2_kt_rng, 815 .multi_capable = 1, 816 .chip_version = 1, 817 }; 818 819 static struct n2rng_template m4_template = { 820 .id = N2_m4_rng, 821 .multi_capable = 1, 822 .chip_version = 2, 823 }; 824 825 static struct n2rng_template m7_template = { 826 .id = N2_m7_rng, 827 .multi_capable = 1, 828 .chip_version = 2, 829 }; 830 831 static const struct of_device_id n2rng_match[] = { 832 { 833 .name = "random-number-generator", 834 .compatible = "SUNW,n2-rng", 835 .data = &n2_template, 836 }, 837 { 838 .name = "random-number-generator", 839 .compatible = "SUNW,vf-rng", 840 .data = &vf_template, 841 }, 842 { 843 .name = "random-number-generator", 844 .compatible = "SUNW,kt-rng", 845 .data = &kt_template, 846 }, 847 { 848 .name = "random-number-generator", 849 .compatible = "ORCL,m4-rng", 850 .data = &m4_template, 851 }, 852 { 853 .name = "random-number-generator", 854 .compatible = "ORCL,m7-rng", 855 .data = &m7_template, 856 }, 857 {}, 858 }; 859 MODULE_DEVICE_TABLE(of, n2rng_match); 860 861 static struct platform_driver n2rng_driver = { 862 .driver = { 863 .name = "n2rng", 864 .of_match_table = n2rng_match, 865 }, 866 .probe = n2rng_probe, 867 .remove = n2rng_remove, 868 }; 869 870 module_platform_driver(n2rng_driver); 871