1 /* 2 * Copyright (C) 2015 Broadcom Corporation 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation version 2. 7 * 8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 9 * kind, whether express or implied; without even the implied warranty 10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 /* 14 * DESCRIPTION: The Broadcom iProc RNG200 Driver 15 */ 16 17 #include <linux/hw_random.h> 18 #include <linux/init.h> 19 #include <linux/io.h> 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/of_address.h> 23 #include <linux/of_platform.h> 24 #include <linux/platform_device.h> 25 #include <linux/delay.h> 26 27 /* Registers */ 28 #define RNG_CTRL_OFFSET 0x00 29 #define RNG_CTRL_RNG_RBGEN_MASK 0x00001FFF 30 #define RNG_CTRL_RNG_RBGEN_ENABLE 0x00000001 31 32 #define RNG_SOFT_RESET_OFFSET 0x04 33 #define RNG_SOFT_RESET 0x00000001 34 35 #define RBG_SOFT_RESET_OFFSET 0x08 36 #define RBG_SOFT_RESET 0x00000001 37 38 #define RNG_INT_STATUS_OFFSET 0x18 39 #define RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK 0x80000000 40 #define RNG_INT_STATUS_STARTUP_TRANSITIONS_MET_IRQ_MASK 0x00020000 41 #define RNG_INT_STATUS_NIST_FAIL_IRQ_MASK 0x00000020 42 #define RNG_INT_STATUS_TOTAL_BITS_COUNT_IRQ_MASK 0x00000001 43 44 #define RNG_FIFO_DATA_OFFSET 0x20 45 46 #define RNG_FIFO_COUNT_OFFSET 0x24 47 #define RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK 0x000000FF 48 49 struct iproc_rng200_dev { 50 struct hwrng rng; 51 void __iomem *base; 52 }; 53 54 #define to_rng_priv(rng) container_of(rng, struct iproc_rng200_dev, rng) 55 56 static void iproc_rng200_restart(void __iomem *rng_base) 57 { 58 uint32_t val; 59 60 /* Disable RBG */ 61 val = ioread32(rng_base + RNG_CTRL_OFFSET); 62 val &= ~RNG_CTRL_RNG_RBGEN_MASK; 63 iowrite32(val, rng_base + RNG_CTRL_OFFSET); 64 65 /* Clear all interrupt status */ 66 iowrite32(0xFFFFFFFFUL, rng_base + RNG_INT_STATUS_OFFSET); 67 68 /* Reset RNG and RBG */ 69 val = ioread32(rng_base + RBG_SOFT_RESET_OFFSET); 70 val |= RBG_SOFT_RESET; 71 iowrite32(val, rng_base + RBG_SOFT_RESET_OFFSET); 72 73 val = ioread32(rng_base + RNG_SOFT_RESET_OFFSET); 74 val |= RNG_SOFT_RESET; 75 iowrite32(val, rng_base + RNG_SOFT_RESET_OFFSET); 76 77 val = ioread32(rng_base + RNG_SOFT_RESET_OFFSET); 78 val &= ~RNG_SOFT_RESET; 79 iowrite32(val, rng_base + RNG_SOFT_RESET_OFFSET); 80 81 val = ioread32(rng_base + RBG_SOFT_RESET_OFFSET); 82 val &= ~RBG_SOFT_RESET; 83 iowrite32(val, rng_base + RBG_SOFT_RESET_OFFSET); 84 85 /* Enable RBG */ 86 val = ioread32(rng_base + RNG_CTRL_OFFSET); 87 val &= ~RNG_CTRL_RNG_RBGEN_MASK; 88 val |= RNG_CTRL_RNG_RBGEN_ENABLE; 89 iowrite32(val, rng_base + RNG_CTRL_OFFSET); 90 } 91 92 static int iproc_rng200_read(struct hwrng *rng, void *buf, size_t max, 93 bool wait) 94 { 95 struct iproc_rng200_dev *priv = to_rng_priv(rng); 96 uint32_t num_remaining = max; 97 uint32_t status; 98 99 #define MAX_RESETS_PER_READ 1 100 uint32_t num_resets = 0; 101 102 #define MAX_IDLE_TIME (1 * HZ) 103 unsigned long idle_endtime = jiffies + MAX_IDLE_TIME; 104 105 while ((num_remaining > 0) && time_before(jiffies, idle_endtime)) { 106 107 /* Is RNG sane? If not, reset it. */ 108 status = ioread32(priv->base + RNG_INT_STATUS_OFFSET); 109 if ((status & (RNG_INT_STATUS_MASTER_FAIL_LOCKOUT_IRQ_MASK | 110 RNG_INT_STATUS_NIST_FAIL_IRQ_MASK)) != 0) { 111 112 if (num_resets >= MAX_RESETS_PER_READ) 113 return max - num_remaining; 114 115 iproc_rng200_restart(priv->base); 116 num_resets++; 117 } 118 119 /* Are there any random numbers available? */ 120 if ((ioread32(priv->base + RNG_FIFO_COUNT_OFFSET) & 121 RNG_FIFO_COUNT_RNG_FIFO_COUNT_MASK) > 0) { 122 123 if (num_remaining >= sizeof(uint32_t)) { 124 /* Buffer has room to store entire word */ 125 *(uint32_t *)buf = ioread32(priv->base + 126 RNG_FIFO_DATA_OFFSET); 127 buf += sizeof(uint32_t); 128 num_remaining -= sizeof(uint32_t); 129 } else { 130 /* Buffer can only store partial word */ 131 uint32_t rnd_number = ioread32(priv->base + 132 RNG_FIFO_DATA_OFFSET); 133 memcpy(buf, &rnd_number, num_remaining); 134 buf += num_remaining; 135 num_remaining = 0; 136 } 137 138 /* Reset the IDLE timeout */ 139 idle_endtime = jiffies + MAX_IDLE_TIME; 140 } else { 141 if (!wait) 142 /* Cannot wait, return immediately */ 143 return max - num_remaining; 144 145 /* Can wait, give others chance to run */ 146 usleep_range(min(num_remaining * 10, 500U), 500); 147 } 148 } 149 150 return max - num_remaining; 151 } 152 153 static int iproc_rng200_init(struct hwrng *rng) 154 { 155 struct iproc_rng200_dev *priv = to_rng_priv(rng); 156 uint32_t val; 157 158 /* Setup RNG. */ 159 val = ioread32(priv->base + RNG_CTRL_OFFSET); 160 val &= ~RNG_CTRL_RNG_RBGEN_MASK; 161 val |= RNG_CTRL_RNG_RBGEN_ENABLE; 162 iowrite32(val, priv->base + RNG_CTRL_OFFSET); 163 164 return 0; 165 } 166 167 static void iproc_rng200_cleanup(struct hwrng *rng) 168 { 169 struct iproc_rng200_dev *priv = to_rng_priv(rng); 170 uint32_t val; 171 172 /* Disable RNG hardware */ 173 val = ioread32(priv->base + RNG_CTRL_OFFSET); 174 val &= ~RNG_CTRL_RNG_RBGEN_MASK; 175 iowrite32(val, priv->base + RNG_CTRL_OFFSET); 176 } 177 178 static int iproc_rng200_probe(struct platform_device *pdev) 179 { 180 struct iproc_rng200_dev *priv; 181 struct device *dev = &pdev->dev; 182 int ret; 183 184 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 185 if (!priv) 186 return -ENOMEM; 187 188 /* Map peripheral */ 189 priv->base = devm_platform_ioremap_resource(pdev, 0); 190 if (IS_ERR(priv->base)) { 191 dev_err(dev, "failed to remap rng regs\n"); 192 return PTR_ERR(priv->base); 193 } 194 195 priv->rng.name = "iproc-rng200"; 196 priv->rng.read = iproc_rng200_read; 197 priv->rng.init = iproc_rng200_init; 198 priv->rng.cleanup = iproc_rng200_cleanup; 199 200 /* Register driver */ 201 ret = devm_hwrng_register(dev, &priv->rng); 202 if (ret) { 203 dev_err(dev, "hwrng registration failed\n"); 204 return ret; 205 } 206 207 dev_info(dev, "hwrng registered\n"); 208 209 return 0; 210 } 211 212 static const struct of_device_id iproc_rng200_of_match[] = { 213 { .compatible = "brcm,bcm2711-rng200", }, 214 { .compatible = "brcm,bcm7211-rng200", }, 215 { .compatible = "brcm,bcm7278-rng200", }, 216 { .compatible = "brcm,iproc-rng200", }, 217 {}, 218 }; 219 MODULE_DEVICE_TABLE(of, iproc_rng200_of_match); 220 221 static struct platform_driver iproc_rng200_driver = { 222 .driver = { 223 .name = "iproc-rng200", 224 .of_match_table = iproc_rng200_of_match, 225 }, 226 .probe = iproc_rng200_probe, 227 }; 228 module_platform_driver(iproc_rng200_driver); 229 230 MODULE_AUTHOR("Broadcom"); 231 MODULE_DESCRIPTION("iProc RNG200 Random Number Generator driver"); 232 MODULE_LICENSE("GPL v2"); 233