1 /* 2 * RNG driver for Intel RNGs 3 * 4 * Copyright 2005 (c) MontaVista Software, Inc. 5 * 6 * with the majority of the code coming from: 7 * 8 * Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG) 9 * (c) Copyright 2003 Red Hat Inc <jgarzik@redhat.com> 10 * 11 * derived from 12 * 13 * Hardware driver for the AMD 768 Random Number Generator (RNG) 14 * (c) Copyright 2001 Red Hat Inc <alan@redhat.com> 15 * 16 * derived from 17 * 18 * Hardware driver for Intel i810 Random Number Generator (RNG) 19 * Copyright 2000,2001 Jeff Garzik <jgarzik@pobox.com> 20 * Copyright 2000,2001 Philipp Rumpf <prumpf@mandrakesoft.com> 21 * 22 * This file is licensed under the terms of the GNU General Public 23 * License version 2. This program is licensed "as is" without any 24 * warranty of any kind, whether express or implied. 25 */ 26 27 #include <linux/hw_random.h> 28 #include <linux/kernel.h> 29 #include <linux/module.h> 30 #include <linux/pci.h> 31 #include <linux/stop_machine.h> 32 #include <asm/io.h> 33 34 35 #define PFX KBUILD_MODNAME ": " 36 37 /* 38 * RNG registers 39 */ 40 #define INTEL_RNG_HW_STATUS 0 41 #define INTEL_RNG_PRESENT 0x40 42 #define INTEL_RNG_ENABLED 0x01 43 #define INTEL_RNG_STATUS 1 44 #define INTEL_RNG_DATA_PRESENT 0x01 45 #define INTEL_RNG_DATA 2 46 47 /* 48 * Magic address at which Intel PCI bridges locate the RNG 49 */ 50 #define INTEL_RNG_ADDR 0xFFBC015F 51 #define INTEL_RNG_ADDR_LEN 3 52 53 /* 54 * LPC bridge PCI config space registers 55 */ 56 #define FWH_DEC_EN1_REG_OLD 0xe3 57 #define FWH_DEC_EN1_REG_NEW 0xd9 /* high byte of 16-bit register */ 58 #define FWH_F8_EN_MASK 0x80 59 60 #define BIOS_CNTL_REG_OLD 0x4e 61 #define BIOS_CNTL_REG_NEW 0xdc 62 #define BIOS_CNTL_WRITE_ENABLE_MASK 0x01 63 #define BIOS_CNTL_LOCK_ENABLE_MASK 0x02 64 65 /* 66 * Magic address at which Intel Firmware Hubs get accessed 67 */ 68 #define INTEL_FWH_ADDR 0xffff0000 69 #define INTEL_FWH_ADDR_LEN 2 70 71 /* 72 * Intel Firmware Hub command codes (write to any address inside the device) 73 */ 74 #define INTEL_FWH_RESET_CMD 0xff /* aka READ_ARRAY */ 75 #define INTEL_FWH_READ_ID_CMD 0x90 76 77 /* 78 * Intel Firmware Hub Read ID command result addresses 79 */ 80 #define INTEL_FWH_MANUFACTURER_CODE_ADDRESS 0x000000 81 #define INTEL_FWH_DEVICE_CODE_ADDRESS 0x000001 82 83 /* 84 * Intel Firmware Hub Read ID command result values 85 */ 86 #define INTEL_FWH_MANUFACTURER_CODE 0x89 87 #define INTEL_FWH_DEVICE_CODE_8M 0xac 88 #define INTEL_FWH_DEVICE_CODE_4M 0xad 89 90 /* 91 * Data for PCI driver interface 92 * 93 * This data only exists for exporting the supported 94 * PCI ids via MODULE_DEVICE_TABLE. We do not actually 95 * register a pci_driver, because someone else might one day 96 * want to register another driver on the same PCI id. 97 */ 98 static const struct pci_device_id pci_tbl[] = { 99 /* AA 100 { PCI_DEVICE(0x8086, 0x2418) }, */ 101 { PCI_DEVICE(0x8086, 0x2410) }, /* AA */ 102 /* AB 103 { PCI_DEVICE(0x8086, 0x2428) }, */ 104 { PCI_DEVICE(0x8086, 0x2420) }, /* AB */ 105 /* ?? 106 { PCI_DEVICE(0x8086, 0x2430) }, */ 107 /* BAM, CAM, DBM, FBM, GxM 108 { PCI_DEVICE(0x8086, 0x2448) }, */ 109 { PCI_DEVICE(0x8086, 0x244c) }, /* BAM */ 110 { PCI_DEVICE(0x8086, 0x248c) }, /* CAM */ 111 { PCI_DEVICE(0x8086, 0x24cc) }, /* DBM */ 112 { PCI_DEVICE(0x8086, 0x2641) }, /* FBM */ 113 { PCI_DEVICE(0x8086, 0x27b9) }, /* GxM */ 114 { PCI_DEVICE(0x8086, 0x27bd) }, /* GxM DH */ 115 /* BA, CA, DB, Ex, 6300, Fx, 631x/632x, Gx 116 { PCI_DEVICE(0x8086, 0x244e) }, */ 117 { PCI_DEVICE(0x8086, 0x2440) }, /* BA */ 118 { PCI_DEVICE(0x8086, 0x2480) }, /* CA */ 119 { PCI_DEVICE(0x8086, 0x24c0) }, /* DB */ 120 { PCI_DEVICE(0x8086, 0x24d0) }, /* Ex */ 121 { PCI_DEVICE(0x8086, 0x25a1) }, /* 6300 */ 122 { PCI_DEVICE(0x8086, 0x2640) }, /* Fx */ 123 { PCI_DEVICE(0x8086, 0x2670) }, /* 631x/632x */ 124 { PCI_DEVICE(0x8086, 0x2671) }, /* 631x/632x */ 125 { PCI_DEVICE(0x8086, 0x2672) }, /* 631x/632x */ 126 { PCI_DEVICE(0x8086, 0x2673) }, /* 631x/632x */ 127 { PCI_DEVICE(0x8086, 0x2674) }, /* 631x/632x */ 128 { PCI_DEVICE(0x8086, 0x2675) }, /* 631x/632x */ 129 { PCI_DEVICE(0x8086, 0x2676) }, /* 631x/632x */ 130 { PCI_DEVICE(0x8086, 0x2677) }, /* 631x/632x */ 131 { PCI_DEVICE(0x8086, 0x2678) }, /* 631x/632x */ 132 { PCI_DEVICE(0x8086, 0x2679) }, /* 631x/632x */ 133 { PCI_DEVICE(0x8086, 0x267a) }, /* 631x/632x */ 134 { PCI_DEVICE(0x8086, 0x267b) }, /* 631x/632x */ 135 { PCI_DEVICE(0x8086, 0x267c) }, /* 631x/632x */ 136 { PCI_DEVICE(0x8086, 0x267d) }, /* 631x/632x */ 137 { PCI_DEVICE(0x8086, 0x267e) }, /* 631x/632x */ 138 { PCI_DEVICE(0x8086, 0x267f) }, /* 631x/632x */ 139 { PCI_DEVICE(0x8086, 0x27b8) }, /* Gx */ 140 /* E 141 { PCI_DEVICE(0x8086, 0x245e) }, */ 142 { PCI_DEVICE(0x8086, 0x2450) }, /* E */ 143 { 0, }, /* terminate list */ 144 }; 145 MODULE_DEVICE_TABLE(pci, pci_tbl); 146 147 static __initdata int no_fwh_detect; 148 module_param(no_fwh_detect, int, 0); 149 MODULE_PARM_DESC(no_fwh_detect, "Skip FWH detection:\n" 150 " positive value - skip if FWH space locked read-only\n" 151 " negative value - skip always"); 152 153 static inline u8 hwstatus_get(void __iomem *mem) 154 { 155 return readb(mem + INTEL_RNG_HW_STATUS); 156 } 157 158 static inline u8 hwstatus_set(void __iomem *mem, 159 u8 hw_status) 160 { 161 writeb(hw_status, mem + INTEL_RNG_HW_STATUS); 162 return hwstatus_get(mem); 163 } 164 165 static int intel_rng_data_present(struct hwrng *rng) 166 { 167 void __iomem *mem = (void __iomem *)rng->priv; 168 169 return !!(readb(mem + INTEL_RNG_STATUS) & INTEL_RNG_DATA_PRESENT); 170 } 171 172 static int intel_rng_data_read(struct hwrng *rng, u32 *data) 173 { 174 void __iomem *mem = (void __iomem *)rng->priv; 175 176 *data = readb(mem + INTEL_RNG_DATA); 177 178 return 1; 179 } 180 181 static int intel_rng_init(struct hwrng *rng) 182 { 183 void __iomem *mem = (void __iomem *)rng->priv; 184 u8 hw_status; 185 int err = -EIO; 186 187 hw_status = hwstatus_get(mem); 188 /* turn RNG h/w on, if it's off */ 189 if ((hw_status & INTEL_RNG_ENABLED) == 0) 190 hw_status = hwstatus_set(mem, hw_status | INTEL_RNG_ENABLED); 191 if ((hw_status & INTEL_RNG_ENABLED) == 0) { 192 printk(KERN_ERR PFX "cannot enable RNG, aborting\n"); 193 goto out; 194 } 195 err = 0; 196 out: 197 return err; 198 } 199 200 static void intel_rng_cleanup(struct hwrng *rng) 201 { 202 void __iomem *mem = (void __iomem *)rng->priv; 203 u8 hw_status; 204 205 hw_status = hwstatus_get(mem); 206 if (hw_status & INTEL_RNG_ENABLED) 207 hwstatus_set(mem, hw_status & ~INTEL_RNG_ENABLED); 208 else 209 printk(KERN_WARNING PFX "unusual: RNG already disabled\n"); 210 } 211 212 213 static struct hwrng intel_rng = { 214 .name = "intel", 215 .init = intel_rng_init, 216 .cleanup = intel_rng_cleanup, 217 .data_present = intel_rng_data_present, 218 .data_read = intel_rng_data_read, 219 }; 220 221 struct intel_rng_hw { 222 struct pci_dev *dev; 223 void __iomem *mem; 224 u8 bios_cntl_off; 225 u8 bios_cntl_val; 226 u8 fwh_dec_en1_off; 227 u8 fwh_dec_en1_val; 228 }; 229 230 static int __init intel_rng_hw_init(void *_intel_rng_hw) 231 { 232 struct intel_rng_hw *intel_rng_hw = _intel_rng_hw; 233 u8 mfc, dvc; 234 235 /* interrupts disabled in stop_machine_run call */ 236 237 if (!(intel_rng_hw->fwh_dec_en1_val & FWH_F8_EN_MASK)) 238 pci_write_config_byte(intel_rng_hw->dev, 239 intel_rng_hw->fwh_dec_en1_off, 240 intel_rng_hw->fwh_dec_en1_val | 241 FWH_F8_EN_MASK); 242 if (!(intel_rng_hw->bios_cntl_val & BIOS_CNTL_WRITE_ENABLE_MASK)) 243 pci_write_config_byte(intel_rng_hw->dev, 244 intel_rng_hw->bios_cntl_off, 245 intel_rng_hw->bios_cntl_val | 246 BIOS_CNTL_WRITE_ENABLE_MASK); 247 248 writeb(INTEL_FWH_RESET_CMD, intel_rng_hw->mem); 249 writeb(INTEL_FWH_READ_ID_CMD, intel_rng_hw->mem); 250 mfc = readb(intel_rng_hw->mem + INTEL_FWH_MANUFACTURER_CODE_ADDRESS); 251 dvc = readb(intel_rng_hw->mem + INTEL_FWH_DEVICE_CODE_ADDRESS); 252 writeb(INTEL_FWH_RESET_CMD, intel_rng_hw->mem); 253 254 if (!(intel_rng_hw->bios_cntl_val & 255 (BIOS_CNTL_LOCK_ENABLE_MASK|BIOS_CNTL_WRITE_ENABLE_MASK))) 256 pci_write_config_byte(intel_rng_hw->dev, 257 intel_rng_hw->bios_cntl_off, 258 intel_rng_hw->bios_cntl_val); 259 if (!(intel_rng_hw->fwh_dec_en1_val & FWH_F8_EN_MASK)) 260 pci_write_config_byte(intel_rng_hw->dev, 261 intel_rng_hw->fwh_dec_en1_off, 262 intel_rng_hw->fwh_dec_en1_val); 263 264 if (mfc != INTEL_FWH_MANUFACTURER_CODE || 265 (dvc != INTEL_FWH_DEVICE_CODE_8M && 266 dvc != INTEL_FWH_DEVICE_CODE_4M)) { 267 printk(KERN_ERR PFX "FWH not detected\n"); 268 return -ENODEV; 269 } 270 271 return 0; 272 } 273 274 static int __init intel_init_hw_struct(struct intel_rng_hw *intel_rng_hw, 275 struct pci_dev *dev) 276 { 277 intel_rng_hw->bios_cntl_val = 0xff; 278 intel_rng_hw->fwh_dec_en1_val = 0xff; 279 intel_rng_hw->dev = dev; 280 281 /* Check for Intel 82802 */ 282 if (dev->device < 0x2640) { 283 intel_rng_hw->fwh_dec_en1_off = FWH_DEC_EN1_REG_OLD; 284 intel_rng_hw->bios_cntl_off = BIOS_CNTL_REG_OLD; 285 } else { 286 intel_rng_hw->fwh_dec_en1_off = FWH_DEC_EN1_REG_NEW; 287 intel_rng_hw->bios_cntl_off = BIOS_CNTL_REG_NEW; 288 } 289 290 pci_read_config_byte(dev, intel_rng_hw->fwh_dec_en1_off, 291 &intel_rng_hw->fwh_dec_en1_val); 292 pci_read_config_byte(dev, intel_rng_hw->bios_cntl_off, 293 &intel_rng_hw->bios_cntl_val); 294 295 if ((intel_rng_hw->bios_cntl_val & 296 (BIOS_CNTL_LOCK_ENABLE_MASK|BIOS_CNTL_WRITE_ENABLE_MASK)) 297 == BIOS_CNTL_LOCK_ENABLE_MASK) { 298 static __initdata /*const*/ char warning[] = 299 KERN_WARNING PFX "Firmware space is locked read-only. If you can't or\n" 300 KERN_WARNING PFX "don't want to disable this in firmware setup, and if\n" 301 KERN_WARNING PFX "you are certain that your system has a functional\n" 302 KERN_WARNING PFX "RNG, try using the 'no_fwh_detect' option.\n"; 303 304 if (no_fwh_detect) 305 return -ENODEV; 306 printk(warning); 307 return -EBUSY; 308 } 309 310 intel_rng_hw->mem = ioremap_nocache(INTEL_FWH_ADDR, INTEL_FWH_ADDR_LEN); 311 if (intel_rng_hw->mem == NULL) 312 return -EBUSY; 313 314 return 0; 315 } 316 317 318 static int __init mod_init(void) 319 { 320 int err = -ENODEV; 321 int i; 322 struct pci_dev *dev = NULL; 323 void __iomem *mem = mem; 324 u8 hw_status; 325 struct intel_rng_hw *intel_rng_hw; 326 327 for (i = 0; !dev && pci_tbl[i].vendor; ++i) 328 dev = pci_get_device(pci_tbl[i].vendor, pci_tbl[i].device, 329 NULL); 330 331 if (!dev) 332 goto out; /* Device not found. */ 333 334 if (no_fwh_detect < 0) { 335 pci_dev_put(dev); 336 goto fwh_done; 337 } 338 339 intel_rng_hw = kmalloc(sizeof(*intel_rng_hw), GFP_KERNEL); 340 if (!intel_rng_hw) { 341 pci_dev_put(dev); 342 goto out; 343 } 344 345 err = intel_init_hw_struct(intel_rng_hw, dev); 346 if (err) { 347 pci_dev_put(dev); 348 kfree(intel_rng_hw); 349 if (err == -ENODEV) 350 goto fwh_done; 351 goto out; 352 } 353 354 /* 355 * Since the BIOS code/data is going to disappear from its normal 356 * location with the Read ID command, all activity on the system 357 * must be stopped until the state is back to normal. 358 * 359 * Use stop_machine_run because IPIs can be blocked by disabling 360 * interrupts. 361 */ 362 err = stop_machine_run(intel_rng_hw_init, intel_rng_hw, NR_CPUS); 363 pci_dev_put(dev); 364 iounmap(intel_rng_hw->mem); 365 kfree(intel_rng_hw); 366 if (err) 367 goto out; 368 369 fwh_done: 370 err = -ENOMEM; 371 mem = ioremap(INTEL_RNG_ADDR, INTEL_RNG_ADDR_LEN); 372 if (!mem) 373 goto out; 374 intel_rng.priv = (unsigned long)mem; 375 376 /* Check for Random Number Generator */ 377 err = -ENODEV; 378 hw_status = hwstatus_get(mem); 379 if ((hw_status & INTEL_RNG_PRESENT) == 0) { 380 iounmap(mem); 381 goto out; 382 } 383 384 printk(KERN_INFO "Intel 82802 RNG detected\n"); 385 err = hwrng_register(&intel_rng); 386 if (err) { 387 printk(KERN_ERR PFX "RNG registering failed (%d)\n", 388 err); 389 iounmap(mem); 390 } 391 out: 392 return err; 393 394 } 395 396 static void __exit mod_exit(void) 397 { 398 void __iomem *mem = (void __iomem *)intel_rng.priv; 399 400 hwrng_unregister(&intel_rng); 401 iounmap(mem); 402 } 403 404 module_init(mod_init); 405 module_exit(mod_exit); 406 407 MODULE_DESCRIPTION("H/W RNG driver for Intel chipsets"); 408 MODULE_LICENSE("GPL"); 409