1a583ed31SHadar Gat /* SPDX-License-Identifier: GPL-2.0 */ 2a583ed31SHadar Gat /* Copyright (C) 2019-2020 ARM Limited or its affiliates. */ 3a583ed31SHadar Gat 4a583ed31SHadar Gat #include <linux/bitops.h> 5a583ed31SHadar Gat 6a583ed31SHadar Gat #define POWER_DOWN_ENABLE 0x01 7a583ed31SHadar Gat #define POWER_DOWN_DISABLE 0x00 8a583ed31SHadar Gat 9a583ed31SHadar Gat /* hwrng quality: bits of true entropy per 1024 bits of input */ 10a583ed31SHadar Gat #define CC_TRNG_QUALITY 1024 11a583ed31SHadar Gat 12a583ed31SHadar Gat /* CryptoCell TRNG HW definitions */ 13a583ed31SHadar Gat #define CC_TRNG_NUM_OF_ROSCS 4 14a583ed31SHadar Gat /* The number of words generated in the entropy holding register (EHR) 15a583ed31SHadar Gat * 6 words (192 bit) according to HW implementation 16a583ed31SHadar Gat */ 17a583ed31SHadar Gat #define CC_TRNG_EHR_IN_WORDS 6 18a583ed31SHadar Gat #define CC_TRNG_EHR_IN_BITS (CC_TRNG_EHR_IN_WORDS * BITS_PER_TYPE(u32)) 19a583ed31SHadar Gat 20a583ed31SHadar Gat #define CC_HOST_RNG_IRQ_MASK BIT(CC_HOST_RGF_IRR_RNG_INT_BIT_SHIFT) 21a583ed31SHadar Gat 22a583ed31SHadar Gat /* RNG interrupt mask */ 23a583ed31SHadar Gat #define CC_RNG_INT_MASK (BIT(CC_RNG_IMR_EHR_VALID_INT_MASK_BIT_SHIFT) | \ 24a583ed31SHadar Gat BIT(CC_RNG_IMR_AUTOCORR_ERR_INT_MASK_BIT_SHIFT) | \ 25a583ed31SHadar Gat BIT(CC_RNG_IMR_CRNGT_ERR_INT_MASK_BIT_SHIFT) | \ 26a583ed31SHadar Gat BIT(CC_RNG_IMR_VN_ERR_INT_MASK_BIT_SHIFT) | \ 27a583ed31SHadar Gat BIT(CC_RNG_IMR_WATCHDOG_INT_MASK_BIT_SHIFT)) 28a583ed31SHadar Gat 29a583ed31SHadar Gat // -------------------------------------- 30a583ed31SHadar Gat // BLOCK: RNG 31a583ed31SHadar Gat // -------------------------------------- 32a583ed31SHadar Gat #define CC_RNG_IMR_REG_OFFSET 0x0100UL 33a583ed31SHadar Gat #define CC_RNG_IMR_EHR_VALID_INT_MASK_BIT_SHIFT 0x0UL 34a583ed31SHadar Gat #define CC_RNG_IMR_AUTOCORR_ERR_INT_MASK_BIT_SHIFT 0x1UL 35a583ed31SHadar Gat #define CC_RNG_IMR_CRNGT_ERR_INT_MASK_BIT_SHIFT 0x2UL 36a583ed31SHadar Gat #define CC_RNG_IMR_VN_ERR_INT_MASK_BIT_SHIFT 0x3UL 37a583ed31SHadar Gat #define CC_RNG_IMR_WATCHDOG_INT_MASK_BIT_SHIFT 0x4UL 38a583ed31SHadar Gat #define CC_RNG_ISR_REG_OFFSET 0x0104UL 39a583ed31SHadar Gat #define CC_RNG_ISR_EHR_VALID_BIT_SHIFT 0x0UL 40a583ed31SHadar Gat #define CC_RNG_ISR_EHR_VALID_BIT_SIZE 0x1UL 41a583ed31SHadar Gat #define CC_RNG_ISR_AUTOCORR_ERR_BIT_SHIFT 0x1UL 42a583ed31SHadar Gat #define CC_RNG_ISR_AUTOCORR_ERR_BIT_SIZE 0x1UL 43a583ed31SHadar Gat #define CC_RNG_ISR_CRNGT_ERR_BIT_SHIFT 0x2UL 44a583ed31SHadar Gat #define CC_RNG_ISR_CRNGT_ERR_BIT_SIZE 0x1UL 45a583ed31SHadar Gat #define CC_RNG_ISR_WATCHDOG_BIT_SHIFT 0x4UL 46a583ed31SHadar Gat #define CC_RNG_ISR_WATCHDOG_BIT_SIZE 0x1UL 47a583ed31SHadar Gat #define CC_RNG_ICR_REG_OFFSET 0x0108UL 48a583ed31SHadar Gat #define CC_TRNG_CONFIG_REG_OFFSET 0x010CUL 49a583ed31SHadar Gat #define CC_EHR_DATA_0_REG_OFFSET 0x0114UL 50a583ed31SHadar Gat #define CC_RND_SOURCE_ENABLE_REG_OFFSET 0x012CUL 51a583ed31SHadar Gat #define CC_SAMPLE_CNT1_REG_OFFSET 0x0130UL 52a583ed31SHadar Gat #define CC_TRNG_DEBUG_CONTROL_REG_OFFSET 0x0138UL 53a583ed31SHadar Gat #define CC_RNG_SW_RESET_REG_OFFSET 0x0140UL 54a583ed31SHadar Gat #define CC_RNG_CLK_ENABLE_REG_OFFSET 0x01C4UL 55a583ed31SHadar Gat #define CC_RNG_DMA_ENABLE_REG_OFFSET 0x01C8UL 56a583ed31SHadar Gat #define CC_RNG_WATCHDOG_VAL_REG_OFFSET 0x01D8UL 57a583ed31SHadar Gat // -------------------------------------- 58a583ed31SHadar Gat // BLOCK: SEC_HOST_RGF 59a583ed31SHadar Gat // -------------------------------------- 60a583ed31SHadar Gat #define CC_HOST_RGF_IRR_REG_OFFSET 0x0A00UL 61a583ed31SHadar Gat #define CC_HOST_RGF_IRR_RNG_INT_BIT_SHIFT 0xAUL 62a583ed31SHadar Gat #define CC_HOST_RGF_IMR_REG_OFFSET 0x0A04UL 63a583ed31SHadar Gat #define CC_HOST_RGF_ICR_REG_OFFSET 0x0A08UL 64a583ed31SHadar Gat 65a583ed31SHadar Gat #define CC_HOST_POWER_DOWN_EN_REG_OFFSET 0x0A78UL 66a583ed31SHadar Gat 67a583ed31SHadar Gat // -------------------------------------- 68a583ed31SHadar Gat // BLOCK: NVM 69a583ed31SHadar Gat // -------------------------------------- 70a583ed31SHadar Gat #define CC_NVM_IS_IDLE_REG_OFFSET 0x0F10UL 71a583ed31SHadar Gat #define CC_NVM_IS_IDLE_VALUE_BIT_SHIFT 0x0UL 72a583ed31SHadar Gat #define CC_NVM_IS_IDLE_VALUE_BIT_SIZE 0x1UL 73