1 /* 2 * UniNorth AGPGART routines. 3 */ 4 #include <linux/module.h> 5 #include <linux/pci.h> 6 #include <linux/slab.h> 7 #include <linux/init.h> 8 #include <linux/pagemap.h> 9 #include <linux/agp_backend.h> 10 #include <linux/delay.h> 11 #include <linux/vmalloc.h> 12 #include <asm/uninorth.h> 13 #include <asm/prom.h> 14 #include <asm/pmac_feature.h> 15 #include "agp.h" 16 17 /* 18 * NOTES for uninorth3 (G5 AGP) supports : 19 * 20 * There maybe also possibility to have bigger cache line size for 21 * agp (see pmac_pci.c and look for cache line). Need to be investigated 22 * by someone. 23 * 24 * PAGE size are hardcoded but this may change, see asm/page.h. 25 * 26 * Jerome Glisse <j.glisse@gmail.com> 27 */ 28 static int uninorth_rev; 29 static int is_u3; 30 static u32 scratch_value; 31 32 #define DEFAULT_APERTURE_SIZE 256 33 #define DEFAULT_APERTURE_STRING "256" 34 static char *aperture = NULL; 35 36 static int uninorth_fetch_size(void) 37 { 38 int i, size = 0; 39 struct aper_size_info_32 *values = 40 A_SIZE_32(agp_bridge->driver->aperture_sizes); 41 42 if (aperture) { 43 char *save = aperture; 44 45 size = memparse(aperture, &aperture) >> 20; 46 aperture = save; 47 48 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) 49 if (size == values[i].size) 50 break; 51 52 if (i == agp_bridge->driver->num_aperture_sizes) { 53 dev_err(&agp_bridge->dev->dev, "invalid aperture size, " 54 "using default\n"); 55 size = 0; 56 aperture = NULL; 57 } 58 } 59 60 if (!size) { 61 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) 62 if (values[i].size == DEFAULT_APERTURE_SIZE) 63 break; 64 } 65 66 agp_bridge->previous_size = 67 agp_bridge->current_size = (void *)(values + i); 68 agp_bridge->aperture_size_idx = i; 69 return values[i].size; 70 } 71 72 static void uninorth_tlbflush(struct agp_memory *mem) 73 { 74 u32 ctrl = UNI_N_CFG_GART_ENABLE; 75 76 if (is_u3) 77 ctrl |= U3_N_CFG_GART_PERFRD; 78 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 79 ctrl | UNI_N_CFG_GART_INVAL); 80 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, ctrl); 81 82 if (!mem && uninorth_rev <= 0x30) { 83 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 84 ctrl | UNI_N_CFG_GART_2xRESET); 85 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 86 ctrl); 87 } 88 } 89 90 static void uninorth_cleanup(void) 91 { 92 u32 tmp; 93 94 pci_read_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, &tmp); 95 if (!(tmp & UNI_N_CFG_GART_ENABLE)) 96 return; 97 tmp |= UNI_N_CFG_GART_INVAL; 98 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, tmp); 99 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 0); 100 101 if (uninorth_rev <= 0x30) { 102 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 103 UNI_N_CFG_GART_2xRESET); 104 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 105 0); 106 } 107 } 108 109 static int uninorth_configure(void) 110 { 111 struct aper_size_info_32 *current_size; 112 113 current_size = A_SIZE_32(agp_bridge->current_size); 114 115 dev_info(&agp_bridge->dev->dev, "configuring for size idx: %d\n", 116 current_size->size_value); 117 118 /* aperture size and gatt addr */ 119 pci_write_config_dword(agp_bridge->dev, 120 UNI_N_CFG_GART_BASE, 121 (agp_bridge->gatt_bus_addr & 0xfffff000) 122 | current_size->size_value); 123 124 /* HACK ALERT 125 * UniNorth seem to be buggy enough not to handle properly when 126 * the AGP aperture isn't mapped at bus physical address 0 127 */ 128 agp_bridge->gart_bus_addr = 0; 129 #ifdef CONFIG_PPC64 130 /* Assume U3 or later on PPC64 systems */ 131 /* high 4 bits of GART physical address go in UNI_N_CFG_AGP_BASE */ 132 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_AGP_BASE, 133 (agp_bridge->gatt_bus_addr >> 32) & 0xf); 134 #else 135 pci_write_config_dword(agp_bridge->dev, 136 UNI_N_CFG_AGP_BASE, agp_bridge->gart_bus_addr); 137 #endif 138 139 if (is_u3) { 140 pci_write_config_dword(agp_bridge->dev, 141 UNI_N_CFG_GART_DUMMY_PAGE, 142 page_to_phys(agp_bridge->scratch_page_page) >> 12); 143 } 144 145 return 0; 146 } 147 148 static int uninorth_insert_memory(struct agp_memory *mem, off_t pg_start, int type) 149 { 150 int i, num_entries; 151 void *temp; 152 u32 *gp; 153 int mask_type; 154 155 if (type != mem->type) 156 return -EINVAL; 157 158 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 159 if (mask_type != 0) { 160 /* We know nothing of memory types */ 161 return -EINVAL; 162 } 163 164 if (mem->page_count == 0) 165 return 0; 166 167 temp = agp_bridge->current_size; 168 num_entries = A_SIZE_32(temp)->num_entries; 169 170 if ((pg_start + mem->page_count) > num_entries) 171 return -EINVAL; 172 173 gp = (u32 *) &agp_bridge->gatt_table[pg_start]; 174 for (i = 0; i < mem->page_count; ++i) { 175 if (gp[i] != scratch_value) { 176 dev_info(&agp_bridge->dev->dev, 177 "uninorth_insert_memory: entry 0x%x occupied (%x)\n", 178 i, gp[i]); 179 return -EBUSY; 180 } 181 } 182 183 for (i = 0; i < mem->page_count; i++) { 184 if (is_u3) 185 gp[i] = (page_to_phys(mem->pages[i]) >> PAGE_SHIFT) | 0x80000000UL; 186 else 187 gp[i] = cpu_to_le32((page_to_phys(mem->pages[i]) & 0xFFFFF000UL) | 188 0x1UL); 189 flush_dcache_range((unsigned long)__va(page_to_phys(mem->pages[i])), 190 (unsigned long)__va(page_to_phys(mem->pages[i]))+0x1000); 191 } 192 mb(); 193 uninorth_tlbflush(mem); 194 195 return 0; 196 } 197 198 static int uninorth_remove_memory(struct agp_memory *mem, off_t pg_start, int type) 199 { 200 size_t i; 201 u32 *gp; 202 int mask_type; 203 204 if (type != mem->type) 205 return -EINVAL; 206 207 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 208 if (mask_type != 0) { 209 /* We know nothing of memory types */ 210 return -EINVAL; 211 } 212 213 if (mem->page_count == 0) 214 return 0; 215 216 gp = (u32 *) &agp_bridge->gatt_table[pg_start]; 217 for (i = 0; i < mem->page_count; ++i) { 218 gp[i] = scratch_value; 219 } 220 mb(); 221 uninorth_tlbflush(mem); 222 223 return 0; 224 } 225 226 static void uninorth_agp_enable(struct agp_bridge_data *bridge, u32 mode) 227 { 228 u32 command, scratch, status; 229 int timeout; 230 231 pci_read_config_dword(bridge->dev, 232 bridge->capndx + PCI_AGP_STATUS, 233 &status); 234 235 command = agp_collect_device_status(bridge, mode, status); 236 command |= PCI_AGP_COMMAND_AGP; 237 238 if (uninorth_rev == 0x21) { 239 /* 240 * Darwin disable AGP 4x on this revision, thus we 241 * may assume it's broken. This is an AGP2 controller. 242 */ 243 command &= ~AGPSTAT2_4X; 244 } 245 246 if ((uninorth_rev >= 0x30) && (uninorth_rev <= 0x33)) { 247 /* 248 * We need to set REQ_DEPTH to 7 for U3 versions 1.0, 2.1, 249 * 2.2 and 2.3, Darwin do so. 250 */ 251 if ((command >> AGPSTAT_RQ_DEPTH_SHIFT) > 7) 252 command = (command & ~AGPSTAT_RQ_DEPTH) 253 | (7 << AGPSTAT_RQ_DEPTH_SHIFT); 254 } 255 256 uninorth_tlbflush(NULL); 257 258 timeout = 0; 259 do { 260 pci_write_config_dword(bridge->dev, 261 bridge->capndx + PCI_AGP_COMMAND, 262 command); 263 pci_read_config_dword(bridge->dev, 264 bridge->capndx + PCI_AGP_COMMAND, 265 &scratch); 266 } while ((scratch & PCI_AGP_COMMAND_AGP) == 0 && ++timeout < 1000); 267 if ((scratch & PCI_AGP_COMMAND_AGP) == 0) 268 dev_err(&bridge->dev->dev, "can't write UniNorth AGP " 269 "command register\n"); 270 271 if (uninorth_rev >= 0x30) { 272 /* This is an AGP V3 */ 273 agp_device_command(command, (status & AGPSTAT_MODE_3_0) != 0); 274 } else { 275 /* AGP V2 */ 276 agp_device_command(command, false); 277 } 278 279 uninorth_tlbflush(NULL); 280 } 281 282 #ifdef CONFIG_PM 283 /* 284 * These Power Management routines are _not_ called by the normal PCI PM layer, 285 * but directly by the video driver through function pointers in the device 286 * tree. 287 */ 288 static int agp_uninorth_suspend(struct pci_dev *pdev) 289 { 290 struct agp_bridge_data *bridge; 291 u32 cmd; 292 u8 agp; 293 struct pci_dev *device = NULL; 294 295 bridge = agp_find_bridge(pdev); 296 if (bridge == NULL) 297 return -ENODEV; 298 299 /* Only one suspend supported */ 300 if (bridge->dev_private_data) 301 return 0; 302 303 /* turn off AGP on the video chip, if it was enabled */ 304 for_each_pci_dev(device) { 305 /* Don't touch the bridge yet, device first */ 306 if (device == pdev) 307 continue; 308 /* Only deal with devices on the same bus here, no Mac has a P2P 309 * bridge on the AGP port, and mucking around the entire PCI 310 * tree is source of problems on some machines because of a bug 311 * in some versions of pci_find_capability() when hitting a dead 312 * device 313 */ 314 if (device->bus != pdev->bus) 315 continue; 316 agp = pci_find_capability(device, PCI_CAP_ID_AGP); 317 if (!agp) 318 continue; 319 pci_read_config_dword(device, agp + PCI_AGP_COMMAND, &cmd); 320 if (!(cmd & PCI_AGP_COMMAND_AGP)) 321 continue; 322 dev_info(&pdev->dev, "disabling AGP on device %s\n", 323 pci_name(device)); 324 cmd &= ~PCI_AGP_COMMAND_AGP; 325 pci_write_config_dword(device, agp + PCI_AGP_COMMAND, cmd); 326 } 327 328 /* turn off AGP on the bridge */ 329 agp = pci_find_capability(pdev, PCI_CAP_ID_AGP); 330 pci_read_config_dword(pdev, agp + PCI_AGP_COMMAND, &cmd); 331 bridge->dev_private_data = (void *)(long)cmd; 332 if (cmd & PCI_AGP_COMMAND_AGP) { 333 dev_info(&pdev->dev, "disabling AGP on bridge\n"); 334 cmd &= ~PCI_AGP_COMMAND_AGP; 335 pci_write_config_dword(pdev, agp + PCI_AGP_COMMAND, cmd); 336 } 337 /* turn off the GART */ 338 uninorth_cleanup(); 339 340 return 0; 341 } 342 343 static int agp_uninorth_resume(struct pci_dev *pdev) 344 { 345 struct agp_bridge_data *bridge; 346 u32 command; 347 348 bridge = agp_find_bridge(pdev); 349 if (bridge == NULL) 350 return -ENODEV; 351 352 command = (long)bridge->dev_private_data; 353 bridge->dev_private_data = NULL; 354 if (!(command & PCI_AGP_COMMAND_AGP)) 355 return 0; 356 357 uninorth_agp_enable(bridge, command); 358 359 return 0; 360 } 361 #endif /* CONFIG_PM */ 362 363 static struct { 364 struct page **pages_arr; 365 } uninorth_priv; 366 367 static int uninorth_create_gatt_table(struct agp_bridge_data *bridge) 368 { 369 char *table; 370 char *table_end; 371 int size; 372 int page_order; 373 int num_entries; 374 int i; 375 void *temp; 376 struct page *page; 377 378 /* We can't handle 2 level gatt's */ 379 if (bridge->driver->size_type == LVL2_APER_SIZE) 380 return -EINVAL; 381 382 table = NULL; 383 i = bridge->aperture_size_idx; 384 temp = bridge->current_size; 385 size = page_order = num_entries = 0; 386 387 do { 388 size = A_SIZE_32(temp)->size; 389 page_order = A_SIZE_32(temp)->page_order; 390 num_entries = A_SIZE_32(temp)->num_entries; 391 392 table = (char *) __get_free_pages(GFP_KERNEL, page_order); 393 394 if (table == NULL) { 395 i++; 396 bridge->current_size = A_IDX32(bridge); 397 } else { 398 bridge->aperture_size_idx = i; 399 } 400 } while (!table && (i < bridge->driver->num_aperture_sizes)); 401 402 if (table == NULL) 403 return -ENOMEM; 404 405 uninorth_priv.pages_arr = kmalloc_array(1 << page_order, 406 sizeof(struct page *), 407 GFP_KERNEL); 408 if (uninorth_priv.pages_arr == NULL) 409 goto enomem; 410 411 table_end = table + ((PAGE_SIZE * (1 << page_order)) - 1); 412 413 for (page = virt_to_page(table), i = 0; page <= virt_to_page(table_end); 414 page++, i++) { 415 SetPageReserved(page); 416 uninorth_priv.pages_arr[i] = page; 417 } 418 419 bridge->gatt_table_real = (u32 *) table; 420 /* Need to clear out any dirty data still sitting in caches */ 421 flush_dcache_range((unsigned long)table, 422 (unsigned long)table_end + 1); 423 bridge->gatt_table = vmap(uninorth_priv.pages_arr, (1 << page_order), 0, PAGE_KERNEL_NCG); 424 425 if (bridge->gatt_table == NULL) 426 goto enomem; 427 428 bridge->gatt_bus_addr = virt_to_phys(table); 429 430 if (is_u3) 431 scratch_value = (page_to_phys(agp_bridge->scratch_page_page) >> PAGE_SHIFT) | 0x80000000UL; 432 else 433 scratch_value = cpu_to_le32((page_to_phys(agp_bridge->scratch_page_page) & 0xFFFFF000UL) | 434 0x1UL); 435 for (i = 0; i < num_entries; i++) 436 bridge->gatt_table[i] = scratch_value; 437 438 return 0; 439 440 enomem: 441 kfree(uninorth_priv.pages_arr); 442 if (table) 443 free_pages((unsigned long)table, page_order); 444 return -ENOMEM; 445 } 446 447 static int uninorth_free_gatt_table(struct agp_bridge_data *bridge) 448 { 449 int page_order; 450 char *table, *table_end; 451 void *temp; 452 struct page *page; 453 454 temp = bridge->current_size; 455 page_order = A_SIZE_32(temp)->page_order; 456 457 /* Do not worry about freeing memory, because if this is 458 * called, then all agp memory is deallocated and removed 459 * from the table. 460 */ 461 462 vunmap(bridge->gatt_table); 463 kfree(uninorth_priv.pages_arr); 464 table = (char *) bridge->gatt_table_real; 465 table_end = table + ((PAGE_SIZE * (1 << page_order)) - 1); 466 467 for (page = virt_to_page(table); page <= virt_to_page(table_end); page++) 468 ClearPageReserved(page); 469 470 free_pages((unsigned long) bridge->gatt_table_real, page_order); 471 472 return 0; 473 } 474 475 static void null_cache_flush(void) 476 { 477 mb(); 478 } 479 480 /* Setup function */ 481 482 static const struct aper_size_info_32 uninorth_sizes[] = 483 { 484 {256, 65536, 6, 64}, 485 {128, 32768, 5, 32}, 486 {64, 16384, 4, 16}, 487 {32, 8192, 3, 8}, 488 {16, 4096, 2, 4}, 489 {8, 2048, 1, 2}, 490 {4, 1024, 0, 1} 491 }; 492 493 /* 494 * Not sure that u3 supports that high aperture sizes but it 495 * would strange if it did not :) 496 */ 497 static const struct aper_size_info_32 u3_sizes[] = 498 { 499 {512, 131072, 7, 128}, 500 {256, 65536, 6, 64}, 501 {128, 32768, 5, 32}, 502 {64, 16384, 4, 16}, 503 {32, 8192, 3, 8}, 504 {16, 4096, 2, 4}, 505 {8, 2048, 1, 2}, 506 {4, 1024, 0, 1} 507 }; 508 509 const struct agp_bridge_driver uninorth_agp_driver = { 510 .owner = THIS_MODULE, 511 .aperture_sizes = (void *)uninorth_sizes, 512 .size_type = U32_APER_SIZE, 513 .num_aperture_sizes = ARRAY_SIZE(uninorth_sizes), 514 .configure = uninorth_configure, 515 .fetch_size = uninorth_fetch_size, 516 .cleanup = uninorth_cleanup, 517 .tlb_flush = uninorth_tlbflush, 518 .mask_memory = agp_generic_mask_memory, 519 .masks = NULL, 520 .cache_flush = null_cache_flush, 521 .agp_enable = uninorth_agp_enable, 522 .create_gatt_table = uninorth_create_gatt_table, 523 .free_gatt_table = uninorth_free_gatt_table, 524 .insert_memory = uninorth_insert_memory, 525 .remove_memory = uninorth_remove_memory, 526 .alloc_by_type = agp_generic_alloc_by_type, 527 .free_by_type = agp_generic_free_by_type, 528 .agp_alloc_page = agp_generic_alloc_page, 529 .agp_alloc_pages = agp_generic_alloc_pages, 530 .agp_destroy_page = agp_generic_destroy_page, 531 .agp_destroy_pages = agp_generic_destroy_pages, 532 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 533 .cant_use_aperture = true, 534 .needs_scratch_page = true, 535 }; 536 537 const struct agp_bridge_driver u3_agp_driver = { 538 .owner = THIS_MODULE, 539 .aperture_sizes = (void *)u3_sizes, 540 .size_type = U32_APER_SIZE, 541 .num_aperture_sizes = ARRAY_SIZE(u3_sizes), 542 .configure = uninorth_configure, 543 .fetch_size = uninorth_fetch_size, 544 .cleanup = uninorth_cleanup, 545 .tlb_flush = uninorth_tlbflush, 546 .mask_memory = agp_generic_mask_memory, 547 .masks = NULL, 548 .cache_flush = null_cache_flush, 549 .agp_enable = uninorth_agp_enable, 550 .create_gatt_table = uninorth_create_gatt_table, 551 .free_gatt_table = uninorth_free_gatt_table, 552 .insert_memory = uninorth_insert_memory, 553 .remove_memory = uninorth_remove_memory, 554 .alloc_by_type = agp_generic_alloc_by_type, 555 .free_by_type = agp_generic_free_by_type, 556 .agp_alloc_page = agp_generic_alloc_page, 557 .agp_alloc_pages = agp_generic_alloc_pages, 558 .agp_destroy_page = agp_generic_destroy_page, 559 .agp_destroy_pages = agp_generic_destroy_pages, 560 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 561 .cant_use_aperture = true, 562 .needs_scratch_page = true, 563 }; 564 565 static struct agp_device_ids uninorth_agp_device_ids[] = { 566 { 567 .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP, 568 .chipset_name = "UniNorth", 569 }, 570 { 571 .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP_P, 572 .chipset_name = "UniNorth/Pangea", 573 }, 574 { 575 .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP15, 576 .chipset_name = "UniNorth 1.5", 577 }, 578 { 579 .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP2, 580 .chipset_name = "UniNorth 2", 581 }, 582 { 583 .device_id = PCI_DEVICE_ID_APPLE_U3_AGP, 584 .chipset_name = "U3", 585 }, 586 { 587 .device_id = PCI_DEVICE_ID_APPLE_U3L_AGP, 588 .chipset_name = "U3L", 589 }, 590 { 591 .device_id = PCI_DEVICE_ID_APPLE_U3H_AGP, 592 .chipset_name = "U3H", 593 }, 594 { 595 .device_id = PCI_DEVICE_ID_APPLE_IPID2_AGP, 596 .chipset_name = "UniNorth/Intrepid2", 597 }, 598 }; 599 600 static int agp_uninorth_probe(struct pci_dev *pdev, 601 const struct pci_device_id *ent) 602 { 603 struct agp_device_ids *devs = uninorth_agp_device_ids; 604 struct agp_bridge_data *bridge; 605 struct device_node *uninorth_node; 606 u8 cap_ptr; 607 int j; 608 609 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); 610 if (cap_ptr == 0) 611 return -ENODEV; 612 613 /* probe for known chipsets */ 614 for (j = 0; devs[j].chipset_name != NULL; ++j) { 615 if (pdev->device == devs[j].device_id) { 616 dev_info(&pdev->dev, "Apple %s chipset\n", 617 devs[j].chipset_name); 618 goto found; 619 } 620 } 621 622 dev_err(&pdev->dev, "unsupported Apple chipset [%04x/%04x]\n", 623 pdev->vendor, pdev->device); 624 return -ENODEV; 625 626 found: 627 /* Set revision to 0 if we could not read it. */ 628 uninorth_rev = 0; 629 is_u3 = 0; 630 /* Locate core99 Uni-N */ 631 uninorth_node = of_find_node_by_name(NULL, "uni-n"); 632 /* Locate G5 u3 */ 633 if (uninorth_node == NULL) { 634 is_u3 = 1; 635 uninorth_node = of_find_node_by_name(NULL, "u3"); 636 } 637 if (uninorth_node) { 638 const int *revprop = of_get_property(uninorth_node, 639 "device-rev", NULL); 640 if (revprop != NULL) 641 uninorth_rev = *revprop & 0x3f; 642 of_node_put(uninorth_node); 643 } 644 645 #ifdef CONFIG_PM 646 /* Inform platform of our suspend/resume caps */ 647 pmac_register_agp_pm(pdev, agp_uninorth_suspend, agp_uninorth_resume); 648 #endif 649 650 /* Allocate & setup our driver */ 651 bridge = agp_alloc_bridge(); 652 if (!bridge) 653 return -ENOMEM; 654 655 if (is_u3) 656 bridge->driver = &u3_agp_driver; 657 else 658 bridge->driver = &uninorth_agp_driver; 659 660 bridge->dev = pdev; 661 bridge->capndx = cap_ptr; 662 bridge->flags = AGP_ERRATA_FASTWRITES; 663 664 /* Fill in the mode register */ 665 pci_read_config_dword(pdev, cap_ptr+PCI_AGP_STATUS, &bridge->mode); 666 667 pci_set_drvdata(pdev, bridge); 668 return agp_add_bridge(bridge); 669 } 670 671 static void agp_uninorth_remove(struct pci_dev *pdev) 672 { 673 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 674 675 #ifdef CONFIG_PM 676 /* Inform platform of our suspend/resume caps */ 677 pmac_register_agp_pm(pdev, NULL, NULL); 678 #endif 679 680 agp_remove_bridge(bridge); 681 agp_put_bridge(bridge); 682 } 683 684 static const struct pci_device_id agp_uninorth_pci_table[] = { 685 { 686 .class = (PCI_CLASS_BRIDGE_HOST << 8), 687 .class_mask = ~0, 688 .vendor = PCI_VENDOR_ID_APPLE, 689 .device = PCI_ANY_ID, 690 .subvendor = PCI_ANY_ID, 691 .subdevice = PCI_ANY_ID, 692 }, 693 { } 694 }; 695 696 MODULE_DEVICE_TABLE(pci, agp_uninorth_pci_table); 697 698 static struct pci_driver agp_uninorth_pci_driver = { 699 .name = "agpgart-uninorth", 700 .id_table = agp_uninorth_pci_table, 701 .probe = agp_uninorth_probe, 702 .remove = agp_uninorth_remove, 703 }; 704 705 static int __init agp_uninorth_init(void) 706 { 707 if (agp_off) 708 return -EINVAL; 709 return pci_register_driver(&agp_uninorth_pci_driver); 710 } 711 712 static void __exit agp_uninorth_cleanup(void) 713 { 714 pci_unregister_driver(&agp_uninorth_pci_driver); 715 } 716 717 module_init(agp_uninorth_init); 718 module_exit(agp_uninorth_cleanup); 719 720 module_param(aperture, charp, 0); 721 MODULE_PARM_DESC(aperture, 722 "Aperture size, must be power of two between 4MB and an\n" 723 "\t\tupper limit specific to the UniNorth revision.\n" 724 "\t\tDefault: " DEFAULT_APERTURE_STRING "M"); 725 726 MODULE_AUTHOR("Ben Herrenschmidt & Paul Mackerras"); 727 MODULE_LICENSE("GPL"); 728