1 /* 2 * UniNorth AGPGART routines. 3 */ 4 #include <linux/module.h> 5 #include <linux/pci.h> 6 #include <linux/init.h> 7 #include <linux/pagemap.h> 8 #include <linux/agp_backend.h> 9 #include <linux/delay.h> 10 #include <asm/uninorth.h> 11 #include <asm/pci-bridge.h> 12 #include <asm/prom.h> 13 #include <asm/pmac_feature.h> 14 #include "agp.h" 15 16 /* 17 * NOTES for uninorth3 (G5 AGP) supports : 18 * 19 * There maybe also possibility to have bigger cache line size for 20 * agp (see pmac_pci.c and look for cache line). Need to be investigated 21 * by someone. 22 * 23 * PAGE size are hardcoded but this may change, see asm/page.h. 24 * 25 * Jerome Glisse <j.glisse@gmail.com> 26 */ 27 static int uninorth_rev; 28 static int is_u3; 29 30 static char *aperture = NULL; 31 32 static int uninorth_fetch_size(void) 33 { 34 int i, size = 0; 35 struct aper_size_info_32 *values = 36 A_SIZE_32(agp_bridge->driver->aperture_sizes); 37 38 if (aperture) { 39 char *save = aperture; 40 41 size = memparse(aperture, &aperture) >> 20; 42 aperture = save; 43 44 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) 45 if (size == values[i].size) 46 break; 47 48 if (i == agp_bridge->driver->num_aperture_sizes) { 49 dev_err(&agp_bridge->dev->dev, "invalid aperture size, " 50 "using default\n"); 51 size = 0; 52 aperture = NULL; 53 } 54 } 55 56 if (!size) { 57 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) 58 if (values[i].size == 32) 59 break; 60 } 61 62 agp_bridge->previous_size = 63 agp_bridge->current_size = (void *)(values + i); 64 agp_bridge->aperture_size_idx = i; 65 return values[i].size; 66 } 67 68 static void uninorth_tlbflush(struct agp_memory *mem) 69 { 70 u32 ctrl = UNI_N_CFG_GART_ENABLE; 71 72 if (is_u3) 73 ctrl |= U3_N_CFG_GART_PERFRD; 74 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 75 ctrl | UNI_N_CFG_GART_INVAL); 76 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, ctrl); 77 78 if (uninorth_rev <= 0x30) { 79 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 80 ctrl | UNI_N_CFG_GART_2xRESET); 81 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 82 ctrl); 83 } 84 } 85 86 static void uninorth_cleanup(void) 87 { 88 u32 tmp; 89 90 pci_read_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, &tmp); 91 if (!(tmp & UNI_N_CFG_GART_ENABLE)) 92 return; 93 tmp |= UNI_N_CFG_GART_INVAL; 94 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, tmp); 95 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 0); 96 97 if (uninorth_rev <= 0x30) { 98 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 99 UNI_N_CFG_GART_2xRESET); 100 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 101 0); 102 } 103 } 104 105 static int uninorth_configure(void) 106 { 107 struct aper_size_info_32 *current_size; 108 109 current_size = A_SIZE_32(agp_bridge->current_size); 110 111 dev_info(&agp_bridge->dev->dev, "configuring for size idx: %d\n", 112 current_size->size_value); 113 114 /* aperture size and gatt addr */ 115 pci_write_config_dword(agp_bridge->dev, 116 UNI_N_CFG_GART_BASE, 117 (agp_bridge->gatt_bus_addr & 0xfffff000) 118 | current_size->size_value); 119 120 /* HACK ALERT 121 * UniNorth seem to be buggy enough not to handle properly when 122 * the AGP aperture isn't mapped at bus physical address 0 123 */ 124 agp_bridge->gart_bus_addr = 0; 125 #ifdef CONFIG_PPC64 126 /* Assume U3 or later on PPC64 systems */ 127 /* high 4 bits of GART physical address go in UNI_N_CFG_AGP_BASE */ 128 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_AGP_BASE, 129 (agp_bridge->gatt_bus_addr >> 32) & 0xf); 130 #else 131 pci_write_config_dword(agp_bridge->dev, 132 UNI_N_CFG_AGP_BASE, agp_bridge->gart_bus_addr); 133 #endif 134 135 if (is_u3) { 136 pci_write_config_dword(agp_bridge->dev, 137 UNI_N_CFG_GART_DUMMY_PAGE, 138 agp_bridge->scratch_page_real >> 12); 139 } 140 141 return 0; 142 } 143 144 static int uninorth_insert_memory(struct agp_memory *mem, off_t pg_start, 145 int type) 146 { 147 int i, j, num_entries; 148 void *temp; 149 150 temp = agp_bridge->current_size; 151 num_entries = A_SIZE_32(temp)->num_entries; 152 153 if (type != 0 || mem->type != 0) 154 /* We know nothing of memory types */ 155 return -EINVAL; 156 if ((pg_start + mem->page_count) > num_entries) 157 return -EINVAL; 158 159 j = pg_start; 160 161 while (j < (pg_start + mem->page_count)) { 162 if (agp_bridge->gatt_table[j]) 163 return -EBUSY; 164 j++; 165 } 166 167 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) { 168 agp_bridge->gatt_table[j] = 169 cpu_to_le32((mem->memory[i] & 0xFFFFF000UL) | 0x1UL); 170 flush_dcache_range((unsigned long)__va(mem->memory[i]), 171 (unsigned long)__va(mem->memory[i])+0x1000); 172 } 173 (void)in_le32((volatile u32*)&agp_bridge->gatt_table[pg_start]); 174 mb(); 175 flush_dcache_range((unsigned long)&agp_bridge->gatt_table[pg_start], 176 (unsigned long)&agp_bridge->gatt_table[pg_start + mem->page_count]); 177 178 uninorth_tlbflush(mem); 179 return 0; 180 } 181 182 static int u3_insert_memory(struct agp_memory *mem, off_t pg_start, int type) 183 { 184 int i, num_entries; 185 void *temp; 186 u32 *gp; 187 188 temp = agp_bridge->current_size; 189 num_entries = A_SIZE_32(temp)->num_entries; 190 191 if (type != 0 || mem->type != 0) 192 /* We know nothing of memory types */ 193 return -EINVAL; 194 if ((pg_start + mem->page_count) > num_entries) 195 return -EINVAL; 196 197 gp = (u32 *) &agp_bridge->gatt_table[pg_start]; 198 for (i = 0; i < mem->page_count; ++i) { 199 if (gp[i]) { 200 dev_info(&agp_bridge->dev->dev, 201 "u3_insert_memory: entry 0x%x occupied (%x)\n", 202 i, gp[i]); 203 return -EBUSY; 204 } 205 } 206 207 for (i = 0; i < mem->page_count; i++) { 208 gp[i] = (mem->memory[i] >> PAGE_SHIFT) | 0x80000000UL; 209 flush_dcache_range((unsigned long)__va(mem->memory[i]), 210 (unsigned long)__va(mem->memory[i])+0x1000); 211 } 212 mb(); 213 flush_dcache_range((unsigned long)gp, (unsigned long) &gp[i]); 214 uninorth_tlbflush(mem); 215 216 return 0; 217 } 218 219 int u3_remove_memory(struct agp_memory *mem, off_t pg_start, int type) 220 { 221 size_t i; 222 u32 *gp; 223 224 if (type != 0 || mem->type != 0) 225 /* We know nothing of memory types */ 226 return -EINVAL; 227 228 gp = (u32 *) &agp_bridge->gatt_table[pg_start]; 229 for (i = 0; i < mem->page_count; ++i) 230 gp[i] = 0; 231 mb(); 232 flush_dcache_range((unsigned long)gp, (unsigned long) &gp[i]); 233 uninorth_tlbflush(mem); 234 235 return 0; 236 } 237 238 static void uninorth_agp_enable(struct agp_bridge_data *bridge, u32 mode) 239 { 240 u32 command, scratch, status; 241 int timeout; 242 243 pci_read_config_dword(bridge->dev, 244 bridge->capndx + PCI_AGP_STATUS, 245 &status); 246 247 command = agp_collect_device_status(bridge, mode, status); 248 command |= PCI_AGP_COMMAND_AGP; 249 250 if (uninorth_rev == 0x21) { 251 /* 252 * Darwin disable AGP 4x on this revision, thus we 253 * may assume it's broken. This is an AGP2 controller. 254 */ 255 command &= ~AGPSTAT2_4X; 256 } 257 258 if ((uninorth_rev >= 0x30) && (uninorth_rev <= 0x33)) { 259 /* 260 * We need to to set REQ_DEPTH to 7 for U3 versions 1.0, 2.1, 261 * 2.2 and 2.3, Darwin do so. 262 */ 263 if ((command >> AGPSTAT_RQ_DEPTH_SHIFT) > 7) 264 command = (command & ~AGPSTAT_RQ_DEPTH) 265 | (7 << AGPSTAT_RQ_DEPTH_SHIFT); 266 } 267 268 uninorth_tlbflush(NULL); 269 270 timeout = 0; 271 do { 272 pci_write_config_dword(bridge->dev, 273 bridge->capndx + PCI_AGP_COMMAND, 274 command); 275 pci_read_config_dword(bridge->dev, 276 bridge->capndx + PCI_AGP_COMMAND, 277 &scratch); 278 } while ((scratch & PCI_AGP_COMMAND_AGP) == 0 && ++timeout < 1000); 279 if ((scratch & PCI_AGP_COMMAND_AGP) == 0) 280 dev_err(&bridge->dev->dev, "can't write UniNorth AGP " 281 "command register\n"); 282 283 if (uninorth_rev >= 0x30) { 284 /* This is an AGP V3 */ 285 agp_device_command(command, (status & AGPSTAT_MODE_3_0) != 0); 286 } else { 287 /* AGP V2 */ 288 agp_device_command(command, false); 289 } 290 291 uninorth_tlbflush(NULL); 292 } 293 294 #ifdef CONFIG_PM 295 /* 296 * These Power Management routines are _not_ called by the normal PCI PM layer, 297 * but directly by the video driver through function pointers in the device 298 * tree. 299 */ 300 static int agp_uninorth_suspend(struct pci_dev *pdev) 301 { 302 struct agp_bridge_data *bridge; 303 u32 cmd; 304 u8 agp; 305 struct pci_dev *device = NULL; 306 307 bridge = agp_find_bridge(pdev); 308 if (bridge == NULL) 309 return -ENODEV; 310 311 /* Only one suspend supported */ 312 if (bridge->dev_private_data) 313 return 0; 314 315 /* turn off AGP on the video chip, if it was enabled */ 316 for_each_pci_dev(device) { 317 /* Don't touch the bridge yet, device first */ 318 if (device == pdev) 319 continue; 320 /* Only deal with devices on the same bus here, no Mac has a P2P 321 * bridge on the AGP port, and mucking around the entire PCI 322 * tree is source of problems on some machines because of a bug 323 * in some versions of pci_find_capability() when hitting a dead 324 * device 325 */ 326 if (device->bus != pdev->bus) 327 continue; 328 agp = pci_find_capability(device, PCI_CAP_ID_AGP); 329 if (!agp) 330 continue; 331 pci_read_config_dword(device, agp + PCI_AGP_COMMAND, &cmd); 332 if (!(cmd & PCI_AGP_COMMAND_AGP)) 333 continue; 334 dev_info(&pdev->dev, "disabling AGP on device %s\n", 335 pci_name(device)); 336 cmd &= ~PCI_AGP_COMMAND_AGP; 337 pci_write_config_dword(device, agp + PCI_AGP_COMMAND, cmd); 338 } 339 340 /* turn off AGP on the bridge */ 341 agp = pci_find_capability(pdev, PCI_CAP_ID_AGP); 342 pci_read_config_dword(pdev, agp + PCI_AGP_COMMAND, &cmd); 343 bridge->dev_private_data = (void *)(long)cmd; 344 if (cmd & PCI_AGP_COMMAND_AGP) { 345 dev_info(&pdev->dev, "disabling AGP on bridge\n"); 346 cmd &= ~PCI_AGP_COMMAND_AGP; 347 pci_write_config_dword(pdev, agp + PCI_AGP_COMMAND, cmd); 348 } 349 /* turn off the GART */ 350 uninorth_cleanup(); 351 352 return 0; 353 } 354 355 static int agp_uninorth_resume(struct pci_dev *pdev) 356 { 357 struct agp_bridge_data *bridge; 358 u32 command; 359 360 bridge = agp_find_bridge(pdev); 361 if (bridge == NULL) 362 return -ENODEV; 363 364 command = (long)bridge->dev_private_data; 365 bridge->dev_private_data = NULL; 366 if (!(command & PCI_AGP_COMMAND_AGP)) 367 return 0; 368 369 uninorth_agp_enable(bridge, command); 370 371 return 0; 372 } 373 #endif /* CONFIG_PM */ 374 375 static int uninorth_create_gatt_table(struct agp_bridge_data *bridge) 376 { 377 char *table; 378 char *table_end; 379 int size; 380 int page_order; 381 int num_entries; 382 int i; 383 void *temp; 384 struct page *page; 385 386 /* We can't handle 2 level gatt's */ 387 if (bridge->driver->size_type == LVL2_APER_SIZE) 388 return -EINVAL; 389 390 table = NULL; 391 i = bridge->aperture_size_idx; 392 temp = bridge->current_size; 393 size = page_order = num_entries = 0; 394 395 do { 396 size = A_SIZE_32(temp)->size; 397 page_order = A_SIZE_32(temp)->page_order; 398 num_entries = A_SIZE_32(temp)->num_entries; 399 400 table = (char *) __get_free_pages(GFP_KERNEL, page_order); 401 402 if (table == NULL) { 403 i++; 404 bridge->current_size = A_IDX32(bridge); 405 } else { 406 bridge->aperture_size_idx = i; 407 } 408 } while (!table && (i < bridge->driver->num_aperture_sizes)); 409 410 if (table == NULL) 411 return -ENOMEM; 412 413 table_end = table + ((PAGE_SIZE * (1 << page_order)) - 1); 414 415 for (page = virt_to_page(table); page <= virt_to_page(table_end); page++) 416 SetPageReserved(page); 417 418 bridge->gatt_table_real = (u32 *) table; 419 bridge->gatt_table = (u32 *)table; 420 bridge->gatt_bus_addr = virt_to_gart(table); 421 422 for (i = 0; i < num_entries; i++) 423 bridge->gatt_table[i] = 0; 424 425 flush_dcache_range((unsigned long)table, (unsigned long)table_end); 426 427 return 0; 428 } 429 430 static int uninorth_free_gatt_table(struct agp_bridge_data *bridge) 431 { 432 int page_order; 433 char *table, *table_end; 434 void *temp; 435 struct page *page; 436 437 temp = bridge->current_size; 438 page_order = A_SIZE_32(temp)->page_order; 439 440 /* Do not worry about freeing memory, because if this is 441 * called, then all agp memory is deallocated and removed 442 * from the table. 443 */ 444 445 table = (char *) bridge->gatt_table_real; 446 table_end = table + ((PAGE_SIZE * (1 << page_order)) - 1); 447 448 for (page = virt_to_page(table); page <= virt_to_page(table_end); page++) 449 ClearPageReserved(page); 450 451 free_pages((unsigned long) bridge->gatt_table_real, page_order); 452 453 return 0; 454 } 455 456 void null_cache_flush(void) 457 { 458 mb(); 459 } 460 461 /* Setup function */ 462 463 static const struct aper_size_info_32 uninorth_sizes[7] = 464 { 465 #if 0 /* Not sure uninorth supports that high aperture sizes */ 466 {256, 65536, 6, 64}, 467 {128, 32768, 5, 32}, 468 {64, 16384, 4, 16}, 469 #endif 470 {32, 8192, 3, 8}, 471 {16, 4096, 2, 4}, 472 {8, 2048, 1, 2}, 473 {4, 1024, 0, 1} 474 }; 475 476 /* 477 * Not sure that u3 supports that high aperture sizes but it 478 * would strange if it did not :) 479 */ 480 static const struct aper_size_info_32 u3_sizes[8] = 481 { 482 {512, 131072, 7, 128}, 483 {256, 65536, 6, 64}, 484 {128, 32768, 5, 32}, 485 {64, 16384, 4, 16}, 486 {32, 8192, 3, 8}, 487 {16, 4096, 2, 4}, 488 {8, 2048, 1, 2}, 489 {4, 1024, 0, 1} 490 }; 491 492 const struct agp_bridge_driver uninorth_agp_driver = { 493 .owner = THIS_MODULE, 494 .aperture_sizes = (void *)uninorth_sizes, 495 .size_type = U32_APER_SIZE, 496 .num_aperture_sizes = 4, 497 .configure = uninorth_configure, 498 .fetch_size = uninorth_fetch_size, 499 .cleanup = uninorth_cleanup, 500 .tlb_flush = uninorth_tlbflush, 501 .mask_memory = agp_generic_mask_memory, 502 .masks = NULL, 503 .cache_flush = null_cache_flush, 504 .agp_enable = uninorth_agp_enable, 505 .create_gatt_table = uninorth_create_gatt_table, 506 .free_gatt_table = uninorth_free_gatt_table, 507 .insert_memory = uninorth_insert_memory, 508 .remove_memory = agp_generic_remove_memory, 509 .alloc_by_type = agp_generic_alloc_by_type, 510 .free_by_type = agp_generic_free_by_type, 511 .agp_alloc_page = agp_generic_alloc_page, 512 .agp_alloc_pages = agp_generic_alloc_pages, 513 .agp_destroy_page = agp_generic_destroy_page, 514 .agp_destroy_pages = agp_generic_destroy_pages, 515 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 516 .cant_use_aperture = true, 517 }; 518 519 const struct agp_bridge_driver u3_agp_driver = { 520 .owner = THIS_MODULE, 521 .aperture_sizes = (void *)u3_sizes, 522 .size_type = U32_APER_SIZE, 523 .num_aperture_sizes = 8, 524 .configure = uninorth_configure, 525 .fetch_size = uninorth_fetch_size, 526 .cleanup = uninorth_cleanup, 527 .tlb_flush = uninorth_tlbflush, 528 .mask_memory = agp_generic_mask_memory, 529 .masks = NULL, 530 .cache_flush = null_cache_flush, 531 .agp_enable = uninorth_agp_enable, 532 .create_gatt_table = uninorth_create_gatt_table, 533 .free_gatt_table = uninorth_free_gatt_table, 534 .insert_memory = u3_insert_memory, 535 .remove_memory = u3_remove_memory, 536 .alloc_by_type = agp_generic_alloc_by_type, 537 .free_by_type = agp_generic_free_by_type, 538 .agp_alloc_page = agp_generic_alloc_page, 539 .agp_alloc_pages = agp_generic_alloc_pages, 540 .agp_destroy_page = agp_generic_destroy_page, 541 .agp_destroy_pages = agp_generic_destroy_pages, 542 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 543 .cant_use_aperture = true, 544 .needs_scratch_page = true, 545 }; 546 547 static struct agp_device_ids uninorth_agp_device_ids[] __devinitdata = { 548 { 549 .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP, 550 .chipset_name = "UniNorth", 551 }, 552 { 553 .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP_P, 554 .chipset_name = "UniNorth/Pangea", 555 }, 556 { 557 .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP15, 558 .chipset_name = "UniNorth 1.5", 559 }, 560 { 561 .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP2, 562 .chipset_name = "UniNorth 2", 563 }, 564 { 565 .device_id = PCI_DEVICE_ID_APPLE_U3_AGP, 566 .chipset_name = "U3", 567 }, 568 { 569 .device_id = PCI_DEVICE_ID_APPLE_U3L_AGP, 570 .chipset_name = "U3L", 571 }, 572 { 573 .device_id = PCI_DEVICE_ID_APPLE_U3H_AGP, 574 .chipset_name = "U3H", 575 }, 576 { 577 .device_id = PCI_DEVICE_ID_APPLE_IPID2_AGP, 578 .chipset_name = "UniNorth/Intrepid2", 579 }, 580 }; 581 582 static int __devinit agp_uninorth_probe(struct pci_dev *pdev, 583 const struct pci_device_id *ent) 584 { 585 struct agp_device_ids *devs = uninorth_agp_device_ids; 586 struct agp_bridge_data *bridge; 587 struct device_node *uninorth_node; 588 u8 cap_ptr; 589 int j; 590 591 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); 592 if (cap_ptr == 0) 593 return -ENODEV; 594 595 /* probe for known chipsets */ 596 for (j = 0; devs[j].chipset_name != NULL; ++j) { 597 if (pdev->device == devs[j].device_id) { 598 dev_info(&pdev->dev, "Apple %s chipset\n", 599 devs[j].chipset_name); 600 goto found; 601 } 602 } 603 604 dev_err(&pdev->dev, "unsupported Apple chipset [%04x/%04x]\n", 605 pdev->vendor, pdev->device); 606 return -ENODEV; 607 608 found: 609 /* Set revision to 0 if we could not read it. */ 610 uninorth_rev = 0; 611 is_u3 = 0; 612 /* Locate core99 Uni-N */ 613 uninorth_node = of_find_node_by_name(NULL, "uni-n"); 614 /* Locate G5 u3 */ 615 if (uninorth_node == NULL) { 616 is_u3 = 1; 617 uninorth_node = of_find_node_by_name(NULL, "u3"); 618 } 619 if (uninorth_node) { 620 const int *revprop = of_get_property(uninorth_node, 621 "device-rev", NULL); 622 if (revprop != NULL) 623 uninorth_rev = *revprop & 0x3f; 624 of_node_put(uninorth_node); 625 } 626 627 #ifdef CONFIG_PM 628 /* Inform platform of our suspend/resume caps */ 629 pmac_register_agp_pm(pdev, agp_uninorth_suspend, agp_uninorth_resume); 630 #endif 631 632 /* Allocate & setup our driver */ 633 bridge = agp_alloc_bridge(); 634 if (!bridge) 635 return -ENOMEM; 636 637 if (is_u3) 638 bridge->driver = &u3_agp_driver; 639 else 640 bridge->driver = &uninorth_agp_driver; 641 642 bridge->dev = pdev; 643 bridge->capndx = cap_ptr; 644 bridge->flags = AGP_ERRATA_FASTWRITES; 645 646 /* Fill in the mode register */ 647 pci_read_config_dword(pdev, cap_ptr+PCI_AGP_STATUS, &bridge->mode); 648 649 pci_set_drvdata(pdev, bridge); 650 return agp_add_bridge(bridge); 651 } 652 653 static void __devexit agp_uninorth_remove(struct pci_dev *pdev) 654 { 655 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 656 657 #ifdef CONFIG_PM 658 /* Inform platform of our suspend/resume caps */ 659 pmac_register_agp_pm(pdev, NULL, NULL); 660 #endif 661 662 agp_remove_bridge(bridge); 663 agp_put_bridge(bridge); 664 } 665 666 static struct pci_device_id agp_uninorth_pci_table[] = { 667 { 668 .class = (PCI_CLASS_BRIDGE_HOST << 8), 669 .class_mask = ~0, 670 .vendor = PCI_VENDOR_ID_APPLE, 671 .device = PCI_ANY_ID, 672 .subvendor = PCI_ANY_ID, 673 .subdevice = PCI_ANY_ID, 674 }, 675 { } 676 }; 677 678 MODULE_DEVICE_TABLE(pci, agp_uninorth_pci_table); 679 680 static struct pci_driver agp_uninorth_pci_driver = { 681 .name = "agpgart-uninorth", 682 .id_table = agp_uninorth_pci_table, 683 .probe = agp_uninorth_probe, 684 .remove = agp_uninorth_remove, 685 }; 686 687 static int __init agp_uninorth_init(void) 688 { 689 if (agp_off) 690 return -EINVAL; 691 return pci_register_driver(&agp_uninorth_pci_driver); 692 } 693 694 static void __exit agp_uninorth_cleanup(void) 695 { 696 pci_unregister_driver(&agp_uninorth_pci_driver); 697 } 698 699 module_init(agp_uninorth_init); 700 module_exit(agp_uninorth_cleanup); 701 702 module_param(aperture, charp, 0); 703 MODULE_PARM_DESC(aperture, 704 "Aperture size, must be power of two between 4MB and an\n" 705 "\t\tupper limit specific to the UniNorth revision.\n" 706 "\t\tDefault: 32M"); 707 708 MODULE_AUTHOR("Ben Herrenschmidt & Paul Mackerras"); 709 MODULE_LICENSE("GPL"); 710