1 /* 2 * UniNorth AGPGART routines. 3 */ 4 #include <linux/module.h> 5 #include <linux/pci.h> 6 #include <linux/init.h> 7 #include <linux/pagemap.h> 8 #include <linux/agp_backend.h> 9 #include <linux/delay.h> 10 #include <linux/vmalloc.h> 11 #include <asm/uninorth.h> 12 #include <asm/pci-bridge.h> 13 #include <asm/prom.h> 14 #include <asm/pmac_feature.h> 15 #include "agp.h" 16 17 /* 18 * NOTES for uninorth3 (G5 AGP) supports : 19 * 20 * There maybe also possibility to have bigger cache line size for 21 * agp (see pmac_pci.c and look for cache line). Need to be investigated 22 * by someone. 23 * 24 * PAGE size are hardcoded but this may change, see asm/page.h. 25 * 26 * Jerome Glisse <j.glisse@gmail.com> 27 */ 28 static int uninorth_rev; 29 static int is_u3; 30 31 #define DEFAULT_APERTURE_SIZE 256 32 #define DEFAULT_APERTURE_STRING "256" 33 static char *aperture = NULL; 34 35 static int uninorth_fetch_size(void) 36 { 37 int i, size = 0; 38 struct aper_size_info_32 *values = 39 A_SIZE_32(agp_bridge->driver->aperture_sizes); 40 41 if (aperture) { 42 char *save = aperture; 43 44 size = memparse(aperture, &aperture) >> 20; 45 aperture = save; 46 47 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) 48 if (size == values[i].size) 49 break; 50 51 if (i == agp_bridge->driver->num_aperture_sizes) { 52 dev_err(&agp_bridge->dev->dev, "invalid aperture size, " 53 "using default\n"); 54 size = 0; 55 aperture = NULL; 56 } 57 } 58 59 if (!size) { 60 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) 61 if (values[i].size == DEFAULT_APERTURE_SIZE) 62 break; 63 } 64 65 agp_bridge->previous_size = 66 agp_bridge->current_size = (void *)(values + i); 67 agp_bridge->aperture_size_idx = i; 68 return values[i].size; 69 } 70 71 static void uninorth_tlbflush(struct agp_memory *mem) 72 { 73 u32 ctrl = UNI_N_CFG_GART_ENABLE; 74 75 if (is_u3) 76 ctrl |= U3_N_CFG_GART_PERFRD; 77 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 78 ctrl | UNI_N_CFG_GART_INVAL); 79 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, ctrl); 80 81 if (uninorth_rev <= 0x30) { 82 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 83 ctrl | UNI_N_CFG_GART_2xRESET); 84 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 85 ctrl); 86 } 87 } 88 89 static void uninorth_cleanup(void) 90 { 91 u32 tmp; 92 93 pci_read_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, &tmp); 94 if (!(tmp & UNI_N_CFG_GART_ENABLE)) 95 return; 96 tmp |= UNI_N_CFG_GART_INVAL; 97 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, tmp); 98 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 0); 99 100 if (uninorth_rev <= 0x30) { 101 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 102 UNI_N_CFG_GART_2xRESET); 103 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, 104 0); 105 } 106 } 107 108 static int uninorth_configure(void) 109 { 110 struct aper_size_info_32 *current_size; 111 112 current_size = A_SIZE_32(agp_bridge->current_size); 113 114 dev_info(&agp_bridge->dev->dev, "configuring for size idx: %d\n", 115 current_size->size_value); 116 117 /* aperture size and gatt addr */ 118 pci_write_config_dword(agp_bridge->dev, 119 UNI_N_CFG_GART_BASE, 120 (agp_bridge->gatt_bus_addr & 0xfffff000) 121 | current_size->size_value); 122 123 /* HACK ALERT 124 * UniNorth seem to be buggy enough not to handle properly when 125 * the AGP aperture isn't mapped at bus physical address 0 126 */ 127 agp_bridge->gart_bus_addr = 0; 128 #ifdef CONFIG_PPC64 129 /* Assume U3 or later on PPC64 systems */ 130 /* high 4 bits of GART physical address go in UNI_N_CFG_AGP_BASE */ 131 pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_AGP_BASE, 132 (agp_bridge->gatt_bus_addr >> 32) & 0xf); 133 #else 134 pci_write_config_dword(agp_bridge->dev, 135 UNI_N_CFG_AGP_BASE, agp_bridge->gart_bus_addr); 136 #endif 137 138 if (is_u3) { 139 pci_write_config_dword(agp_bridge->dev, 140 UNI_N_CFG_GART_DUMMY_PAGE, 141 page_to_phys(agp_bridge->scratch_page_page) >> 12); 142 } 143 144 return 0; 145 } 146 147 static int uninorth_insert_memory(struct agp_memory *mem, off_t pg_start, int type) 148 { 149 int i, num_entries; 150 void *temp; 151 u32 *gp; 152 int mask_type; 153 154 if (type != mem->type) 155 return -EINVAL; 156 157 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 158 if (mask_type != 0) { 159 /* We know nothing of memory types */ 160 return -EINVAL; 161 } 162 163 if (mem->page_count == 0) 164 return 0; 165 166 temp = agp_bridge->current_size; 167 num_entries = A_SIZE_32(temp)->num_entries; 168 169 if ((pg_start + mem->page_count) > num_entries) 170 return -EINVAL; 171 172 gp = (u32 *) &agp_bridge->gatt_table[pg_start]; 173 for (i = 0; i < mem->page_count; ++i) { 174 if (gp[i]) { 175 dev_info(&agp_bridge->dev->dev, 176 "uninorth_insert_memory: entry 0x%x occupied (%x)\n", 177 i, gp[i]); 178 return -EBUSY; 179 } 180 } 181 182 for (i = 0; i < mem->page_count; i++) { 183 if (is_u3) 184 gp[i] = (page_to_phys(mem->pages[i]) >> PAGE_SHIFT) | 0x80000000UL; 185 else 186 gp[i] = cpu_to_le32((page_to_phys(mem->pages[i]) & 0xFFFFF000UL) | 187 0x1UL); 188 flush_dcache_range((unsigned long)__va(page_to_phys(mem->pages[i])), 189 (unsigned long)__va(page_to_phys(mem->pages[i]))+0x1000); 190 } 191 mb(); 192 uninorth_tlbflush(mem); 193 194 return 0; 195 } 196 197 int uninorth_remove_memory(struct agp_memory *mem, off_t pg_start, int type) 198 { 199 size_t i; 200 u32 *gp; 201 int mask_type; 202 203 if (type != mem->type) 204 return -EINVAL; 205 206 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type); 207 if (mask_type != 0) { 208 /* We know nothing of memory types */ 209 return -EINVAL; 210 } 211 212 if (mem->page_count == 0) 213 return 0; 214 215 gp = (u32 *) &agp_bridge->gatt_table[pg_start]; 216 for (i = 0; i < mem->page_count; ++i) 217 gp[i] = 0; 218 mb(); 219 uninorth_tlbflush(mem); 220 221 return 0; 222 } 223 224 static void uninorth_agp_enable(struct agp_bridge_data *bridge, u32 mode) 225 { 226 u32 command, scratch, status; 227 int timeout; 228 229 pci_read_config_dword(bridge->dev, 230 bridge->capndx + PCI_AGP_STATUS, 231 &status); 232 233 command = agp_collect_device_status(bridge, mode, status); 234 command |= PCI_AGP_COMMAND_AGP; 235 236 if (uninorth_rev == 0x21) { 237 /* 238 * Darwin disable AGP 4x on this revision, thus we 239 * may assume it's broken. This is an AGP2 controller. 240 */ 241 command &= ~AGPSTAT2_4X; 242 } 243 244 if ((uninorth_rev >= 0x30) && (uninorth_rev <= 0x33)) { 245 /* 246 * We need to set REQ_DEPTH to 7 for U3 versions 1.0, 2.1, 247 * 2.2 and 2.3, Darwin do so. 248 */ 249 if ((command >> AGPSTAT_RQ_DEPTH_SHIFT) > 7) 250 command = (command & ~AGPSTAT_RQ_DEPTH) 251 | (7 << AGPSTAT_RQ_DEPTH_SHIFT); 252 } 253 254 uninorth_tlbflush(NULL); 255 256 timeout = 0; 257 do { 258 pci_write_config_dword(bridge->dev, 259 bridge->capndx + PCI_AGP_COMMAND, 260 command); 261 pci_read_config_dword(bridge->dev, 262 bridge->capndx + PCI_AGP_COMMAND, 263 &scratch); 264 } while ((scratch & PCI_AGP_COMMAND_AGP) == 0 && ++timeout < 1000); 265 if ((scratch & PCI_AGP_COMMAND_AGP) == 0) 266 dev_err(&bridge->dev->dev, "can't write UniNorth AGP " 267 "command register\n"); 268 269 if (uninorth_rev >= 0x30) { 270 /* This is an AGP V3 */ 271 agp_device_command(command, (status & AGPSTAT_MODE_3_0) != 0); 272 } else { 273 /* AGP V2 */ 274 agp_device_command(command, false); 275 } 276 277 uninorth_tlbflush(NULL); 278 } 279 280 #ifdef CONFIG_PM 281 /* 282 * These Power Management routines are _not_ called by the normal PCI PM layer, 283 * but directly by the video driver through function pointers in the device 284 * tree. 285 */ 286 static int agp_uninorth_suspend(struct pci_dev *pdev) 287 { 288 struct agp_bridge_data *bridge; 289 u32 cmd; 290 u8 agp; 291 struct pci_dev *device = NULL; 292 293 bridge = agp_find_bridge(pdev); 294 if (bridge == NULL) 295 return -ENODEV; 296 297 /* Only one suspend supported */ 298 if (bridge->dev_private_data) 299 return 0; 300 301 /* turn off AGP on the video chip, if it was enabled */ 302 for_each_pci_dev(device) { 303 /* Don't touch the bridge yet, device first */ 304 if (device == pdev) 305 continue; 306 /* Only deal with devices on the same bus here, no Mac has a P2P 307 * bridge on the AGP port, and mucking around the entire PCI 308 * tree is source of problems on some machines because of a bug 309 * in some versions of pci_find_capability() when hitting a dead 310 * device 311 */ 312 if (device->bus != pdev->bus) 313 continue; 314 agp = pci_find_capability(device, PCI_CAP_ID_AGP); 315 if (!agp) 316 continue; 317 pci_read_config_dword(device, agp + PCI_AGP_COMMAND, &cmd); 318 if (!(cmd & PCI_AGP_COMMAND_AGP)) 319 continue; 320 dev_info(&pdev->dev, "disabling AGP on device %s\n", 321 pci_name(device)); 322 cmd &= ~PCI_AGP_COMMAND_AGP; 323 pci_write_config_dword(device, agp + PCI_AGP_COMMAND, cmd); 324 } 325 326 /* turn off AGP on the bridge */ 327 agp = pci_find_capability(pdev, PCI_CAP_ID_AGP); 328 pci_read_config_dword(pdev, agp + PCI_AGP_COMMAND, &cmd); 329 bridge->dev_private_data = (void *)(long)cmd; 330 if (cmd & PCI_AGP_COMMAND_AGP) { 331 dev_info(&pdev->dev, "disabling AGP on bridge\n"); 332 cmd &= ~PCI_AGP_COMMAND_AGP; 333 pci_write_config_dword(pdev, agp + PCI_AGP_COMMAND, cmd); 334 } 335 /* turn off the GART */ 336 uninorth_cleanup(); 337 338 return 0; 339 } 340 341 static int agp_uninorth_resume(struct pci_dev *pdev) 342 { 343 struct agp_bridge_data *bridge; 344 u32 command; 345 346 bridge = agp_find_bridge(pdev); 347 if (bridge == NULL) 348 return -ENODEV; 349 350 command = (long)bridge->dev_private_data; 351 bridge->dev_private_data = NULL; 352 if (!(command & PCI_AGP_COMMAND_AGP)) 353 return 0; 354 355 uninorth_agp_enable(bridge, command); 356 357 return 0; 358 } 359 #endif /* CONFIG_PM */ 360 361 static int uninorth_create_gatt_table(struct agp_bridge_data *bridge) 362 { 363 char *table; 364 char *table_end; 365 int size; 366 int page_order; 367 int num_entries; 368 int i; 369 void *temp; 370 struct page *page; 371 struct page **pages; 372 373 /* We can't handle 2 level gatt's */ 374 if (bridge->driver->size_type == LVL2_APER_SIZE) 375 return -EINVAL; 376 377 table = NULL; 378 i = bridge->aperture_size_idx; 379 temp = bridge->current_size; 380 size = page_order = num_entries = 0; 381 382 do { 383 size = A_SIZE_32(temp)->size; 384 page_order = A_SIZE_32(temp)->page_order; 385 num_entries = A_SIZE_32(temp)->num_entries; 386 387 table = (char *) __get_free_pages(GFP_KERNEL, page_order); 388 389 if (table == NULL) { 390 i++; 391 bridge->current_size = A_IDX32(bridge); 392 } else { 393 bridge->aperture_size_idx = i; 394 } 395 } while (!table && (i < bridge->driver->num_aperture_sizes)); 396 397 if (table == NULL) 398 return -ENOMEM; 399 400 pages = kmalloc((1 << page_order) * sizeof(struct page*), GFP_KERNEL); 401 if (pages == NULL) 402 goto enomem; 403 404 table_end = table + ((PAGE_SIZE * (1 << page_order)) - 1); 405 406 for (page = virt_to_page(table), i = 0; page <= virt_to_page(table_end); 407 page++, i++) { 408 SetPageReserved(page); 409 pages[i] = page; 410 } 411 412 bridge->gatt_table_real = (u32 *) table; 413 /* Need to clear out any dirty data still sitting in caches */ 414 flush_dcache_range((unsigned long)table, 415 (unsigned long)(table_end + PAGE_SIZE)); 416 bridge->gatt_table = vmap(pages, (1 << page_order), 0, PAGE_KERNEL_NCG); 417 418 if (bridge->gatt_table == NULL) 419 goto enomem; 420 421 bridge->gatt_bus_addr = virt_to_phys(table); 422 423 for (i = 0; i < num_entries; i++) 424 bridge->gatt_table[i] = 0; 425 426 return 0; 427 428 enomem: 429 kfree(pages); 430 if (table) 431 free_pages((unsigned long)table, page_order); 432 return -ENOMEM; 433 } 434 435 static int uninorth_free_gatt_table(struct agp_bridge_data *bridge) 436 { 437 int page_order; 438 char *table, *table_end; 439 void *temp; 440 struct page *page; 441 442 temp = bridge->current_size; 443 page_order = A_SIZE_32(temp)->page_order; 444 445 /* Do not worry about freeing memory, because if this is 446 * called, then all agp memory is deallocated and removed 447 * from the table. 448 */ 449 450 vunmap(bridge->gatt_table); 451 table = (char *) bridge->gatt_table_real; 452 table_end = table + ((PAGE_SIZE * (1 << page_order)) - 1); 453 454 for (page = virt_to_page(table); page <= virt_to_page(table_end); page++) 455 ClearPageReserved(page); 456 457 free_pages((unsigned long) bridge->gatt_table_real, page_order); 458 459 return 0; 460 } 461 462 void null_cache_flush(void) 463 { 464 mb(); 465 } 466 467 /* Setup function */ 468 469 static const struct aper_size_info_32 uninorth_sizes[] = 470 { 471 {256, 65536, 6, 64}, 472 {128, 32768, 5, 32}, 473 {64, 16384, 4, 16}, 474 {32, 8192, 3, 8}, 475 {16, 4096, 2, 4}, 476 {8, 2048, 1, 2}, 477 {4, 1024, 0, 1} 478 }; 479 480 /* 481 * Not sure that u3 supports that high aperture sizes but it 482 * would strange if it did not :) 483 */ 484 static const struct aper_size_info_32 u3_sizes[] = 485 { 486 {512, 131072, 7, 128}, 487 {256, 65536, 6, 64}, 488 {128, 32768, 5, 32}, 489 {64, 16384, 4, 16}, 490 {32, 8192, 3, 8}, 491 {16, 4096, 2, 4}, 492 {8, 2048, 1, 2}, 493 {4, 1024, 0, 1} 494 }; 495 496 const struct agp_bridge_driver uninorth_agp_driver = { 497 .owner = THIS_MODULE, 498 .aperture_sizes = (void *)uninorth_sizes, 499 .size_type = U32_APER_SIZE, 500 .num_aperture_sizes = ARRAY_SIZE(uninorth_sizes), 501 .configure = uninorth_configure, 502 .fetch_size = uninorth_fetch_size, 503 .cleanup = uninorth_cleanup, 504 .tlb_flush = uninorth_tlbflush, 505 .mask_memory = agp_generic_mask_memory, 506 .masks = NULL, 507 .cache_flush = null_cache_flush, 508 .agp_enable = uninorth_agp_enable, 509 .create_gatt_table = uninorth_create_gatt_table, 510 .free_gatt_table = uninorth_free_gatt_table, 511 .insert_memory = uninorth_insert_memory, 512 .remove_memory = uninorth_remove_memory, 513 .alloc_by_type = agp_generic_alloc_by_type, 514 .free_by_type = agp_generic_free_by_type, 515 .agp_alloc_page = agp_generic_alloc_page, 516 .agp_alloc_pages = agp_generic_alloc_pages, 517 .agp_destroy_page = agp_generic_destroy_page, 518 .agp_destroy_pages = agp_generic_destroy_pages, 519 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 520 .cant_use_aperture = true, 521 }; 522 523 const struct agp_bridge_driver u3_agp_driver = { 524 .owner = THIS_MODULE, 525 .aperture_sizes = (void *)u3_sizes, 526 .size_type = U32_APER_SIZE, 527 .num_aperture_sizes = ARRAY_SIZE(u3_sizes), 528 .configure = uninorth_configure, 529 .fetch_size = uninorth_fetch_size, 530 .cleanup = uninorth_cleanup, 531 .tlb_flush = uninorth_tlbflush, 532 .mask_memory = agp_generic_mask_memory, 533 .masks = NULL, 534 .cache_flush = null_cache_flush, 535 .agp_enable = uninorth_agp_enable, 536 .create_gatt_table = uninorth_create_gatt_table, 537 .free_gatt_table = uninorth_free_gatt_table, 538 .insert_memory = uninorth_insert_memory, 539 .remove_memory = uninorth_remove_memory, 540 .alloc_by_type = agp_generic_alloc_by_type, 541 .free_by_type = agp_generic_free_by_type, 542 .agp_alloc_page = agp_generic_alloc_page, 543 .agp_alloc_pages = agp_generic_alloc_pages, 544 .agp_destroy_page = agp_generic_destroy_page, 545 .agp_destroy_pages = agp_generic_destroy_pages, 546 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 547 .cant_use_aperture = true, 548 .needs_scratch_page = true, 549 }; 550 551 static struct agp_device_ids uninorth_agp_device_ids[] __devinitdata = { 552 { 553 .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP, 554 .chipset_name = "UniNorth", 555 }, 556 { 557 .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP_P, 558 .chipset_name = "UniNorth/Pangea", 559 }, 560 { 561 .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP15, 562 .chipset_name = "UniNorth 1.5", 563 }, 564 { 565 .device_id = PCI_DEVICE_ID_APPLE_UNI_N_AGP2, 566 .chipset_name = "UniNorth 2", 567 }, 568 { 569 .device_id = PCI_DEVICE_ID_APPLE_U3_AGP, 570 .chipset_name = "U3", 571 }, 572 { 573 .device_id = PCI_DEVICE_ID_APPLE_U3L_AGP, 574 .chipset_name = "U3L", 575 }, 576 { 577 .device_id = PCI_DEVICE_ID_APPLE_U3H_AGP, 578 .chipset_name = "U3H", 579 }, 580 { 581 .device_id = PCI_DEVICE_ID_APPLE_IPID2_AGP, 582 .chipset_name = "UniNorth/Intrepid2", 583 }, 584 }; 585 586 static int __devinit agp_uninorth_probe(struct pci_dev *pdev, 587 const struct pci_device_id *ent) 588 { 589 struct agp_device_ids *devs = uninorth_agp_device_ids; 590 struct agp_bridge_data *bridge; 591 struct device_node *uninorth_node; 592 u8 cap_ptr; 593 int j; 594 595 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); 596 if (cap_ptr == 0) 597 return -ENODEV; 598 599 /* probe for known chipsets */ 600 for (j = 0; devs[j].chipset_name != NULL; ++j) { 601 if (pdev->device == devs[j].device_id) { 602 dev_info(&pdev->dev, "Apple %s chipset\n", 603 devs[j].chipset_name); 604 goto found; 605 } 606 } 607 608 dev_err(&pdev->dev, "unsupported Apple chipset [%04x/%04x]\n", 609 pdev->vendor, pdev->device); 610 return -ENODEV; 611 612 found: 613 /* Set revision to 0 if we could not read it. */ 614 uninorth_rev = 0; 615 is_u3 = 0; 616 /* Locate core99 Uni-N */ 617 uninorth_node = of_find_node_by_name(NULL, "uni-n"); 618 /* Locate G5 u3 */ 619 if (uninorth_node == NULL) { 620 is_u3 = 1; 621 uninorth_node = of_find_node_by_name(NULL, "u3"); 622 } 623 if (uninorth_node) { 624 const int *revprop = of_get_property(uninorth_node, 625 "device-rev", NULL); 626 if (revprop != NULL) 627 uninorth_rev = *revprop & 0x3f; 628 of_node_put(uninorth_node); 629 } 630 631 #ifdef CONFIG_PM 632 /* Inform platform of our suspend/resume caps */ 633 pmac_register_agp_pm(pdev, agp_uninorth_suspend, agp_uninorth_resume); 634 #endif 635 636 /* Allocate & setup our driver */ 637 bridge = agp_alloc_bridge(); 638 if (!bridge) 639 return -ENOMEM; 640 641 if (is_u3) 642 bridge->driver = &u3_agp_driver; 643 else 644 bridge->driver = &uninorth_agp_driver; 645 646 bridge->dev = pdev; 647 bridge->capndx = cap_ptr; 648 bridge->flags = AGP_ERRATA_FASTWRITES; 649 650 /* Fill in the mode register */ 651 pci_read_config_dword(pdev, cap_ptr+PCI_AGP_STATUS, &bridge->mode); 652 653 pci_set_drvdata(pdev, bridge); 654 return agp_add_bridge(bridge); 655 } 656 657 static void __devexit agp_uninorth_remove(struct pci_dev *pdev) 658 { 659 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 660 661 #ifdef CONFIG_PM 662 /* Inform platform of our suspend/resume caps */ 663 pmac_register_agp_pm(pdev, NULL, NULL); 664 #endif 665 666 agp_remove_bridge(bridge); 667 agp_put_bridge(bridge); 668 } 669 670 static struct pci_device_id agp_uninorth_pci_table[] = { 671 { 672 .class = (PCI_CLASS_BRIDGE_HOST << 8), 673 .class_mask = ~0, 674 .vendor = PCI_VENDOR_ID_APPLE, 675 .device = PCI_ANY_ID, 676 .subvendor = PCI_ANY_ID, 677 .subdevice = PCI_ANY_ID, 678 }, 679 { } 680 }; 681 682 MODULE_DEVICE_TABLE(pci, agp_uninorth_pci_table); 683 684 static struct pci_driver agp_uninorth_pci_driver = { 685 .name = "agpgart-uninorth", 686 .id_table = agp_uninorth_pci_table, 687 .probe = agp_uninorth_probe, 688 .remove = agp_uninorth_remove, 689 }; 690 691 static int __init agp_uninorth_init(void) 692 { 693 if (agp_off) 694 return -EINVAL; 695 return pci_register_driver(&agp_uninorth_pci_driver); 696 } 697 698 static void __exit agp_uninorth_cleanup(void) 699 { 700 pci_unregister_driver(&agp_uninorth_pci_driver); 701 } 702 703 module_init(agp_uninorth_init); 704 module_exit(agp_uninorth_cleanup); 705 706 module_param(aperture, charp, 0); 707 MODULE_PARM_DESC(aperture, 708 "Aperture size, must be power of two between 4MB and an\n" 709 "\t\tupper limit specific to the UniNorth revision.\n" 710 "\t\tDefault: " DEFAULT_APERTURE_STRING "M"); 711 712 MODULE_AUTHOR("Ben Herrenschmidt & Paul Mackerras"); 713 MODULE_LICENSE("GPL"); 714