1 /* 2 * SiS AGPGART routines. 3 */ 4 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 #include <linux/init.h> 8 #include <linux/agp_backend.h> 9 #include <linux/delay.h> 10 #include "agp.h" 11 12 #define SIS_ATTBASE 0x90 13 #define SIS_APSIZE 0x94 14 #define SIS_TLBCNTRL 0x97 15 #define SIS_TLBFLUSH 0x98 16 17 #define PCI_DEVICE_ID_SI_662 0x0662 18 #define PCI_DEVICE_ID_SI_671 0x0671 19 20 static int __devinitdata agp_sis_force_delay = 0; 21 static int __devinitdata agp_sis_agp_spec = -1; 22 23 static int sis_fetch_size(void) 24 { 25 u8 temp_size; 26 int i; 27 struct aper_size_info_8 *values; 28 29 pci_read_config_byte(agp_bridge->dev, SIS_APSIZE, &temp_size); 30 values = A_SIZE_8(agp_bridge->driver->aperture_sizes); 31 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) { 32 if ((temp_size == values[i].size_value) || 33 ((temp_size & ~(0x07)) == 34 (values[i].size_value & ~(0x07)))) { 35 agp_bridge->previous_size = 36 agp_bridge->current_size = (void *) (values + i); 37 38 agp_bridge->aperture_size_idx = i; 39 return values[i].size; 40 } 41 } 42 43 return 0; 44 } 45 46 static void sis_tlbflush(struct agp_memory *mem) 47 { 48 pci_write_config_byte(agp_bridge->dev, SIS_TLBFLUSH, 0x02); 49 } 50 51 static int sis_configure(void) 52 { 53 u32 temp; 54 struct aper_size_info_8 *current_size; 55 56 current_size = A_SIZE_8(agp_bridge->current_size); 57 pci_write_config_byte(agp_bridge->dev, SIS_TLBCNTRL, 0x05); 58 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp); 59 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK); 60 pci_write_config_dword(agp_bridge->dev, SIS_ATTBASE, 61 agp_bridge->gatt_bus_addr); 62 pci_write_config_byte(agp_bridge->dev, SIS_APSIZE, 63 current_size->size_value); 64 return 0; 65 } 66 67 static void sis_cleanup(void) 68 { 69 struct aper_size_info_8 *previous_size; 70 71 previous_size = A_SIZE_8(agp_bridge->previous_size); 72 pci_write_config_byte(agp_bridge->dev, SIS_APSIZE, 73 (previous_size->size_value & ~(0x03))); 74 } 75 76 static void sis_delayed_enable(struct agp_bridge_data *bridge, u32 mode) 77 { 78 struct pci_dev *device = NULL; 79 u32 command; 80 int rate; 81 82 printk(KERN_INFO PFX "Found an AGP %d.%d compliant device at %s.\n", 83 agp_bridge->major_version, 84 agp_bridge->minor_version, 85 pci_name(agp_bridge->dev)); 86 87 pci_read_config_dword(agp_bridge->dev, agp_bridge->capndx + PCI_AGP_STATUS, &command); 88 command = agp_collect_device_status(bridge, mode, command); 89 command |= AGPSTAT_AGP_ENABLE; 90 rate = (command & 0x7) << 2; 91 92 for_each_pci_dev(device) { 93 u8 agp = pci_find_capability(device, PCI_CAP_ID_AGP); 94 if (!agp) 95 continue; 96 97 printk(KERN_INFO PFX "Putting AGP V3 device at %s into %dx mode\n", 98 pci_name(device), rate); 99 100 pci_write_config_dword(device, agp + PCI_AGP_COMMAND, command); 101 102 /* 103 * Weird: on some sis chipsets any rate change in the target 104 * command register triggers a 5ms screwup during which the master 105 * cannot be configured 106 */ 107 if (device->device == bridge->dev->device) { 108 printk(KERN_INFO PFX "SiS delay workaround: giving bridge time to recover.\n"); 109 msleep(10); 110 } 111 } 112 } 113 114 static const struct aper_size_info_8 sis_generic_sizes[7] = 115 { 116 {256, 65536, 6, 99}, 117 {128, 32768, 5, 83}, 118 {64, 16384, 4, 67}, 119 {32, 8192, 3, 51}, 120 {16, 4096, 2, 35}, 121 {8, 2048, 1, 19}, 122 {4, 1024, 0, 3} 123 }; 124 125 static struct agp_bridge_driver sis_driver = { 126 .owner = THIS_MODULE, 127 .aperture_sizes = sis_generic_sizes, 128 .size_type = U8_APER_SIZE, 129 .num_aperture_sizes = 7, 130 .configure = sis_configure, 131 .fetch_size = sis_fetch_size, 132 .cleanup = sis_cleanup, 133 .tlb_flush = sis_tlbflush, 134 .mask_memory = agp_generic_mask_memory, 135 .masks = NULL, 136 .agp_enable = agp_generic_enable, 137 .cache_flush = global_cache_flush, 138 .create_gatt_table = agp_generic_create_gatt_table, 139 .free_gatt_table = agp_generic_free_gatt_table, 140 .insert_memory = agp_generic_insert_memory, 141 .remove_memory = agp_generic_remove_memory, 142 .alloc_by_type = agp_generic_alloc_by_type, 143 .free_by_type = agp_generic_free_by_type, 144 .agp_alloc_page = agp_generic_alloc_page, 145 .agp_destroy_page = agp_generic_destroy_page, 146 .agp_type_to_mask_type = agp_generic_type_to_mask_type, 147 }; 148 149 // chipsets that require the 'delay hack' 150 static int sis_broken_chipsets[] __devinitdata = { 151 PCI_DEVICE_ID_SI_648, 152 PCI_DEVICE_ID_SI_746, 153 0 // terminator 154 }; 155 156 static void __devinit sis_get_driver(struct agp_bridge_data *bridge) 157 { 158 int i; 159 160 for (i=0; sis_broken_chipsets[i]!=0; ++i) 161 if (bridge->dev->device==sis_broken_chipsets[i]) 162 break; 163 164 if (sis_broken_chipsets[i] || agp_sis_force_delay) 165 sis_driver.agp_enable=sis_delayed_enable; 166 167 // sis chipsets that indicate less than agp3.5 168 // are not actually fully agp3 compliant 169 if ((agp_bridge->major_version == 3 && agp_bridge->minor_version >= 5 170 && agp_sis_agp_spec!=0) || agp_sis_agp_spec==1) { 171 sis_driver.aperture_sizes = agp3_generic_sizes; 172 sis_driver.size_type = U16_APER_SIZE; 173 sis_driver.num_aperture_sizes = AGP_GENERIC_SIZES_ENTRIES; 174 sis_driver.configure = agp3_generic_configure; 175 sis_driver.fetch_size = agp3_generic_fetch_size; 176 sis_driver.cleanup = agp3_generic_cleanup; 177 sis_driver.tlb_flush = agp3_generic_tlbflush; 178 } 179 } 180 181 182 static int __devinit agp_sis_probe(struct pci_dev *pdev, 183 const struct pci_device_id *ent) 184 { 185 struct agp_bridge_data *bridge; 186 u8 cap_ptr; 187 188 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP); 189 if (!cap_ptr) 190 return -ENODEV; 191 192 193 printk(KERN_INFO PFX "Detected SiS chipset - id:%i\n", pdev->device); 194 bridge = agp_alloc_bridge(); 195 if (!bridge) 196 return -ENOMEM; 197 198 bridge->driver = &sis_driver; 199 bridge->dev = pdev; 200 bridge->capndx = cap_ptr; 201 202 get_agp_version(bridge); 203 204 /* Fill in the mode register */ 205 pci_read_config_dword(pdev, bridge->capndx+PCI_AGP_STATUS, &bridge->mode); 206 sis_get_driver(bridge); 207 208 pci_set_drvdata(pdev, bridge); 209 return agp_add_bridge(bridge); 210 } 211 212 static void __devexit agp_sis_remove(struct pci_dev *pdev) 213 { 214 struct agp_bridge_data *bridge = pci_get_drvdata(pdev); 215 216 agp_remove_bridge(bridge); 217 agp_put_bridge(bridge); 218 } 219 220 #ifdef CONFIG_PM 221 222 static int agp_sis_suspend(struct pci_dev *pdev, pm_message_t state) 223 { 224 pci_save_state(pdev); 225 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 226 227 return 0; 228 } 229 230 static int agp_sis_resume(struct pci_dev *pdev) 231 { 232 pci_set_power_state(pdev, PCI_D0); 233 pci_restore_state(pdev); 234 235 return sis_driver.configure(); 236 } 237 238 #endif /* CONFIG_PM */ 239 240 static struct pci_device_id agp_sis_pci_table[] = { 241 { 242 .class = (PCI_CLASS_BRIDGE_HOST << 8), 243 .class_mask = ~0, 244 .vendor = PCI_VENDOR_ID_SI, 245 .device = PCI_DEVICE_ID_SI_5591_AGP, 246 .subvendor = PCI_ANY_ID, 247 .subdevice = PCI_ANY_ID, 248 }, 249 { 250 .class = (PCI_CLASS_BRIDGE_HOST << 8), 251 .class_mask = ~0, 252 .vendor = PCI_VENDOR_ID_SI, 253 .device = PCI_DEVICE_ID_SI_530, 254 .subvendor = PCI_ANY_ID, 255 .subdevice = PCI_ANY_ID, 256 }, 257 { 258 .class = (PCI_CLASS_BRIDGE_HOST << 8), 259 .class_mask = ~0, 260 .vendor = PCI_VENDOR_ID_SI, 261 .device = PCI_DEVICE_ID_SI_540, 262 .subvendor = PCI_ANY_ID, 263 .subdevice = PCI_ANY_ID, 264 }, 265 { 266 .class = (PCI_CLASS_BRIDGE_HOST << 8), 267 .class_mask = ~0, 268 .vendor = PCI_VENDOR_ID_SI, 269 .device = PCI_DEVICE_ID_SI_550, 270 .subvendor = PCI_ANY_ID, 271 .subdevice = PCI_ANY_ID, 272 }, 273 { 274 .class = (PCI_CLASS_BRIDGE_HOST << 8), 275 .class_mask = ~0, 276 .vendor = PCI_VENDOR_ID_SI, 277 .device = PCI_DEVICE_ID_SI_620, 278 .subvendor = PCI_ANY_ID, 279 .subdevice = PCI_ANY_ID, 280 }, 281 { 282 .class = (PCI_CLASS_BRIDGE_HOST << 8), 283 .class_mask = ~0, 284 .vendor = PCI_VENDOR_ID_SI, 285 .device = PCI_DEVICE_ID_SI_630, 286 .subvendor = PCI_ANY_ID, 287 .subdevice = PCI_ANY_ID, 288 }, 289 { 290 .class = (PCI_CLASS_BRIDGE_HOST << 8), 291 .class_mask = ~0, 292 .vendor = PCI_VENDOR_ID_SI, 293 .device = PCI_DEVICE_ID_SI_635, 294 .subvendor = PCI_ANY_ID, 295 .subdevice = PCI_ANY_ID, 296 }, 297 { 298 .class = (PCI_CLASS_BRIDGE_HOST << 8), 299 .class_mask = ~0, 300 .vendor = PCI_VENDOR_ID_SI, 301 .device = PCI_DEVICE_ID_SI_645, 302 .subvendor = PCI_ANY_ID, 303 .subdevice = PCI_ANY_ID, 304 }, 305 { 306 .class = (PCI_CLASS_BRIDGE_HOST << 8), 307 .class_mask = ~0, 308 .vendor = PCI_VENDOR_ID_SI, 309 .device = PCI_DEVICE_ID_SI_646, 310 .subvendor = PCI_ANY_ID, 311 .subdevice = PCI_ANY_ID, 312 }, 313 { 314 .class = (PCI_CLASS_BRIDGE_HOST << 8), 315 .class_mask = ~0, 316 .vendor = PCI_VENDOR_ID_SI, 317 .device = PCI_DEVICE_ID_SI_648, 318 .subvendor = PCI_ANY_ID, 319 .subdevice = PCI_ANY_ID, 320 }, 321 { 322 .class = (PCI_CLASS_BRIDGE_HOST << 8), 323 .class_mask = ~0, 324 .vendor = PCI_VENDOR_ID_SI, 325 .device = PCI_DEVICE_ID_SI_650, 326 .subvendor = PCI_ANY_ID, 327 .subdevice = PCI_ANY_ID, 328 }, 329 { 330 .class = (PCI_CLASS_BRIDGE_HOST << 8), 331 .class_mask = ~0, 332 .vendor = PCI_VENDOR_ID_SI, 333 .device = PCI_DEVICE_ID_SI_651, 334 .subvendor = PCI_ANY_ID, 335 .subdevice = PCI_ANY_ID, 336 }, 337 { 338 .class = (PCI_CLASS_BRIDGE_HOST << 8), 339 .class_mask = ~0, 340 .vendor = PCI_VENDOR_ID_SI, 341 .device = PCI_DEVICE_ID_SI_655, 342 .subvendor = PCI_ANY_ID, 343 .subdevice = PCI_ANY_ID, 344 }, 345 { 346 .class = (PCI_CLASS_BRIDGE_HOST << 8), 347 .class_mask = ~0, 348 .vendor = PCI_VENDOR_ID_SI, 349 .device = PCI_DEVICE_ID_SI_661, 350 .subvendor = PCI_ANY_ID, 351 .subdevice = PCI_ANY_ID, 352 }, 353 { 354 .class = (PCI_CLASS_BRIDGE_HOST << 8), 355 .class_mask = ~0, 356 .vendor = PCI_VENDOR_ID_SI, 357 .device = PCI_DEVICE_ID_SI_662, 358 .subvendor = PCI_ANY_ID, 359 .subdevice = PCI_ANY_ID, 360 }, 361 { 362 .class = (PCI_CLASS_BRIDGE_HOST << 8), 363 .class_mask = ~0, 364 .vendor = PCI_VENDOR_ID_SI, 365 .device = PCI_DEVICE_ID_SI_671, 366 .subvendor = PCI_ANY_ID, 367 .subdevice = PCI_ANY_ID, 368 }, 369 { 370 .class = (PCI_CLASS_BRIDGE_HOST << 8), 371 .class_mask = ~0, 372 .vendor = PCI_VENDOR_ID_SI, 373 .device = PCI_DEVICE_ID_SI_730, 374 .subvendor = PCI_ANY_ID, 375 .subdevice = PCI_ANY_ID, 376 }, 377 { 378 .class = (PCI_CLASS_BRIDGE_HOST << 8), 379 .class_mask = ~0, 380 .vendor = PCI_VENDOR_ID_SI, 381 .device = PCI_DEVICE_ID_SI_735, 382 .subvendor = PCI_ANY_ID, 383 .subdevice = PCI_ANY_ID, 384 }, 385 { 386 .class = (PCI_CLASS_BRIDGE_HOST << 8), 387 .class_mask = ~0, 388 .vendor = PCI_VENDOR_ID_SI, 389 .device = PCI_DEVICE_ID_SI_740, 390 .subvendor = PCI_ANY_ID, 391 .subdevice = PCI_ANY_ID, 392 }, 393 { 394 .class = (PCI_CLASS_BRIDGE_HOST << 8), 395 .class_mask = ~0, 396 .vendor = PCI_VENDOR_ID_SI, 397 .device = PCI_DEVICE_ID_SI_741, 398 .subvendor = PCI_ANY_ID, 399 .subdevice = PCI_ANY_ID, 400 }, 401 { 402 .class = (PCI_CLASS_BRIDGE_HOST << 8), 403 .class_mask = ~0, 404 .vendor = PCI_VENDOR_ID_SI, 405 .device = PCI_DEVICE_ID_SI_745, 406 .subvendor = PCI_ANY_ID, 407 .subdevice = PCI_ANY_ID, 408 }, 409 { 410 .class = (PCI_CLASS_BRIDGE_HOST << 8), 411 .class_mask = ~0, 412 .vendor = PCI_VENDOR_ID_SI, 413 .device = PCI_DEVICE_ID_SI_746, 414 .subvendor = PCI_ANY_ID, 415 .subdevice = PCI_ANY_ID, 416 }, 417 { 418 .class = (PCI_CLASS_BRIDGE_HOST << 8), 419 .class_mask = ~0, 420 .vendor = PCI_VENDOR_ID_SI, 421 .device = PCI_DEVICE_ID_SI_760, 422 .subvendor = PCI_ANY_ID, 423 .subdevice = PCI_ANY_ID, 424 }, 425 { } 426 }; 427 428 MODULE_DEVICE_TABLE(pci, agp_sis_pci_table); 429 430 static struct pci_driver agp_sis_pci_driver = { 431 .name = "agpgart-sis", 432 .id_table = agp_sis_pci_table, 433 .probe = agp_sis_probe, 434 .remove = agp_sis_remove, 435 #ifdef CONFIG_PM 436 .suspend = agp_sis_suspend, 437 .resume = agp_sis_resume, 438 #endif 439 }; 440 441 static int __init agp_sis_init(void) 442 { 443 if (agp_off) 444 return -EINVAL; 445 return pci_register_driver(&agp_sis_pci_driver); 446 } 447 448 static void __exit agp_sis_cleanup(void) 449 { 450 pci_unregister_driver(&agp_sis_pci_driver); 451 } 452 453 module_init(agp_sis_init); 454 module_exit(agp_sis_cleanup); 455 456 module_param(agp_sis_force_delay, bool, 0); 457 MODULE_PARM_DESC(agp_sis_force_delay,"forces sis delay hack"); 458 module_param(agp_sis_agp_spec, int, 0); 459 MODULE_PARM_DESC(agp_sis_agp_spec,"0=force sis init, 1=force generic agp3 init, default: autodetect"); 460 MODULE_LICENSE("GPL and additional rights"); 461